CN209691363U - A kind of LED drive chip - Google Patents
A kind of LED drive chip Download PDFInfo
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- CN209691363U CN209691363U CN201920651786.1U CN201920651786U CN209691363U CN 209691363 U CN209691363 U CN 209691363U CN 201920651786 U CN201920651786 U CN 201920651786U CN 209691363 U CN209691363 U CN 209691363U
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Abstract
The utility model discloses a kind of LED drive chips, including serial i/O, register, data clock for obtaining clock pins is converted into the internal clocking module of the higher grayscale clock of frequency, PWM count is according to processing module, channels drive module and reference current source, clock pins are connect with internal clocking module, internal clocking module is also connect with PWM count according to processing module, clock pins are also connect with the serial i/O, serial i/O is connected by a SRAM and PWM count according to processing module, serial i/O is also connect with register, register also respectively with the internal clocking module, PWM count is according to processing module, reference current source, the connection of channels drive module, channels drive module is also connect with the reference current source；Its effect is: by providing reliable and stable high frequency grayscale clock by chip interior, breaking through the upper limiting frequency of the outer grayscale clock of piece of traditional scheme, effectively improves the refresh rate of output picture, the user experience is improved.
Description
Technical field
The utility model relates to technical field of LED display, and in particular to a kind of LED drive chip.
Background technique
Present LED display driving IC includes channel module, and the conducting in channel is corresponding on shutdown control LED display
LED lamp bead light on and off.The time width of channel conductive needs to refer to the time span of grayscale clock, and grayscale clock is all adopted
The mode inputted with external clock, is limited to the factors such as PCB layer number, wiring width, spacing, signal interference, coupling, grayscale clock
Upper frequency limit can not improve the refresh rate of output picture in 20MHz or so, be unable to satisfy the experience requirements that user refreshes height.
Summary of the invention
To solve the above-mentioned problems, the utility model provides a kind of LED drive chip, solves in the prior art, Wu Fati
The defect of the refresh rate of height output picture.
The technical solution that the utility model is taken are as follows: a kind of LED drive chip, including for obtaining external gradation data
With the serial i/O for carrying out register configuration, register, it is higher that the data clock for obtaining clock pins is converted into frequency
The internal clocking module of grayscale clock, the PWM count for being split to the gradation data are each for controlling according to processing module
The channels drive module of road output end ON/OFF and reference current source for constant current when providing channel conductive；
The clock pins are connect with the internal clocking module, and the internal clocking module is also with the PWM count according to place
Module connection is managed, the clock pins are also connect with the serial i/O, are the input or defeated of the serial i/O gradation data
Clock signal is provided out, the serial i/O is connect with the PWM count according to processing module by a SRAM, the serial i/O also with
The register connection, the register include four road output ends, and each output end output has different output signals, and the first via is defeated
Outlet is connect with the internal clocking module, and the second road output end is connect with the PWM count according to processing module, third road output end
Connect with the channels drive module, the 4th road output end is connect with the reference current source, the channels drive module also with
The reference current source connection.
Preferably, the internal clocking module includes mode switch, phaselocked loop and the frequency divider connecting with the phaselocked loop,
The mode switch includes common end, the first output end and second output terminal；
The common end of the mode switch is connect with the clock pins, the output of the first via output end of the register
The contact that signal is used to control the mode switch is connected with the first output end or second output terminal, first output end and institute
The input terminal connection of phaselocked loop is stated, the output end of the phaselocked loop is connect with the input terminal of the frequency divider, the frequency divider
Output end is connect with the PWM count according to processing module, and the output end of the frequency divider is also connect with the second output terminal.
Preferably, the PWM count includes data-optimized module, data buffer storage and PWM count according to segmentation module according to processing module；
The data-optimized module is connect with the SRAM, the output end of register and data buffer storage respectively, the data
Caching connect with the output end of the frequency divider and PWM count according to segmentation module respectively, the PWM count according to divide module respectively with institute
The output end of the output end, register of stating frequency divider is connected with channels drive module.
Preferably, a kind of LED drive chip, which is characterized in that it further include row synchronous control signal circuit, it is described
Row synchronous control signal circuit is connect with the PWM count according to processing module.
By adopting the above technical scheme, have the advantage that the utility model proposes a kind of LED drive chip, by setting
Some internal clocking modules are provided reliable and stable high frequency grayscale clock by chip interior, break through the outer grayscale of piece of traditional scheme
The upper limiting frequency of clock effectively improves the refresh rate of output picture, and the user experience is improved.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the utility model embodiment；
Fig. 2 is the schematic diagram of internal structure of internal clocking module in Fig. 1.
Specific embodiment
In order to keep the technical problems to be solved in the utility model, technical solution and advantage clearer, below in conjunction with attached
Figure and specific embodiment are described in detail, and the following examples illustrate the utility model, but it is practical new to be not limited to this
The range of type.
Shown in referring to Fig.1, a kind of LED drive chip, including matching for obtaining external gradation data and progress register
Serial i/the O set, register, the data clock for obtaining clock pins are converted into the inside of the higher grayscale clock of frequency
Clock module, PWM count for being split to the gradation data according to processing module, for control each road output end conducting/
The channels drive module of shutdown and reference current source for constant current when providing channel conductive；
The clock pins are connect with the internal clocking module, and the internal clocking module is also with the PWM count according to place
Module connection is managed, the clock pins are also connect with the serial i/O, are the input or defeated of the serial i/O gradation data
Clock signal is provided out, the serial i/O is connect with the PWM count according to processing module by a SRAM, the serial i/O also with
The register connection, the register include four road output ends, and each output end output has different output signals, and the first via is defeated
Outlet is connect with the internal clocking module, and the second road output end is connect with the PWM count according to processing module, third road output end
Connect with the channels drive module, the 4th road output end is connect with the reference current source, the channels drive module also with
The reference current source connection.
In the present embodiment, chip is equipped with corresponding serial i/O pin and connect with external equipment, which further includes other
Pin, numerous to list herein, described carry out register configuration in text, it is to register that those skilled in the art, which are understood that,
In control word be configured, details are not described herein, the control word in the present embodiment include operating mode control word, frequency multiplication control
Word and frequency dividing control word.
In application, referring to shown in Fig. 2, the internal clocking module include mode switch, phaselocked loop and with the phaselocked loop
The frequency divider of connection, the mode switch include common end, the first output end and second output terminal；
The common end of the mode switch is connect with the clock pins, the output of the first via output end of the register
The contact that signal is used to control the mode switch is connected with the first output end or second output terminal, first output end and institute
The input terminal connection of phaselocked loop is stated, the output end of the phaselocked loop is connect with the input terminal of the frequency divider, the frequency divider
Output end is connect with the PWM count according to processing module, and the output end of the frequency divider is also connect with the second output terminal.
As seen in Figure 2, external data clock fin to internal grayscale clock fout mono- shares two accesses, and by
Register control, i.e., the control word control in register, specific signal flow are as follows:
Access 1: overtone mode, fin is after the frequency multiplication of phase locked loop of internal clocking module, then the frequency dividing through internal clocking module
Device output, obtain accurately, the higher grayscale clock fout of upper frequency limit is (in the frequency for breaking through the outer grayscale clock of traditional piece
Limit)；
Access 2: direct mode operation, the output end of frequency divider are directly connected to the second output terminal, such fin=fout,
Its response time is most short；Above two mode can be chosen as the case may be.
Further, the PWM count includes data-optimized module, data buffer storage and PWM count according to segmentation mould according to processing module
Block；
The data-optimized module is connect with the SRAM, the output end of register and data buffer storage respectively, the data
Caching connect with the output end of the frequency divider and PWM count according to segmentation module respectively, the PWM count according to divide module respectively with institute
The output end of the output end, register of stating frequency divider is connected with channels drive module, it should be noted that deposit described here
The output end of device, that is, previously described second road output end, the second road output end include two sub- road output ends, a sub- road and institute
Data-optimized module connection is stated, another sub- road is connect with the PWM count according to segmentation module.
Specifically, PWM count is split according to the gradation data that processing module is used to receive, wherein data-optimized module
For judging whether gradation data is less than the threshold value of setting, when being less than, then exported after compensating, threshold value is by register
Configuration setting；
The frequency of the grayscale clock of the data buffer storage output is updated, i.e. data in update data buffer storage；
The PWM count according to segmentation module cache for receiving data in gradation data, and by the grayscale clock frequency
Rate is split processing to the gradation data, and partitioning scheme is determined by the configuration in register.
When implementation, a kind of LED drive chip further includes row synchronous control signal circuit, the row synchronously control
Signal circuit is connect with the PWM count according to processing module, that is, realizes the control to enter a new line by outer row signal come simultaneous display, is led to
Cross PWM count according to the every paths of LEDs lamp string of processing module synchronously control switch, can avoid road paths of LEDs lamp string between display/closing when
Between it is asynchronous, influence the consistency and accuracy of LED light on and off；
Meanwhile in the present embodiment, in order to improve the performance of the driving chip, the reference current source is matched by register
It sets, constant current when conducting is provided for channel；It can prevent channels drive module from leading to local temperature mistake because of LED light on and off in this way
Gao Shi, current source is inconsistent between each channel, and then influences the consistency and accuracy of the gray scale of LED.
It is provided by chip interior reliable and stable by the application of the utility model by the internal clocking module being equipped with
High frequency grayscale clock breaks through the upper limiting frequency of the outer grayscale clock of piece of traditional scheme, effectively improves the refresh rate of output picture, mention
User experience is risen.
Here, it is to be noted that, the utility model relates to function, algorithm, method etc. be only the prior art routine
Adaptability application.Therefore, improvement of the utility model for the prior art, the connection relationship being substantially between hardware, rather than
Although it is related to some functions, algorithm, method for function, algorithm, method itself namely the utility model, but and does not include pair
The improvement that function, algorithm, method itself propose；Description of the utility model for function, algorithm, method, is in order to better
Illustrate the utility model, to better understand the utility model.
Finally, it should be noted that foregoing description is only specific embodiment of the present utility model, but the utility model
Protection scope is not limited thereto, the technical scope that anyone skilled in the art discloses in the utility model
Interior, any changes or substitutions that can be easily thought of, should be covered within the scope of the utility model.
Claims (4)
1. a kind of LED drive chip, which is characterized in that including for obtaining external gradation data and carrying out register configuration
Serial i/O, register, the data clock for obtaining clock pins are converted into the internal clocking of the higher grayscale clock of frequency
Module, the PWM count for being split to the gradation data is according to processing module, for controlling each road output end ON/OFF
Channels drive module and reference current source for constant current when providing channel conductive；
The clock pins are connect with the internal clocking module, and the internal clocking module is also with the PWM count according to processing mould
Block connection, the clock pins are also connect with the serial i/O, are mentioned for the input of the serial i/O gradation data or output
For clock signal, the serial i/O is connect with the PWM count according to processing module by a SRAM, the serial i/O also with it is described
Register connection, the register include four road output ends, and each output end output has different output signals, first via output end
It is connect with the internal clocking module, the second road output end is connect with the PWM count according to processing module, third road output end and institute
State the connection of channels drive module, the 4th road output end connect with the reference current source, the channels drive module also with it is described
Reference current source connection.
2. a kind of LED drive chip according to claim 1, which is characterized in that the internal clocking module includes mode
Switch, phaselocked loop and the frequency divider connecting with the phaselocked loop, the mode switch include common end, the first output end and second
Output end；
The common end of the mode switch is connect with the clock pins, the output signal of the first via output end of the register
Contact for controlling the mode switch is connected with the first output end or second output terminal, first output end and the lock
The input terminal of phase ring connects, and the output end of the phaselocked loop is connect with the input terminal of the frequency divider, the output of the frequency divider
End is connect with the PWM count according to processing module, and the output end of the frequency divider is also connect with the second output terminal.
3. a kind of LED drive chip according to claim 2, which is characterized in that the PWM count includes number according to processing module
According to optimization module, data buffer storage and PWM count according to segmentation module；
The data-optimized module is connect with the SRAM, the output end of register and data buffer storage respectively, the data buffer storage
Connect respectively with the output end of the frequency divider and PWM count according to segmentation module, the PWM count according to divide module respectively with described point
The output end of frequency device, the output end of register are connected with channels drive module.
4. a kind of LED drive chip according to claim 3, which is characterized in that it further include row synchronous control signal circuit,
The row synchronous control signal circuit is connect with the PWM count according to processing module.
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| CN201920651786.1U CN209691363U (en) | 2019-05-08 | 2019-05-08 | A kind of LED drive chip |
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| CN201920651786.1U CN209691363U (en) | 2019-05-08 | 2019-05-08 | A kind of LED drive chip |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111105748A (en) * | 2020-01-10 | 2020-05-05 | 深圳市富满电子集团股份有限公司 | LED display method and device based on gamma table |
| CN112967670A (en) * | 2021-03-03 | 2021-06-15 | 北京集创北方科技股份有限公司 | Display driving method, device and chip, display device and storage medium |
| CN113851074A (en) * | 2020-06-28 | 2021-12-28 | 深圳市明微电子股份有限公司 | LED driving pulse modulation method and device |
| WO2023020361A1 (en) * | 2021-08-18 | 2023-02-23 | 重庆康佳光电技术研究院有限公司 | Grayscale compensation circuit, display apparatus, and grayscale compensation method |
-
2019
- 2019-05-08 CN CN201920651786.1U patent/CN209691363U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111105748A (en) * | 2020-01-10 | 2020-05-05 | 深圳市富满电子集团股份有限公司 | LED display method and device based on gamma table |
| CN113851074A (en) * | 2020-06-28 | 2021-12-28 | 深圳市明微电子股份有限公司 | LED driving pulse modulation method and device |
| WO2022001580A1 (en) * | 2020-06-28 | 2022-01-06 | 深圳市明微电子股份有限公司 | Led drive pulse modulation method and apparatus |
| US11783759B2 (en) | 2020-06-28 | 2023-10-10 | Shenzhen Sunmoon Microelectronics Co., Ltd. | Method and device of LED driving pulse modulation |
| CN112967670A (en) * | 2021-03-03 | 2021-06-15 | 北京集创北方科技股份有限公司 | Display driving method, device and chip, display device and storage medium |
| WO2023020361A1 (en) * | 2021-08-18 | 2023-02-23 | 重庆康佳光电技术研究院有限公司 | Grayscale compensation circuit, display apparatus, and grayscale compensation method |
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Address after: 518000 1701, building 1, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen City, Guangdong Province Patentee after: Fuman microelectronics Group Co.,Ltd. Address before: 518000, 18 floor, west corner, Nong Yuan Road Times Technology Building, Xiangmi Lake street, Shenzhen, Guangdong, Futian District Patentee before: FINE MADE MICROELECTRONICS GROUP CO.,LTD. |
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Address after: 518000, Building 101, Fuman Microelectronics Group Co., Ltd., Intersection of Renmin East Road and Shouhe Road, Jinsha Community, Kengzi Street, Pingshan District, Shenzhen City, Guangdong Province Patentee after: Fuman microelectronics Group Co.,Ltd. Country or region after: China Address before: 518000 1701, building 1, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen City, Guangdong Province Patentee before: Fuman microelectronics Group Co.,Ltd. Country or region before: China |