JPH08340498A - Luminance controller - Google Patents

Abstract

PURPOSE: To automatically correct the variation in luminance to a constant value when a frame frequency varies. CONSTITUTION: When image data are inputted from some image input equipment to the control part of a display device, a VSYNC cycle count part 11 counts cycles of VSYNC in the image data by using a basic clock CLK1 that the counter part has inside previously, a count data latch part 12 latches the count data, and a division part 13 divides its data by a set value of gradations to calculate by what number the basic clock needs to be divided. According to the arithmetic result, a frequency division part 14 divides the frequency of the basic clock to generate an illumination time control clock. An illumination time control signal generation part 5 resamples luminance data with the illumination time control clock to hold the luminance of display constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a brightness control device, and more particularly to a brightness control device for a display device which controls brightness in response to changes in frame frequency.

[0002]

2. Description of the Related Art A conventional brightness control device will be described with reference to the drawings.

FIG. 3 is a circuit diagram showing a conventional example.

In FIG. 3, this conventional example shows an actual flat plate 1-1.
The disclosure of Japanese Patent Publication No. 59469 is disclosed, in which the brightness of a cathode ray tube is manually set by a brightness adjustment signal, the contrast of the cathode ray tube is manually set by a contrast adjustment signal, and a plurality of frame frequencies can be arbitrarily selected In the display device, brightness adjustment signal generating means (brightness change circuits 112a to 112d, brightness adjustment circuit 1) for generating the plurality of brightness adjustment signals preset corresponding to the plurality of frame frequencies, respectively.
4) and a contrast adjustment signal generating means (contrast changing circuit 111) for generating a plurality of contrast adjustment signals set in advance corresponding to each of the plurality of frame frequencies.
a-111d, a contrast adjustment circuit 114), and when any one of the plurality of frame frequencies is selected, a frame frequency selection signal indicating the selected frame frequency is generated by the brightness adjustment signal generating means and the contrast adjustment signal generation. A frame frequency selecting means (frame frequency selecting circuit 110) for supplying the brightness adjusting signal and the contrast adjusting signal corresponding to the selected frame frequency, and switching the plurality of frame frequencies. However, the brightness and the contrast were always constant.

In the conventional brightness control device, if the brightness data is constant when the frame frequency changes, the lighting time between VSYNC and VSYNC does not change and the brightness also changes, as shown in FIG. Or adjust according to the settings in the register or the above, Kaikaihei 1-1
As shown in Japanese Patent Publication No. 59469, brightness adjustment is manually performed for some preset frame frequencies that are internally adjusted.

[0006]

As described above, in the conventional brightness control device, when the frame frequency of the input image changes (such as changing the image input device), the brightness also changes. However, there is a problem that the brightness data must be manually adjusted (switch / volume control or register setting) from the outside to make a delicate adjustment manually so as to keep the ratio of the lighting time between VSYNC and VSYNC constant. . Moreover, if the correction is not performed, the brightness also changes each time the frame frequency of the input image data changes (such as changing the image input device), so that there is the problem that the adjustment must be performed manually each time. there were.

[0007]

The brightness control device of the present invention counts the period of an input vertical synchronizing signal with a basic clock and divides the count value by a preset gradation to determine the basic clock. Control clock generation means for dividing or calculating a dividing number, dividing the basic clock based on the dividing number to generate a lighting time control clock, and controlling input brightness data by the lighting time control clock And a control signal generating means for generating a lighting time control signal.

The orbit control device of the present invention comprises a vertical synchronizing signal cycle counter section for counting the cycle of an input vertical synchronizing signal with a basic clock, and a count data latch for latching the count value of the output of the vertical synchronizing signal cycle counter section. And a latch data division unit that calculates a frequency division number by which the basic clock is divided by dividing the count value latched by the count data latch unit by a preset gray scale, A dividing unit that divides the basic clock based on the fractional number to generate a lighting time control clock, and a lighting time control signal that controls the brightness data to be input by the lighting time control clock to generate a lighting time control signal. And a generator.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Referring to FIG. 1, a brightness control device 1 of the present embodiment.
Is a VSYNC cycle counter section 11 that counts the cycle of the input vertical synchronizing signal (VSYNC) with the basic clock CLK1 and a count data latch section 12 that latches the output count value of this VSYNC cycle counting section 11.
And a latch data division unit 13 that calculates a frequency division number by which the basic clock CLK1 should be divided by dividing the value of the latch data latched by the count data latch unit 12 by a preset gradation. , Latch data division unit 13
Generated from the frequency dividing unit 14 which divides the basic clock CLK1 based on the frequency division number of the output of the above to generate the lighting time control clock, and the lighting time control clock and a display device (not shown) to which this embodiment is applied. And a lighting time control signal generator 15 for generating a lighting time control signal according to the brightness data.

FIG. 2 is a diagram showing the timing when the frame frequency changes in this embodiment.

Next, the operation of this embodiment will be described with reference to FIGS.
Will be described with reference to.

When image data is input from a certain image input device to the control unit of the display device to which the present embodiment is applied, the basic clock CLK1 which internally has the cycle of VSYNC in the image data is used, The VSYNC cycle counter unit 11 counts and outputs to the count data latch unit 12. The output data is latched by the count data latch unit 12 and output to the latch data division unit 13. By dividing the latched data by the preset gradation value in the latched data division unit 13, the basic clock CL
The frequency division of K1 is calculated, and the calculation result is output to the frequency divider 14. The frequency division unit 14 divides the basic clock CLK1 based on the calculation result to generate a lighting time control clock and outputs it to the lighting time control signal generation unit 15. The lighting time control signal generation unit 15 resamples the luminance data generated inside the display device by using the lighting time control clock to adjust the lighting time control so that the ratio between VSYNC and VSYNC becomes constant. A signal is generated.

For example, with 256 gradations and luminance data of 128
If so, the count value of the VSYNC cycle is
In the case of 4608, the count result is latched by the count data latch unit 12, and the latch data division unit 13
Is divided by the gradation at (4608/256 = 18),
As a result, the dividing unit 14 divides the basic clock CLK1 to generate a lighting time control clock, and the lighting time control signal generation unit 15 generates a lighting time control signal based on the clock and the luminance data (128 × 18 = 230
4). In this case, the ratio of the lighting time between VSYNC and VSYNC is 2304/4608 = 0.5, which is 50.
You can see that it is%.

Similarly, when the count value of the cycle of VSYNC is 5120, the latch data division unit 13 is used as described above.
Is calculated (5120/256 = 20), the frequency division section 14 generates a lighting time control clock, and the lighting time control signal generation section 15 generates a lighting time control signal (128 × 20). = 2560). VSY in this case
The ratio of the lighting time between NC and VSYNC is 2560.
/5120=0.5, which is 50% as in the case.

As described above, even when the frame frequency of the input image is changed (image input device is changed, etc.), VSYNC to VSYNC can be obtained without manual fine adjustment from the outside.
It is possible to keep the ratio of the lighting time to the NC constant, eliminate the change in luminance, and keep the brightness constant.

[0018]

As described above, according to the present invention, the frequency of the basic clock is divided by counting the period of the input vertical synchronizing signal with the basic clock and dividing the count value by a preset gradation. A control clock generation unit that calculates a frequency division number and divides a basic clock based on the frequency division number to generate a lighting time control clock, and controls the input brightness data with the lighting time control clock to generate a lighting time control signal. In the case where the frame frequency of the input image data is changed (change of the image input device, etc.) in the display device in which the brightness is controlled by the pulse width modulation (PWM) method by including the control signal generating means for generating There is an effect that the image input device can be changed without manually adjusting for the change of the brightness each time.

Further, since the brightness control is automatically performed internally instead of manually, the error of the adjustment which is considered to occur when the manual adjustment is made does not occur, and the number of manually operated parts is reduced, so that the adjustment is performed. It has the effect of making it easier.

Further, since there is no need for manual adjustment when the image input device is changed, there is an effect that connection with various image input devices can be facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing an example of timing when a frame frequency is changed in the present embodiment.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a diagram showing an example of timing when a conventional frame frequency is changed.

[Explanation of symbols]

 1 Brightness Control Device 11 VSYNC Cycle Counter 12 Count Data Latch 13 Latch Data Divider 14 Frequency Divider 15 Lighting Time Control Signal Generator

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Naoki Kaneko 1-1-1, Shinurashima-cho, Kanagawa-ku, Yokohama, Kanagawa Prefecture NEC Robot Engineering Co., Ltd.

Claims (2)

[Claims] 1. A cycle of an input vertical synchronizing signal is counted by a basic clock, and the count value is divided by a preset gradation to calculate a frequency division number for dividing the basic clock. Control clock generation means for generating a lighting time control clock by dividing the basic clock based on a frequency, and control signal generation for controlling input brightness data with the lighting time control clock to generate a lighting time control signal. And a brightness control device. 2. A vertical synchronization signal cycle counter section for counting the cycle of an input vertical synchronization signal with a basic clock, a count data latch section for latching the count value of the output of this vertical synchronization signal cycle counter section, and this count data. A latch data division unit that calculates a frequency division number by which to divide the basic clock by dividing the count value latched by the latch unit by a preset gradation, and based on the fraction number A frequency division unit that divides the basic clock to generate a lighting time control clock; and a lighting time control signal generation unit that controls the input brightness data with the lighting time control clock to generate a lighting time control signal. A brightness control device characterized by.