CN112953536A - Adjustable gain dynamic amplifying device with calibration circuit and method - Google Patents
Adjustable gain dynamic amplifying device with calibration circuit and method Download PDFInfo
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- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
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Abstract
An adjustable gain dynamic amplifying device with a calibration circuit and a method thereof are provided, which comprises the following steps: the circuit comprises a calibration input voltage circuit, a dynamic amplifier, a variable load capacitor array and a dynamic comparator which are controlled by digital signals, wherein the input end of the dynamic amplifier is connected with the calibration input voltage circuit, the output end of the dynamic amplifier is respectively connected with the variable load capacitor array and the dynamic comparator, a comparison result signal of the dynamic comparator is connected with the variable load capacitor array, and switch combinations for switching circuit topological connection are arranged between the calibration input voltage circuit and the dynamic amplifier, between the dynamic amplifier and the dynamic comparator and between the dynamic amplifier and an external working circuit. The invention has smaller area, lower power consumption and high calibration precision; the calibration loop output signal controls the load of the dynamic amplifier, realizes the gain calibration of the dynamic amplifier, solves the problem that the traditional calibration method cannot be applied to the dynamic amplifier, and realizes the gain of the dynamic amplifier to be kept stable under PVT.
Description
Technical Field
The invention relates to the technology in the field of semiconductor devices, in particular to an adjustable gain dynamic amplification device with a calibration circuit and a method.
Background
The Dynamic Amplifier (DA) is a circuit which is controlled by a clock to realize a voltage amplification function, and the power consumption of the DA is lower than that of a traditional operational amplifier and has the characteristic that the power consumption changes along with the frequency, so that the DA is widely applied to a noise shaping successive approximation type analog-to-digital converter and a pipeline analog-to-digital converter.
The defects of the existing dynamic amplifier after the gain is adjusted and the defects which need to be solved urgently are as follows: the existing gain adjusting method needs to manually input a control signal to adjust the gain after the gain of the dynamic amplifier is obtained through measurement, and cannot realize automatic calibration; existing gain calibration methods require additional amplifier or other circuit overhead that increases power consumption and area and may present mismatch problems; the existing traditional amplifier calibration method cannot be applied to a dynamic amplifier.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the adjustable gain dynamic amplification device with the calibration circuit and the method thereof, the same dynamic amplifier is multiplexed by a calibration loop and a working channel, and a dynamic comparator and digital logic are used for replacing a high gain amplifier, so that the area is smaller, the power consumption is lower, and the calibration precision is high; the output signal of the calibration loop controls the load of the dynamic amplifier, realizes the gain calibration of the dynamic amplifier, solves the problem that the traditional calibration method cannot be applied to the dynamic amplifier, and realizes that the gain of the dynamic amplifier is kept stable under different Process corners, power supply voltages and temperatures (PVT).
The invention is realized by the following technical scheme:
the invention relates to an adjustable gain dynamic amplifying device with a calibration circuit, which comprises: calibrating an input voltage circuit, a dynamic amplifier, a digital signal controlled variable load capacitor array, and a dynamic comparator, wherein: the input end of the dynamic amplifier is connected with the calibration input voltage circuit, the output end of the dynamic amplifier is respectively connected with the variable load capacitor array and the dynamic comparator, the comparison result signal of the dynamic comparator is connected with the variable load capacitor array, and switch combinations for switching circuit topology connection are arranged between the calibration input voltage circuit and the dynamic amplifier, between the dynamic amplifier and the dynamic comparator and between the dynamic amplifier and the external working circuit.
The switch combination comprises eight switches which are respectively arranged at the positive and negative input and output ends of the dynamic amplifier; the method specifically comprises the following steps: four comparison result signal control switches and four comparison result negation signal control switches, wherein: the first and second comparison result signal control switches are arranged between the calibration input voltage circuit and the dynamic amplifier, the first and second non-signal control switches are arranged between the dynamic amplifier and the dynamic comparator, and the third and fourth comparison result signal control switches and the comparison result inverting signal control switch are respectively arranged between the dynamic amplifier and the external working circuit.
When the comparison result signal is at high level, the first to fourth comparison result signals control the switch to be switched on, and simultaneously the first to fourth comparison result negation signals control the switch to be switched off, so that the dynamic amplifier works in the calibration loop. At this time, the calibration input voltage circuit, the comparison result signal control switch, the dynamic amplifier, the dynamic comparator and the variable load capacitor array jointly form a calibration loop.
When the comparison result signal is in a low level, the first comparison result signal, the second comparison result signal, the third comparison result signal, the fourth comparison result signal. At the moment, the comparison result inverting signal controls the switch, the dynamic amplifier and the external working circuit to jointly form a working path.
The dynamic amplifier is a transistor differential amplifier.
The dynamic comparator is a transistor differential pair dynamic comparator.
The variable load capacitor array comprises: the binary system that connects gradually subtracts method counter, binary code commentaries on classics temperature code's transcoder and a negative terminal and the positive terminal output load capacitance group that a plurality of grounded capacitance branch road that has the switch is parallelly connected to be constituteed, wherein: the binary subtraction counter outputs a binary signal to the transcoder, and the transcoder outputs a plurality of control signals respectively to be connected with the switches in the capacitance branch circuits.
The invention relates to a foreground calibration method of the gain-adjustable dynamic amplifier, which automatically finishes calibration when a system is powered on, namely, a calibration input voltage circuit generates calibration input voltage, the voltage is compared with reference voltage in a dynamic comparator after passing through the calibrated dynamic amplifier, and the comparison result is used for a variable load capacitor array to adjust the load of the dynamic amplifier to change the gain of the dynamic amplifier.
Technical effects
The invention integrally solves the problem that the prior dynamic amplifier gain adjustment method needs to manually input a control signal and cannot realize automatic calibration; the existing dynamic amplifier gain calibration method requires additional amplifier or other circuit overhead, which increases power consumption and area and may cause mismatch problems; the traditional amplifier gain calibration method cannot be applied to the problem of a dynamic amplifier.
Compared with the prior art, the calibrated dynamic amplifier can work in a calibration loop and a working path, namely the calibration loop and the working path multiplex the same dynamic amplifier. By the method, the power consumption and the area of a circuit can be saved, the problem of mismatch between the calibrated dynamic amplifier and the dynamic amplifier used for calibration does not exist, and the calibration precision is high.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a system timing diagram;
in the figure: CLK1And CLK2Being clock signals of dynamic amplifiers, CLKDynamic comparatorBeing the clock signal of a dynamic comparator, CLKcaliA clock signal that is a variable load capacitor array;
FIG. 3 is a schematic diagram of a dynamic amplifier;
FIG. 4 is a dynamic comparator;
fig. 5 is a digital signal controlled capacitor array.
Detailed Description
As shown in fig. 1, the present embodiment relates to an adjustable gain dynamic amplifying apparatus with a calibration circuit, which includes: calibrating the input voltage circuit, the dynamic amplifier 140, the digital signal controlled variable load capacitor array 170, and the dynamic comparator 160, wherein: the input end of the dynamic amplifier 140 is connected to the calibration input voltage circuit, the output end of the dynamic amplifier 140 is connected to the variable load capacitor array 170 and the dynamic comparator 160, respectively, the output end of the dynamic comparator 160 is connected to the variable load capacitor array 170, and switch combinations for switching circuit topology connection are arranged between the calibration input voltage circuit and the dynamic amplifier 140, between the dynamic amplifier 140 and the dynamic comparator 160, and between the dynamic amplifier 140 and the external working circuit 150.
The calibration input voltage circuit comprises: four divider resistors connected in series, wherein: the first to fourth voltage-dividing resistors 110.1-110.4 are all R in resistance value and are used for generating a calibration input voltage of the Dynamic Amplifier (DA); the lower end of the fourth voltage-dividing resistor 110.4 is connected with the bias voltage V of the dynamic amplifier 140biasThe upper end of the first voltage dividing resistor 110.1 is connected with a bias voltage Vbias+ reference voltage Vref。
The switch combination comprises: four OP signal controlled switches 120.1-120.4 and four OP non-signal controlled switches 130.1-130.4, wherein: the first and second OP signal control switches are disposed between the calibration input voltage circuit and the dynamic amplifier 140, the first and second non-signal control switches are disposed between the dynamic amplifier 140 and the dynamic comparator 160, and the third and fourth OP signal control switches and the OP non-signal control switches are disposed between the dynamic amplifier 140 and the external operating circuit 150, respectively.
The two positive input signals of the dynamic comparator 160 are respectively IP and VbiasThe input signals of the two reverse input ends are IN and V respectivelybias+Vref(ii) a The two differential outputs are an OP signal and an ON signal, respectively, and the OP signal is output to the variable load capacitor array 170.
The variable load capacitor array 170 controlled by the digital signal is respectively connected to the output terminals VP and VN of the dynamic amplifier 140 and receives the OP signal and CLKcaliAnd (5) controlling signals.
When the OP signal is high, the first to fourth OP signals control the switches 120.1-120.4 to be turned on, and the first to fourth OP non-signal control switches 130.1-130.4 to be turned off, so that the dynamic amplifier operates in the calibration loop. At this time, the calibration input voltage circuit 110, the OP signal control switch 120, the dynamic amplifier 140, the dynamic comparator 160, and the variable load capacitor array 170 together form a calibration loop.
When the OP signal is at a low level, the first to fourth OP signal control switches 120.1-120.4 are turned off, and the first to fourth OP non-signal control switches 130.1-130.4 are turned on, so that the dynamic amplifier operates in the working path. At this time, the OP non-signal control switch 130, the dynamic amplifier 140 and the external operating circuit 150 together form an operating path.
The voltage dividing resistor 110.1-the voltage dividing resistor 110.4 of the voltage dividing resistor string may also be composed of other resistors with the same resistance, and the OP signal control switch 120.1 and the OP signal control switch 120.2 may also be connected to other positions of the resistor string, as long as the voltage difference can satisfy the above-mentioned calibration logic.
As shown in FIG. 3, the dynamic amplifier 140 includes a differential amplifier composed of four transistors 141, 142, 145, 146 and an input transistor 147, and the dynamic amplifier operates at two clock signals CLK1And CLK2The actuated switches 143 and 144 operate under control.
When the first clock signal CLK1At low level, the dynamic amplifier is reset. The input transistor 147 is turned off while the first and second transistors 141 and 142 are turned on, and the power supply voltage charges the load capacitance of two nodes VP and VN to V via the first and second transistors 141 and 142DD。
When the clock signal CLK1And CLK2While high, the dynamic amplifier is operating, switches 143 and 144 are conducting, and VP and VN are discharging via third and fourth transistors 145 and 146 at a rate dependent on the size of RP and RN, with VN discharging at a rate greater than VP when RP is greater than RN, and vice versa.
When the first clock signal CLK1Is high level and the second clock signal CLK2At low powerAt normal times, the voltages at the two points VP and VN are in a hold state.
The gain of the dynamic amplifier after calibration may not be equal to 4, and when the gain after calibration is other values, the connection mode of the divider resistor 110.1 and the divider resistor 110.4 needs to be modified.
As shown in FIG. 4, the dynamic comparator is a transistor differential pair dynamic comparator that is at CLKDynamic comparatorAnd the operation is controlled.
When CLK is appliedDynamic comparatorAt low, the dynamic comparator is reset and the power supply voltage charges the two nodes of the OP signal and ON signal to V via transistors 167.1 and 167.2DDWhile transistors 166.1, 166.2, 168.1, 168.2 are all off.
When CLK is appliedDynamic comparatorAt high, the dynamic comparator is operated, and the OP signal and the ON signal are discharged via 161, 162, 163, 164, transistors 165.1, 165.2, 166.1, 166.2 at a rate dependent ON the magnitude of the input signal to the input transistor.
When the sum of the input voltages of the transistors 161 and 162 is greater than the sum of the input voltages 163 and 164, the ON signal discharge rate is greater than the OP signal, so that the gate terminal voltage of the transistor 165.2 is lower than the gate terminal voltage of the transistor 165.1, and the OP signal discharge rate is further reduced until the transistor 168.2 is turned ON, and finally the OP signal is at a high level and the ON signal is at a low level; and vice versa.
As shown in fig. 5, the variable load capacitor array 170 includes: a 4-bit binary subtraction counter 172, a 4-bit binary code-to-thermometer code transcoder 174, and a negative and positive output load capacitor banks 176.1 and 176.2 formed by a plurality of grounded switched capacitor branches connected in parallel, wherein: the binary subtraction counter 172 outputs a 4-bit binary signal to the transcoder 174, which outputs a plurality of control signals respectively to connect with the switches in the capacitive branches; the variable load capacitor array has switches 171 and CLK applied by OP signalcaliAnd the operation is controlled.
When the OP signal is at high level, the variable load capacitor array is at CLKcaliUnder the control of the dynamic amplifier gradually reduces the negative of the dynamic amplifierTerminal and positive terminal output load capacitance banks 176.1 and 176.2;
when OP signal is at low level, load capacitance of dynamic amplifier is not influenced by CLKcaliThe load capacitance banks 176.1 and 176.2 remain unchanged.
The 4-bit binary subtraction counter 172 outputs 1111 when reset and 1 when the clock rising edge comes.
The 4-bit binary code to thermometer code transcoder 174 outputs thermometer codes 175.1-175.16 to the negative and positive terminals respectively, and outputs load capacitor banks 176.1 and 176.2.
The negative and positive side output load capacitor banks 176.1 and 176.2 include: a grounded fixed capacitor C1And a plurality of parallel-connected earthed capacitors C with switches2A branch circuit; example C216 thermometer codes 175.1-175.16 are used for controlling the on-off of the switch, namely the corresponding C2Whether or not to ground.
When 175.1-175.16 are high, C on the corresponding bit2To the VP or VN terminal as part of the dynamic amplifier load. C2And C1The larger the relative proportion of (C), the larger the calibration range of the gain of the dynamic amplifier, and the present embodiment needs to ensure that 16C are obtained2And when the VP or VN is completely switched in, the gain of the dynamic amplifier is smaller than the calibrated target gain.
The calibration accuracy of the variable load capacitor array may take other values, and the number of bits 172, 174, 176.1, and 176.2 may need to be modified to match the calibration accuracy.
The variable load capacitor arrays 176.1 and 176.2. 16 capacity values thereof are C2The capacitance of (2) may also be of different sizes, for example, the last capacitance value is taken as a relatively large value to increase the calibration range, so as to prevent the target gain from exceeding the calibration range after calibration.
The embodiment relates to the foreground calibration method of the dynamic amplifier, wherein the calibration is performed when the system is powered on, and the dynamic amplifier can normally work after the calibration is completed. When the system is powered on, each module is in a reset state, and the OP signal is at a high level, so that the dynamic amplifier is in a calibration loop.
The calibration input voltage circuit divider resistor 110 generates the input of the dynamic amplifier, in this embodiment, the calibration input voltage circuit divider resistor 110 is composed of 4 resistors, the input terminals RP and RN of the dynamic amplifier are connected to the two ends of the fourth divider resistor 110.4, and the target gain of the dynamic amplifier after calibration is 4.
In this embodiment, the RP terminal voltage is Vbias+1/4VrefRN terminal voltage is VbiasThe voltage difference between the two ends is 1/4VrefAfter being amplified by the dynamic amplifier, the difference between the output terminals VP and VN is about the actual gain of the dynamic amplifier multiplied by 1/4VrefIN this case, VP is the input IP of the dynamic comparator, and VN is the input IN of the dynamic comparator. When the dynamic comparator is reset, the output OP signal and the output ON signal are both high level, and when the dynamic comparator is in work, if the sum of the input voltages of the positive end is greater than the sum of the input voltages of the negative end, namely IP and VbiasThe sum is greater than IN and Vbias+VrefAnd if the sum is less than the predetermined value, the OP signal is kept at a high level and the ON signal is changed to a low level. Otherwise, the OP signal goes low and the ON signal remains high. In this example, if the actual gain of the dynamic amplifier is greater than the calibrated target gain, the OP signal is at a high level and the ON signal is at a low level; otherwise, if the actual gain of the dynamic amplifier is smaller than the calibrated target gain, the OP signal is at a low level, and the ON signal is at a high level. Because the gain of the dynamic amplifier is inversely proportional to the load capacitance, the load capacitance of the dynamic amplifier is the maximum value during resetting in the embodiment, if the calibration range is large enough, the actual gain of the dynamic amplifier is smaller than the calibrated target gain, the OP signal keeps high level, and the CLK signal is CLKcaliThe dynamic amplifier load capacitance is reduced by one unit under control of the signal. This is the end of the first calibration period.
In the next calibration period, the above steps are repeated until the load capacitance of the dynamic amplifier is reduced to make the actual gain of the dynamic amplifier greater than the calibrated target gain, the OP signal output becomes low level, the load capacitance of the dynamic amplifier does not change any more, meanwhile, the dynamic amplifier is disconnected from the calibration loop, the switch OP non-signal control switch 130 is turned on, and the dynamic amplifier is connected in the working loop and enters the normal working state. At this point, the calibration is complete.
As shown in fig. 2, for the timing diagram of the system and the voltage variation of the important node, in the period 210, the dynamic amplifier and the dynamic comparator are both in the reset state, and the OP signal, the ON signal, VP, and VN are all high level. During the period 220, the dynamic amplifier operates with its output voltages VP and VN dropping at a rate that depends on the magnitude of the input signals RP and RN and the magnitude of the load capacitance. At the beginning of the 230 time period, the operation of the dynamic amplifier is finished, the voltages of the outputs VP and VN are maintained, and the dynamic comparator is operated, and the OP signal and the ON signal become corresponding values according to the comparison result. During the 240 time period, the variable load capacitor array is operated, and the digital logic in the variable load capacitor array determines whether to reduce the load capacitance of the dynamic amplifier according to the value of the OP signal. And after the 240 time period is finished, resetting the dynamic amplifier and the dynamic comparator, completing a calibration period, and if the calibration is not finished, entering the 210 stage again, and circulating the steps.
The dynamic amplifier and the dynamic comparator are reset once in each calibration period, and the variable load capacitor array is reset once only when the chip is powered on.
Through specific practical experiments, the gain of the calibrated dynamic amplifier under the standard conditions of tt process angle, 55 ℃ and standard power supply voltage is 8.4. The gains of the two-phase current transformer are measured under 27 different PVT conditions, and the minimum gain is 5.8 under the ss process angle, the temperature of 125 ℃ and the power supply voltage which is 5 percent lower than the standard power supply voltage; the gain is maximum at ss process angle, -45 deg.C, and a supply voltage 5% higher than the standard supply voltage, 10.6. The maximum gain variation is about 31%. By using the calibration method of the present invention, the calibrated target gain is 8, 8 identical resistors are used to generate the calibrated input voltage, the capacitance of C1 in the variable load capacitor array is about 367f, and the capacitance of C2 is 64, each capacitance is about 17f, and the gain is 8.11 under the standard condition after calibration, and the maximum gain variation is about 2.5% under 27 different PVT conditions.
Gain compensation method of existing dynamic amplifier, its compensated gainThe ratio of the variation to the temperature variation is generally 3X 10-2The ratio of gain variation to temperature variation after calibration of the present invention is about 1.52 × 10 at a variation of the same power supply voltage around%/deg.C-2% at. Since the present invention is an integrated calibration system, the above effects can be achieved by virtue of the integrated system architecture and calibration concept.
The foregoing embodiments may be modified in many different ways by those skilled in the art without departing from the spirit and scope of the invention, which is defined by the appended claims and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (9)
1. An adjustable gain dynamic amplification device having a calibration circuit, comprising: calibrating an input voltage circuit, a dynamic amplifier, a digital signal controlled variable load capacitor array, and a dynamic comparator, wherein: the input end of the dynamic amplifier is connected with the calibration input voltage circuit, the output end of the dynamic amplifier is respectively connected with the variable load capacitor array and the dynamic comparator, a comparison result signal of the dynamic comparator is connected with the variable load capacitor array, and switch combinations for switching circuit topology connection are arranged between the calibration input voltage circuit and the dynamic amplifier, between the dynamic amplifier and the dynamic comparator and between the dynamic amplifier and an external working circuit, so that the working path and the calibration loop share the same dynamic amplifier.
2. The dynamic amplifier apparatus with adjustable gain of claim 1, wherein the switch combination comprises eight switches respectively disposed at the positive and negative input/output terminals of the dynamic amplifier; the method specifically comprises the following steps: four comparison result signal control switches and four comparison result negation signal control switches, wherein: the first and second comparison result signal control switches are arranged between the calibration input voltage circuit and the dynamic amplifier, the first and second non-signal control switches are arranged between the dynamic amplifier and the dynamic comparator, and the third and fourth comparison result signal control switches and the comparison result inverting signal control switch are respectively arranged between the dynamic amplifier and the external working circuit;
when the comparison result signal is at a high level, the first comparison result signal, the second comparison result signal, the third comparison result signal, the fourth comparison result signal, the first comparison result signal, the second comparison result signal, the third comparison result signal, the fourth comparison result signal; at the moment, the calibration input voltage circuit, the comparison result signal control switch, the dynamic amplifier, the dynamic comparator and the variable load capacitor array jointly form a calibration loop;
when the comparison result signal is in a low level, the first comparison result signal, the second comparison result signal, the third comparison result signal, the fourth comparison result signal, the third comparison result signal; at the moment, the comparison result is inverted, the signal control switch, the dynamic amplifier and the external working circuit jointly form a working path.
3. The dynamic adjustable gain amplifier with calibration circuit as claimed in claim 1, wherein said variable load capacitor array comprises: the binary system that connects gradually subtracts method counter, binary code commentaries on classics temperature code's transcoder and a negative terminal and the positive terminal output load capacitance group that a plurality of grounded capacitance branch road that has the switch is parallelly connected to be constituteed, wherein: the binary subtraction counter outputs a binary signal to the transcoder, and the transcoder outputs a plurality of control signals respectively to be connected with the switches in the capacitance branch circuits.
4. The dynamic adjustable gain amplifier with calibration circuit as claimed in claim 1, wherein said calibration input voltage circuit comprises: four divider resistors connected in series, wherein: the first to fourth voltage dividing resistors are used for generating a calibration input voltage of the dynamic amplifier; the lower end of the fourth voltage-dividing resistor is connected with the bias voltage V of the dynamic amplifierbiasThe upper end of the first voltage dividing resistor is connected with a bias voltage Vbias+ reference voltage Vref。
5. According to claim1 the adjustable gain dynamic amplifying device with the calibration circuit is characterized in that input signals of two positive input ends of the dynamic comparator are respectively IP and VbiasThe input signals of the two reverse input ends are IN and V respectivelybias+Vref(ii) a The two differential outputs are respectively an OP signal and an ON signal, and the OP signal is output to the variable load capacitor array; the variable load capacitor array is respectively connected with the output ends VP and VN of the dynamic amplifier and receives OP signals and CLKcaliAnd (5) controlling signals.
6. The dynamic adjustable gain amplifier with calibration circuit of claim 1, wherein the dynamic amplifier comprises a differential amplifier consisting of four transistors and an input transistor, the dynamic amplifier operating under the switching and control of two clock signals CLK and CLK.
7. The dynamic adjustable gain amplifier with calibration circuit of claim 1, wherein the dynamic comparator is a differential pair of transistors dynamic comparator, the dynamic comparator being in CLKDynamic comparatorAnd the operation is controlled.
8. The dynamic adjustable gain amplifier with calibration circuit as claimed in claim 1, wherein said variable load capacitor array comprises: the 4-bit binary system that connect gradually subtracts method counter, 4-bit binary system code to the transcoder of thermometer code and negative terminal and the positive end output load capacitance group that a plurality of grounded capacitance branch road that has the switch is parallelly connected to be constituteed, wherein: the binary subtraction counter outputs a binary signal to the transcoder, and the transcoder outputs a plurality of control signals respectively to be connected with the switches in the capacitance branch circuits; the variable load capacitor array switches and CLK under the action of OP signalcaliAnd the operation is controlled.
9. A foreground calibration method for an amplifying device according to any one of the preceding claims, wherein a calibration input voltage is generated by a voltage dividing resistor, the calibration input voltage is compared with a reference voltage in a dynamic comparator after passing through a calibrated dynamic amplifier, the comparison result is used as an input of a variable load capacitor array, and the variable load capacitor array changes the gain of the dynamic amplifier by changing the load of the dynamic amplifier.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101465649A (en) * | 2007-12-19 | 2009-06-24 | 中国科学院微电子研究所 | Comparator with adjustable reference voltage |
| CN101656519A (en) * | 2009-08-13 | 2010-02-24 | 捷顶微电子（上海）有限公司 | Calibration circuit of RC filter and method |
| CN103095279A (en) * | 2012-11-13 | 2013-05-08 | 苏州磐启微电子有限公司 | Received signal strength indicator with digital output and low power consumption functions |
| US20130214946A1 (en) * | 2012-02-16 | 2013-08-22 | Renesas Electronics Corporation | A/D Converter and Method for Calibrating the Same |
| CN108023571A (en) * | 2016-10-31 | 2018-05-11 | 深圳市中兴微电子技术有限公司 | One kind calibration circuit and calibration method |
| CN109150181A (en) * | 2018-08-28 | 2019-01-04 | 中科芯集成电路股份有限公司 | A kind of self-alignment 12bit SAR ADC structure and method for self-calibrating |
-
2019
- 2019-12-11 CN CN201911265186.2A patent/CN112953536B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101465649A (en) * | 2007-12-19 | 2009-06-24 | 中国科学院微电子研究所 | Comparator with adjustable reference voltage |
| CN101656519A (en) * | 2009-08-13 | 2010-02-24 | 捷顶微电子（上海）有限公司 | Calibration circuit of RC filter and method |
| US20130214946A1 (en) * | 2012-02-16 | 2013-08-22 | Renesas Electronics Corporation | A/D Converter and Method for Calibrating the Same |
| CN103095279A (en) * | 2012-11-13 | 2013-05-08 | 苏州磐启微电子有限公司 | Received signal strength indicator with digital output and low power consumption functions |
| CN108023571A (en) * | 2016-10-31 | 2018-05-11 | 深圳市中兴微电子技术有限公司 | One kind calibration circuit and calibration method |
| CN109150181A (en) * | 2018-08-28 | 2019-01-04 | 中科芯集成电路股份有限公司 | A kind of self-alignment 12bit SAR ADC structure and method for self-calibrating |
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