CN114499424A - Differential amplifier applied to two-stage analog-to-digital converter, calibration circuit and calibration method - Google Patents

Differential amplifier applied to two-stage analog-to-digital converter, calibration circuit and calibration method Download PDF

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CN114499424A
CN114499424A CN202111514356.3A CN202111514356A CN114499424A CN 114499424 A CN114499424 A CN 114499424A CN 202111514356 A CN202111514356 A CN 202111514356A CN 114499424 A CN114499424 A CN 114499424A
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current
amplifier
differential
group
voltage
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胡伟波
薛明艺
张星
邓新伟
肖知明
王美玉
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Nankai University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45197—Pl types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/372—Noise reduction and elimination in amplifier

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Abstract

The invention discloses a differential amplifier, a calibration circuit and a calibration method for a two-stage analog-to-digital converter, wherein the differential amplifier comprises a first group of input geminate transistors, a second group of current mirrors, a third group of current mirrors, a current source, a first output resistor and a second output resistor; the first set of input pair tubes comprises a first mos tube and a second mos tube; the differential amplifier adopts an open-loop structure, can quickly amplify differential input voltage, and can obtain accurate and stable voltage value in a short time. The gain of the amplifier is determined by the resistance ratio, and the gain of the amplifier can be accurately adjusted by adjusting the resistance ratio, so that the amplifier is suitable for different circuit requirements.

Description

Differential amplifier, calibration circuit and calibration method applied to two-stage analog-to-digital converter
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a differential amplifier, a calibration circuit and a calibration method for a two-stage analog-to-digital converter.
Background
In recent years, new information technologies such as big data, artificial intelligence, internet of things and the like are rapidly developed, and deep influence is brought to the economic society. These techniques have evolved without the need for large amounts of data acquisition, quantification and processing. Data quantization is an integral loop in the whole data processing flow and determines the quantity and quality of the whole data circulation. Data quantization is to convert an analog signal into a digital signal; the circuit that performs the conversion of the analog signal to the digital signal is called an analog-to-digital converter. The analog-to-digital converter includes a pipeline analog-to-digital converter, a successive approximation analog-to-digital converter, an oversampling analog-to-digital converter, and the like.
The existing methods for realizing differential voltage amplification generally have two types, one is an open-loop basic fully differential operational amplifier structure, and the other is to realize differential voltage amplification in an operational amplifier negative feedback mode.
The open-loop basic fully-differential operational amplifier structure is shown in FIG. 1, and the gain of the operational amplifier is
Av＝gm1*(ro1||ro3)
Wherein, gm1Denotes the input tube M1 transconductance, ro1And ro3Representing the output resistance of the M1 and M3 tubes. The gain of the basic fully differential operational amplifier structure is determined by the transconductance and the output resistance of the tube, and the transconductance and the output resistance of the tube are easily influenced and hardly kept constant, so that the gain of the structure is difficult to accurately set and is not easy to flexibly adjust according to the actual circuit design requirement.
The structure of a fully differential negative feedback amplifier is shown in fig. 2. The differential voltage amplification mode realized by the negative feedback mode usually needs to use an operational amplifier with large gain and high precision, the operational amplifier is in closed-loop negative feedback connection, and then the voltage multiplying amplification function is realized by resistors (R and Rf) which are externally connected in proportion. The precision of the amplification factor depends on the performance of the operational amplifier and the resistance matching, the accurate voltage amplification can be realized only when the operational amplifier is close to an ideal operational amplifier, and the precision of the amplification factor depends on the open-loop gain of the operational amplifier. High performance, high accuracy, high gain operational amplifiers consume significant cost.
The existing circuit structure for realizing differential voltage amplification has certain problems. Firstly, for a basic fully differential operational amplifier structure, the gain of the structure is determined by the transconductance of an amplifier tube and the output resistance of an output tube, so that the precise control and flexible adjustment of the amplification factor are difficult to realize, and the application range is small. Secondly, for a fully differential operational amplifier circuit connected in a negative feedback manner, when differential voltage amplification is realized, a high-gain and high-precision operational amplifier is required to be used, so that accurate voltage amplification can be accurately realized. Third, the speed of amplifiers based on negative feedback tends to be slow, requiring a wide bandwidth of their operational amplifiers on the one hand, and a long time to obtain stable results on the other hand. Furthermore, amplifier amplification based on negative feedback is limited by the open loop gain of the operational amplifier. In addition, the high-precision and high-gain operational amplifier is complex in circuit, large in scale, prone to occupy large area and high in cost. When the full differential operational amplifier circuit is applied to amplifying the residual voltage of the analog-to-digital converter, the full differential operational amplifier circuit connected in a negative feedback mode is difficult to integrate in a chip.
Disclosure of Invention
Therefore, an object of the present invention is to provide a differential amplifier, a calibration circuit, and a calibration method for a two-stage analog-to-digital converter, in which the differential amplifier adopts an open-loop structure, and can realize rapid amplification of a differential input voltage, and obtain an accurate and stable voltage value in a short time.
In order to achieve the above object, the present invention provides a differential amplifier for a two-stage analog-to-digital converter, which includes a first set of input pair transistors, a second set of current mirrors, a third set of current mirrors, a current source, a first output resistor, and a second output resistor; the first set of input pair tubes comprises a first mos tube and a second mos tube;
the grid electrode of the first mos tube is connected with the positive phase differential input signal, and the source electrode of the first mos tube is connected with the second group of current mirrors; the drain electrode is connected with a current source; the first output resistor is connected with the second group of current mirrors, and the other end of the first output resistor is a differential output end of the amplifier;
the grid electrode of the second mos tube is connected with the inverted differential input signal, and the source electrode of the second mos tube is connected with the third group of current mirrors; the drain electrode of the second mos tube is connected with a current source; the second output resistor is connected with the third group of current mirrors, and the other end of the second output resistor is the other differential output end of the amplifier.
Further preferably, the second set of current mirrors is a cascode current mirror structure formed by an even number of identical MOS transistors.
Further preferably, the third group of current mirrors is a cascode current mirror structure formed by an even number of identical MOS transistors.
Further preferably, the current source is a Cascode current source structure formed by an even number of identical MOS transistors, and is configured to provide bias currents to the first MOS transistor and the second MOS transistor, respectively.
Further preferably, the device further comprises a bias circuit for acquiring a bias voltage; the bias circuit is used for converting the input bias current into 3 paths of bias voltages, wherein the first path of bias voltage and the second path of bias voltage are respectively used for triggering the current source to provide the bias current; and the third bias voltage is used for biasing the common-gate tube of the second group of current mirrors and the third group of current mirrors, so that the second group of current mirrors and the third group of current mirrors work in a saturation region.
The invention also provides a correction circuit of the differential voltage amplifier, which is used for correcting the input end mismatch voltage of the differential voltage amplifier and comprises a comparator, a plurality of groups of selection switches and a binary current source, wherein the input of each selection switch in the plurality of groups of selection switches is connected with one branch of the calibration current source, and the outputs of the plurality of groups of selection switches are respectively connected to the drain terminals of the input pair transistors M1 or M2.
Further preferably, the number of the selection switches in the plurality of sets of selection switches is set as follows:
and determining the total current value of the current source used by the calibration circuit through the total mismatch voltage range of the differential voltage amplifier in the simulation test.
And distributing the current values in each current source branch according to an equal ratio sequence with a common ratio of 2 according to the minimum value of the current flowing in the current source branch when the selection switch is switched on until the sum of all the current values is equal to or just greater than the total current value, wherein the number of the selection switches is the number of terms of the equal ratio sequence.
The invention also provides a correction method of the differential voltage amplifier, which is used for correcting the differential voltage amplifier and comprises the following steps:
s1, short-circuiting the input of the amplifier to the common-mode voltage, and measuring the mismatch voltage and noise amplified and output by the amplifier;
s2, comparing the output results VOP and VON of the amplifier by using a comparator, and outputting a high level or a low level; if the comparator outputs a high level, a first branch (IC) of the current source is switched by a selection switch in a first set of switch arraysn) Connecting to one side of a second mos tube; if the comparator outputs a low level, the first branch (IC) is connectedn) Attached to one side of the first mos tube;
s3, the output voltage of the amplifier is sent to the comparator for comparison again, and the second branch (IC) of the current source is connected by one selection switch in the second group of switch array according to the comparison result of the comparatorn-1) And gating, repeating the second step process until all current source branches are connected with the first mos tube or the second mos tube, and finishing calibration.
Compared with the prior art, the differential amplifier, the calibration circuit and the calibration method for the two-stage analog-to-digital converter disclosed by the application have at least the following advantages:
1. the amplifier provided by the design adopts an open-loop structure, can quickly amplify differential input voltage, and can obtain accurate and stable voltage value in a short time.
2. The gain of the amplifier provided by the design is determined by the resistance ratio, and the gain of the amplifier can be accurately adjusted by adjusting the resistance ratio, so that the amplifier is suitable for different circuit requirements. The amplification factor of the amplifier is accurate and is not influenced by the transconductance of the input pair transistors. The operational amplifier independent of high open loop gain is convenient for on-chip integration, and can be used as an intermediate amplifier connected with two-stage or multi-stage analog-to-digital converters.
Drawings
Fig. 1 is a diagram of a basic fully differential operational amplifier of an open loop provided in the background art;
FIG. 2 is a diagram of a fully differential negative feedback operational amplifier architecture provided in the prior art;
FIG. 3 is a schematic diagram of a differential amplifier for a two-stage analog-to-digital converter provided in the background art;
FIG. 4 is an overall block diagram of a differential amplifier for a two-stage analog-to-digital converter provided herein;
fig. 5 is a schematic block diagram of a one-time calibration technique provided by the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the detailed description.
As shown in fig. 3, an embodiment of an aspect of the present invention provides a differential amplifier for a two-stage analog-to-digital converter, which includes a first set of input pair transistors (M1, M2), a second set of current mirrors (M3, M4), a third set of current mirrors (M5, M6), and a current source. The current source comprises two branches (branch I1 and branch I2), a first output resistor R1 and a second output resistor R2; the first set of input pair tubes comprises a first mos tube M1 and a second mos tube M2.
The gate of the first mos transistor M1 is connected to a positive phase differential input signal VIP, and the source is connected to a second set of input pair transistors (M3, M4); the drain electrode is connected with a current source I1; the first output resistor R1 is connected with the second group of current mirrors (M3, M4), and one end of the first output resistor R1 is a differential output end VOP of the amplifier.
The grid electrode of the second mos tube M2 is connected with an inverted differential input signal, and the source electrode of the second mos tube M2 is connected with a third group of current mirrors (M5 and M6); the drain electrode of the second mos tube M2 is connected with a current source I2; the second output resistor R2 is connected with a third group of current mirrors (M5, M6), and one end of the second output resistor R2 is the other differential output end V0N of the amplifier.
M1 and M2 are input pair transistors that receive the positive side input voltage VIP and the negative side input voltage VIN, respectively. The current sources I1 and I2 are generated by Cascode current mirrors, and the current magnitude is the same, i.e., I1 is I2.
And (3) carrying out differential input on signals VIN and VIP through two groups of source followers consisting of M1-2 and I1-2 to obtain VSN and VSP, wherein the VSP-VSN is quite close to the VIP-VIN. The voltage difference generates a current on the bridge resistor R, and the current is:
Figure BDA0003406317630000061
when I1 is I2 is I0, the magnitude of the current flowing through M5 is: i5 ═ I0-IR, and the magnitude of the current flowing through M4 was: i4 ═ I0+ IR. The ratio of the preset output resistors R1 and R2 to the bridge resistor R is K. Since M3-M4, M5-M6 form two sets of current mirrors, generating mirror currents IR1 ═ I4, IR2 ═ I5, the output voltages are:
VOP＝I4*R1＝(I0+IR)*K*R
VON＝I5*R1＝(I0-IR)*K*R
the output voltage difference is therefore:
VOP-VON＝2*IR*K*R＝2K(VSP-VSN)
namely, it is
VOP-VON≈2K(VIP-VIN)
The gain of the amplifier is thus obtained as:
Figure BDA0003406317630000062
therefore, the input differential voltage generates current on the resistor R0, and the current flows through the output resistor through the current mirror, so that the differential output voltage with accurate multiple can be generated. The differential voltage amplifier can change the gain of the amplifier by changing the ratio of the output resistor to the bridge resistor, thereby realizing the flexible adjustability of the gain of the amplifier and simply and effectively amplifying the residual voltage by a certain multiple.
As shown in fig. 4, the overall structure of the differential voltage amplifier proposed by the present design mainly includes two parts: a bias circuit and an amplifier input-output circuit. The input signal of the bias circuit is a bias current IBIAS, which is given from the outside and is mainly used for generating amplifier input stage Cascode tube bias voltages VBN1, VBN2 and VBP 3.
In this embodiment, the second and third sets of current mirrors are all cascode current mirror structures formed by an even number of identical MOS transistors.
The current source is a Cascode current source structure formed by even number of same MOS tubes and used for providing bias current for the first MOS tube and the second MOS tube respectively.
The bias circuit is used for converting the input bias current into 3 paths of bias voltages, wherein the first path of bias voltage and the second path of bias voltage are respectively used for triggering the current source to provide the bias current; and the third bias voltage is used for biasing the common-gate tube of the second group of current mirrors and the third group of current mirrors, so that the second group of current mirrors and the third group of current mirrors work in a saturation region.
The differential voltage amplifier mainly comprises eight pairs of MOS tubes and three resistors. In the input-output circuit of the amplifier, the input pair transistors PM1 and PM2 receive external differential input signals VIP and VIN. At the input end of the amplifier, a Cascode current source structure (NM 1-NM 4) is adopted in the design to provide bias currents I1 and I2 for input pair transistors PM1 and PM2, wherein gates of NM1 and NM2 are connected with a bias voltage VBN2 output by a bias circuit, and gates of NM3 and NM4 are connected with a bias voltage VBN1 output by the bias circuit. PM5 to PM6 and PM9 to PM10 form a cascode current mirror structure, and provide mirror current IR2, I5 to output resistor R2; PM 3-PM 4 and PM 7-PM 8 form a cascode current mirror structure, and provide mirror current IR1 (equal to I4) for output resistor R1. Furthermore, three resistors in the amplifier structure are used for realizing accurate generation of amplification factors of the amplifier, and the amplifier structure comprises two output resistors R1 and R2 and a bridge resistor R, and an output resistor R1 is equal to R2; the gain of the amplifier is accurately adjusted by adjusting the ratio of the output resistance to the bridge resistance R.
When the amplifier works, firstly, VBN1 and VBN2 provide bias voltages for current mirrors NM1 to NM4, the current mirrors are used for mirror copying the current mirror on the left side, and the sizes of NM2 and NM1 are ensured to be identical, and the sizes of NM3 and NM4 are identical, so that currents I1 and I2 with the same size can be generated and provided for input pair transistors PM1 and PM2 respectively, and the current size I1 is equal to I2 equal to I0, without considering process deviation.
Assuming that the voltage at the positive input terminal is greater than that at the negative input terminal, that is, VIP > VIN, according to the characteristic that the gain of the source follower is 1, VSP is VIP, and VSN is VIN. VSP > VSN, resulting in a current IR from right to left across the bridge resistance R, IR ═ VSP-VSN)/R. According to kirchhoff's current law, I4 ═ IR + I1 and I5 ═ I2-IR are available.
PM5, PM6, PM9 and PM10 constitute a cascode current mirror, and PM5 and PM6 are the same size, and PM9 and PM10 are the same size. The VBP3 is used for providing a gate bias voltage for the common gate tubes PM 5-PM 6, and ensuring that the PM5 tubes and the PM6 tubes work in a saturation region. Further, the cascode current mirror can ensure that the currents flowing through the PM5 side and the PM6 side are identical, i.e., IR2 is I5. Similarly, for a cascode current mirror consisting of PM3, PM4, PM7, and PM8, there is IR1 ═ I4.
From ohm's law, the voltage drop across the resistor R1 is VOP IR 1R 1I 4R 1. The voltage drop across the resistor R2 is VON IR 2R 2I 5R 2. In the present design, R1 ═ R2 is designed. In addition, VOP and VON are a positive phase output voltage and a negative phase output voltage of the differential voltage amplifier, respectively. Further, VOP-VON ═ 2K (VIP-VIN) can be derived, i.e., the gain of the differential voltage amplifier is 2K.
As shown in fig. 5, this patent also proposes a one-time calibration technique to eliminate the mismatch voltage of the amplifier, mainly calibrating the equivalent input mismatch voltage of the amplifier. FIG. 5 is a schematic block diagram of a one-time calibration technique including a comparator, sets of selection switches and their corresponding binary current sources. The input end of each selector switch in the multiple groups of selector switches is connected with one branch in the calibration current source, and in addition, the selector switches also need a calibration control circuit to control the turn-off of the selector switches.
Further preferably, the number of the selection switches in the multiple groups of selection switches is set according to the following method:
and determining the total current value of the calibration current source by simulating and testing the mismatch voltage total range of the differential voltage amplifier.
And distributing the current values in each current source branch according to an equal ratio sequence with a common ratio of 2 according to the minimum value of the current flowing in the current source branch when the selection switch is switched on until the sum of all the current values is equal to or just greater than the total current value, wherein the number of the selection switches is the number of terms of the equal ratio sequence.
The specific implementation can comprise the following steps: first, the amplifier was tested by monte carlo simulation for the range of mismatch voltage under non-calibrated conditions.
Second, the total current of the calibration module can be determined from the range of mismatch voltages obtained from the simulation. In the calibration module, each group of switches corresponds to one current source. The current sources corresponding to all the groups of switches are added to form the total current.
Thirdly, the current corresponding to each branch current source corresponds to a mismatch voltage range capable of being calibrated. The minimum current value of one current source is generally determined first, and the current values of the other current sources are increased in binary. The minimum branch current source setting criteria are: the current source has a corresponding mismatch voltage range capable of being calibrated smaller than a minimum weight voltage of the second-stage analog-to-digital converter.
Fourthly, the minimum current value of the current source is determined, and the number of the switches can be determined according to the total current and the binary proportional relation among the branch current sources.
For example: the total current is 15uA, and the minimum current is determined to be 0.5uA, then a total of 5 current sources, i.e. corresponding to 5 sets of switches, have current values of 8uA,4uA,2uA,1uA,0.5uA, and a total of 15.5 uA. ,
the invention also provides a correction method of the differential voltage amplifier, which is used for correcting the differential voltage amplifier and comprises the following steps:
s1, short-circuiting the input of the amplifier to the common-mode voltage, and measuring the output mismatch voltage and noise after amplification by the amplifier;
s2, comparing the output results VOP and VON of the amplifier by using a comparator, and outputting a high level or a low level; if the comparator outputs a high level, a selection switch S in the first group of switch arrays is usedNFirst branch (IC) of current sourcen) Connecting to one side of a second mos tube; if the comparator outputs a low level, the first branch (IC) is connectedn) Attached to one side of the first mos tube;
s3, the output voltage of the amplifier is sent to the comparator for comparison again, and the second branch (IC) of the current source is connected by one selection switch in the second group switch array according to the comparison result of the comparatorn-1) And gating, repeating the second step process until all current source branches are connected with the first mos tube or the second mos tube, and finishing calibration. After the calibration is completed, the voltage difference at the output end of the amplifier is the calibrated mismatch voltage. By adjusting the calibration range of the calibration current source, the number of the current source branches and the proportion of the current sources, the mismatch voltage can be controlled within a reasonable range, and the influence of mismatch errors and noise of the amplifier on the second-stage analog-to-digital converter can be reduced as much as possible. The overall calibration process resembles the successive approximation principle.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (9)

1. A differential amplifier for a two-stage analog-to-digital converter is characterized by comprising a first group of input pair transistors, a second group of current mirrors, a third group of current mirrors, a current source, a first output resistor and a second output resistor; the first set of input pair tubes comprises a first mos tube and a second mos tube;
the grid electrode of the first mos tube is connected with the positive phase differential input signal, and the source electrode of the first mos tube is connected with the second group of current mirrors; the drain electrode is connected with a current source; the first output resistor is connected with the second group of current mirrors, and the other end of the first output resistor is a differential output end of the amplifier;
the grid electrode of the second mos tube is connected with the inverted differential input signal, and the source electrode of the second mos tube is connected with the third group of current mirrors; the drain electrode of the second mos tube is connected with a current source; the second output resistor is connected with the third group of current mirrors, and one end of the second output resistor is the other differential output end of the amplifier.
2. A differential amplifier for a two-stage analog-to-digital converter as claimed in claim 1, characterized in that said second set of current mirrors is a cascode current mirror structure formed by an even number of identical MOS transistors.
3. The differential amplifier of claim 1, wherein the third set of current mirrors is a cascode current mirror structure formed from an even number of identical MOS transistors.
4. A differential amplifier for a two-stage analog-to-digital converter as claimed in claim 1, characterized in that said current source is a Cascode current source structure formed by an even number of identical MOS transistors for providing bias currents for the first MOS transistor and the second MOS transistor, respectively.
5. The differential amplifier for a two-stage analog-to-digital converter according to claim 4, further comprising a bias circuit for obtaining a bias voltage;
the bias circuit is used for converting the input bias current into 3 paths of bias voltages, wherein the first path of bias voltage and the second path of bias voltage are respectively used for triggering the current source to provide the bias current; and the third bias voltage is used for biasing the common-gate tube in the second group of current mirrors and the third group of current mirrors, so that the second group of current mirrors and the third group of current mirrors work in a saturation region.
6. A correction circuit for a differential voltage amplifier for correcting the differential voltage amplifier as claimed in any one of claims 1 to 5, comprising a comparator, a plurality of sets of selection switches, and a binary current source, wherein an input terminal of each selection switch of the plurality of sets of selection switches is connected to one branch of the current source of the amplifier, and outputs of the plurality of sets of selection switches are connected to drain terminals of the pair of input transistors M1 or M2, respectively.
7. The correction circuit of claim 6, further comprising a calibration control circuit, said calibration control circuit being connected to the plurality of sets of selection switches for sequentially controlling the turning on and off of the plurality of sets of selection switches.
8. The correction circuit of a differential voltage amplifier according to claim 6, wherein the number of the selection switches in the plurality of sets of selection switches is set as follows:
determining the total current value of a current source used by the calibration circuit through a total mismatch voltage range of a simulation test differential voltage amplifier;
and distributing the current values in each current source branch according to an equal ratio sequence with a common ratio of 2 according to the minimum value of the current flowing in the current source branch when the selection switch is switched on until the sum of all the current values is equal to or just greater than the total current value, wherein the number of the selection switches is the number of terms of the equal ratio sequence.
9. A method of correcting a differential voltage amplifier according to any one of claims 1 to 5, comprising the steps of:
s1, short-circuiting the input of the amplifier to the common-mode voltage, and measuring the output mismatch voltage and noise after amplification by the amplifier;
s2, comparing the output results VOP and VON of the amplifier by using a comparator, and outputting a high level or a low level; if the comparator outputs a high level, a first branch (IC) of the current source is switched by a selection switch in a first set of switch arraysn) Connecting to one side of a second mos tube; if the comparator outputs a low level, the first branch (IC) is connectedn) Attached to one side of the first mos tube;
s3, the output voltage of the amplifier is sent to the comparator for comparison again, and the second branch (IC) of the current source is connected by one selection switch in the second group of switch array according to the comparison result of the comparatorn-1) Gating and repeating the second step until all current source branches are equal toAnd establishing connection between the first mos tube and the second mos tube, and finishing calibration.
CN202111514356.3A 2021-12-13 2021-12-13 Differential amplifier applied to two-stage analog-to-digital converter, calibration circuit and calibration method Pending CN114499424A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115580248A (en) * 2022-11-10 2023-01-06 江苏谷泰微电子有限公司 Precision differential amplifier with adjustable output common mode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115580248A (en) * 2022-11-10 2023-01-06 江苏谷泰微电子有限公司 Precision differential amplifier with adjustable output common mode
CN115580248B (en) * 2022-11-10 2023-11-28 江苏谷泰微电子有限公司 Precise differential amplifier with adjustable output common mode

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