CN112951724B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112951724B
CN112951724B CN201911259681.2A CN201911259681A CN112951724B CN 112951724 B CN112951724 B CN 112951724B CN 201911259681 A CN201911259681 A CN 201911259681A CN 112951724 B CN112951724 B CN 112951724B
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mask
layer
core layer
material layer
side wall
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CN112951724A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, forming a material layer to be patterned and a mask material layer covering the material layer to be patterned on the substrate, wherein the material layer to be patterned is used for forming a target pattern; forming a core layer on the mask material layer; forming a mask side wall on the side wall of the core layer; etching the partial mask side wall to remove the partial mask side wall of any side wall of the core layer and expose the partial side wall of the core layer; etching a part of the mask side walls, and then taking the residual core layer and the mask side walls as mask patterning mask material layers to form mask layers; and patterning the material layer to be patterned by taking the mask layer as a mask to form a target pattern. According to the invention, part of the mask side wall of any side wall of the core layer is removed in an etching mode, so that the shape quality of the corner of the mask side wall and the core layer is good, the quality of a target pattern is improved, and the performance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
A patterning method commonly used in the semiconductor fabrication arts is photolithography (photolithography) which uses a photoresist material and a controlled exposure to transfer a mask pattern into one or more material layers, such as a metal layer, a dielectric layer, or a semiconductor substrate. However, due to many factors, the patterns formed by the photolithography process have a minimum pitch (pitch), which limits further reduction of the pattern size and also limits the development of integrated circuits to smaller and higher density.
In order to improve the integration of semiconductor devices, various dual patterning processes have been proposed. Among them, self-aligned double patterning (self-aligned double patterning, SADP) is a patterning method that is favored in recent years, and that can increase the density of the patterns formed on the semiconductor substrate and further reduce the pitch between two adjacent patterns, thereby eliminating the limitation of the photolithography process to the field of semiconductor manufacturing.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a material layer to be patterned and a mask material layer covering the material layer to be patterned are formed on the substrate, and the material layer to be patterned is used for forming a target pattern; forming a core layer on the mask material layer; forming a mask side wall on the side wall of the core layer; etching part of the mask side wall to remove part of the mask side wall of any side wall of the core layer and expose part of the side wall of the core layer; after etching a part of the mask side wall, patterning the mask material layer by taking the residual core layer and the mask side wall as masks to form a mask layer; and patterning the material layer to be patterned by taking the mask layer as a mask to form a target pattern.
Optionally, in the step of providing a substrate, the substrate includes a first region and a second region, and a target pattern width formed in the first region is smaller than a target pattern width formed in the second region; in the step of forming a core layer on the mask material layer, the core layer is located on the mask material layer of the first region and the second region; in the step of etching part of the mask side wall, etching part of the mask side wall in the second region; before the patterning of the mask material layer by taking the remaining core layer and the mask side wall as masks, the forming method further comprises the following steps: and removing the core layer of the first region.
Optionally, after the mask side wall is formed, removing the core layer of the first region before etching a part of the mask side wall; or after etching a part of the mask side wall, removing the core layer of the first region.
Optionally, the step of removing the core layer of the first region includes: forming a first shielding layer on the mask material layer in the second region, wherein the first shielding layer covers the core layer and the mask side wall; removing the core layer of the first region by taking the first shielding layer as a mask; and removing the first shielding layer after removing the core layer of the first area.
Optionally, the step of etching a portion of the mask sidewall includes: forming a second shielding layer on the mask material layer, wherein the second shielding layer covers the core layer and the top of the mask side wall, and the second shielding layer exposes the mask side wall to be etched on the side wall of the core layer; taking the second shielding layer as a mask, and removing the exposed mask side wall; and removing the second shielding layer after removing the exposed mask side wall.
Optionally, in the process of etching a part of the mask side walls in the second region, cutting off one or more mask side walls in the first region in the extending direction of the mask side walls.
Optionally, an anisotropic dry etching process is adopted to etch a part of the mask side wall.
Optionally, the step of forming a mask sidewall on the sidewall of the core layer includes: forming a side wall material layer which conformally covers the core layer and the mask material layer; and removing the side wall material layer positioned on the top of the core layer and the mask material layer, and reserving the side wall material layer positioned on the side wall of the core layer as a mask side wall.
Optionally, in the step of forming a core layer on the mask material layer, a core layer width of the first region is smaller than a core layer width of the second region.
Optionally, the material of the mask material layer is silicon nitride or silicon oxide, the material of the core layer is amorphous silicon, amorphous germanium, polysilicon, ODL material, DARC material or BARC material, and the material of the mask side wall is silicon oxide or silicon nitride, wherein the material of the mask material layer and the material of the mask side wall are different.
Optionally, the material of the first shielding layer includes photoresist.
Optionally, the material of the second shielding layer includes photoresist.
Optionally, the material layer to be patterned is a fin material layer, and the target pattern is a fin; or the material layer to be patterned is a grid material layer, and the target pattern is a grid layer; or the material layer to be patterned is an inter-metal dielectric layer, and the target pattern is an interconnection opening formed in the inter-metal dielectric layer.
Accordingly, an embodiment of the present invention provides a semiconductor structure, including: the patterning device comprises a substrate, a material layer to be patterned and a mask material layer covering the material layer to be patterned, wherein the material layer to be patterned is used for forming a target pattern; the core layer is positioned on the mask material layer; mask side walls are positioned on the side walls of the core layer, and part of the side walls of any side of the core layer are exposed by the mask side walls; the core layer and the mask side wall are used as masks for patterning the mask material layer.
Optionally, the substrate includes a first region and a second region, and a target pattern width formed in the first region is smaller than a target pattern width formed in the second region; the core layer is positioned on the mask material layer of the second area; the mask side wall is also positioned on the mask material layer of the first region.
Optionally, the material of the mask material layer is silicon nitride or silicon oxide, the material of the core layer is amorphous silicon, amorphous germanium, polysilicon, ODL material, DARC material or BARC material, and the material of the mask side wall is silicon oxide or silicon nitride, wherein the material of the mask material layer and the material of the mask side wall are different.
Optionally, the material layer to be patterned is a fin material layer, and the target pattern is a fin; or the material layer to be patterned is a grid material layer, and the target pattern is a grid layer; or the material layer to be patterned is an inter-metal dielectric layer, and the target pattern is an interconnection opening formed in the inter-metal dielectric layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the scheme disclosed by the embodiment of the invention, a core layer is formed on a mask material layer, after mask side walls are formed on the side walls of the core layer, etching treatment is carried out on part of the mask side walls so as to remove part of the mask side walls of any side wall of the core layer and expose part of the side walls of the core layer, so that the mask material layer is patterned by taking the rest of the core layer and the mask side walls as masks, a mask layer is formed, and then the mask layer is taken as a mask, and the material layer to be patterned is patterned so as to form a target pattern; the mask side wall on the side wall of the core layer is removed in an etching mode, so that the appearance quality of the corner of the mask side wall and the core layer is good, the quality of a target pattern is improved, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 7 to 15 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
Currently, the performance of semiconductor structures is still to be improved.
Now, in conjunction with a method for forming a semiconductor structure, the performance of the semiconductor structure is to be improved. Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a base is provided, including a substrate (not shown) and a fin 10 protruding from the substrate, the substrate 10 including a first region 10a and a second region 10b, on which a gate oxide layer 20, a gate material layer 30 covering the gate oxide layer 20, and a mask material layer 40 covering the gate material layer 30 are formed.
The mask material layer 40 is used to form a gate layer, and the width of the gate layer formed in the first region 10a is smaller than that of the gate layer formed in the second region 10 b.
With continued reference to fig. 1, a core layer 50 is formed on the masking material layer 40 of the first region 10 a.
Referring to fig. 2, mask spacers 60 are formed on sidewalls of the core layer 50.
Referring to fig. 3, after forming mask sidewall 60, core layer 50 is removed.
Referring to fig. 4, after removing the core layer 50, a photoresist layer 70 is formed on the mask material layer 40 of the second region 10 b.
Referring to fig. 5, mask material layer 40 is etched using mask sidewall 60 (shown in fig. 4) and photoresist layer 70 (shown in fig. 4) as a mask to form mask layer 45; after forming the mask layer 45, removing the mask sidewall 60 and the photoresist layer 70; after removing the mask sidewall 60 and the photoresist layer 70, the gate material layer 30 is etched with the mask layer 45 as a mask, thereby forming the gate layer 35.
As shown in fig. 6, fig. 6 is a top view of a semiconductor structure formed by the method described above, and only the fin 10 and the gate layer 35 are illustrated for ease of illustration.
The gate layer 35 formed in the second region 10b includes a gate layer wide section 32 and a gate layer narrow section 31 in the extending direction thereof according to the process requirement, and the width of the gate layer wide section 32 is greater than the width of the gate layer narrow section 31.
Accordingly, in the step of forming the photoresist layer 70 on the mask material layer 40 of the second region 10b, the morphology of the photoresist layer 70 is matched with the morphology of the gate layer 35 formed in the second region 10 b. However, the photoresist layer 70 is formed by using a photolithography process, and is limited by the photolithography process, rounded corners are easily formed at the corners of the pattern, so that after the gate layer 35 is formed, the gate layer 35 of the second region 10b also has rounded corners (as shown by the dotted circle in fig. 6), which easily results in the performance degradation of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a material layer to be patterned and a mask material layer covering the material layer to be patterned are formed on the substrate, and the material layer to be patterned is used for forming a target pattern; forming a core layer on the mask material layer; forming a mask side wall on the side wall of the core layer; etching part of the mask side wall to remove part of the mask side wall of any side wall of the core layer and expose part of the side wall of the core layer; after etching a part of the mask side wall, patterning the mask material layer by taking the residual core layer and the mask side wall as masks to form a mask layer; and patterning the material layer to be patterned by taking the mask layer as a mask to form a target pattern.
In the scheme disclosed by the embodiment of the invention, the mask side wall on the side wall of the core layer part is removed in an etching mode, so that the appearance quality of the corner of the mask side wall and the core layer is good, the quality of a target pattern is improved, and the performance of the semiconductor structure is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 7 to 15 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 7, a substrate 100 is provided, a material layer 120 to be patterned and a mask material layer 140 covering the material layer 120 to be patterned are formed on the substrate 100, and the material layer 120 to be patterned is used for forming a target pattern.
In this embodiment, taking the forming method for forming a fin field effect transistor as an example, the substrate includes a substrate and a fin portion protruding from the substrate. In other embodiments, the base is a substrate.
Specifically, the substrate 100 includes a first region 100a and a second region 100b, and a target pattern width formed in the first region 100a is smaller than a target pattern width formed in the second region 100 b. In other embodiments, the substrate may also be used to form target patterns of the same width.
In this embodiment, the material layer 120 to be patterned is a gate material layer, and the material layer 120 to be patterned is used to prepare for forming the gate layer. That is, the target pattern is a gate layer.
As an example, the material of the material layer 120 to be patterned is polysilicon.
Accordingly, a gate oxide layer 110 is further formed between the substrate 100 and the material layer 120 to be patterned. As an example, the gate oxide layer 110 is made of silicon oxide.
The masking material layer 140 is used to prepare for the subsequent formation of a patterned masking layer. Wherein the hard mask layer is used as a mask for patterning the material layer 120 to be patterned later.
In this embodiment, the material of the mask material layer 140 is silicon nitride. In other embodiments, the material of the mask material layer may also be silicon oxide. In other embodiments, the material of the mask material layer may also be silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride.
For this purpose, in this embodiment, a buffer layer 130 is further formed between the mask material layer 140 and the material layer 120 to be patterned.
The lattice constant of the material of the buffer layer 130 is between the lattice constant of the material of the mask material layer 140 and the lattice constant of the material layer 120 to be patterned, so as to reduce the stress of the mask material layer 140 and the material layer 120 to be patterned. In this embodiment, the material of the buffer layer 130 is silicon oxide.
It should be noted that, in other embodiments, the material layer to be patterned is a fin material layer, and the formed target pattern is a fin. In this case, the base is a substrate, and the base and the material layer to be patterned are in an integral structure, or the material layer to be patterned is epitaxially grown on the base.
In other embodiments, the forming method may be further applied to back end of line (BEOL) process, where the material layer to be patterned is an inter-metal dielectric layer, and the formed target pattern is an interconnect opening formed in the inter-metal dielectric layer.
With continued reference to fig. 7, a core layer 200 is formed on the masking material layer 140.
The core layer 200 is used to provide a process basis for forming a mask sidewall subsequently.
It should be noted that, the core layer 200 is further removed later, so the etching selection ratio of the material of the core layer 200 to the mask material layer 140 is greater than 50:1, and the material of the core layer 200 is easy to be removed, so that the damage of the subsequent process for removing the core layer 200 to the mask material layer 140 is reduced.
For this purpose, in this embodiment, the material of the core layer 200 may be amorphous silicon. In other embodiments, the material of the core layer may also be amorphous germanium.
In this embodiment, the core layer 200 is formed on the mask material layer 140 of the first region 100a and the second region 100 b.
In this embodiment, the width of the target pattern formed in the first region 100a is smaller than that of the target pattern formed in the second region 100b, and thus, the core layer 200 is formed in the first region 100a, so that the target pattern is formed in the first region 100a by using the SADP process.
Accordingly, the width w1 of the core layer 200 of the first region 100a is smaller than the width w2 of the core layer 200 of the second region 100 b. The extending direction of the core layer 200 is a first direction (not labeled), and the direction parallel to the surface of the substrate 100 and perpendicular to the first direction is a second direction (not labeled), where the width refers to the dimension of the core layer 200 in the second direction.
In this embodiment, the core layer 200 is formed, so that the target patterns with different width dimensions are formed by the same process, so that the process compatibility is high, and the process complexity is reduced.
Referring to fig. 8, mask spacers 210 are formed on sidewalls of the core layer 200.
The mask sidewall 210 is used as a mask for the subsequent patterned mask material layer 140.
Specifically, the step of forming the mask sidewall 210 includes: forming a sidewall material layer conformally covering the core layer 200 and the mask material layer 140; the sidewall material layer on top of the core layer 200 and on the mask material layer 140 is removed, and the sidewall material layer on the sidewall of the core layer 200 remains as the mask sidewall 210.
In this embodiment, in order to improve the thickness uniformity of the sidewall material layer, thereby improving the width uniformity of the mask sidewall 210 in the second direction, an atomic layer deposition process is used to form the sidewall material layer; in addition, the atomic layer deposition process is also beneficial to reducing the control difficulty on the thickness of the side wall material layer. In other embodiments, the sidewall material layer may also be formed by a chemical vapor deposition process.
In this embodiment, an anisotropic maskless dry etching (mask dry etching) process is used to selectively etch the sidewall material layer along the surface normal direction of the substrate 100, so as to retain the sidewall material layer on the sidewall of the core layer 200, so as to form the mask sidewall 210.
It should be noted that, the core layer 200 of the first region 100a is further removed later, so in order to reduce the loss of the mask sidewall 210 caused by the process of removing the core layer 200, the etching selectivity of the core layer 200 to the mask sidewall 210 is greater than 10:1.
In addition, the etching process is further performed on a portion of the mask sidewall 210, so that when the mask sidewall 210 is etched, the etching selectivity ratio of the mask sidewall 210 to the mask material layer 140 is greater than 10:1, thereby reducing the damage of the mask material layer 140 caused by the process of etching the mask sidewall 210.
In this embodiment, the material of the mask sidewall 210 is silicon oxide. In other embodiments, the material of the mask sidewall may be silicon nitride. In other embodiments, the material of the mask sidewall may be silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride. Wherein, the mask material layer 140 and the mask sidewall 210 are made of different materials.
In this embodiment, the width of the mask sidewall 210 along the second direction is determined according to the width of the target pattern subsequently formed in the first region 100 a.
Referring to fig. 9 in combination, after forming the mask sidewall 210 on the sidewall of the core layer 200, the forming method further includes: the core layer 200 of the first region 100a is removed.
In this embodiment, in order to increase the removal rate of the core layer 200, a dry etching process is used to remove the core layer 200 of the first region 100 a.
Specifically, the step of removing the core layer 200 of the first region 100a includes: forming a first shielding layer 300 on the mask material layer 140 of the second region 100b, wherein the first shielding layer 300 covers the core layer 200 and the mask sidewall 219; the core layer 200 of the first region 100a is removed using the first blocking layer 300 as a mask.
In this embodiment, the material of the first shielding layer 300 is photoresist. By selecting the photoresist, the patterning can be directly performed by using the photolithography process, so that the first shielding layer 300 is formed at a preset position, and the process is simple. In other embodiments, the first shielding layer may also be a laminated structure, for example: a bottom antireflective coating (BARC) is included and a photoresist layer is covered over the bottom antireflective coating.
In this embodiment, when the core layer 200 of the first region 100a is removed, the core layer 200 of the second region 100b is retained, so that the core layer 200 of the second region 100b can be used as a mask for patterning the mask material layer 140 in a subsequent process, thereby forming a target pattern with a larger width in the second region 100 b.
Referring to fig. 10 and 11 in combination, fig. 10 is a top view, fig. 11 is a cross-sectional view taken along line A1A2 of fig. 10, and after removing the core layer 200 of the first region 100a, the first shielding layer 300 is removed.
The first shielding layer 300 is removed, so as to prepare for the subsequent etching treatment of the mask sidewall 210 of the second region 100 b.
In this embodiment, the material of the first shielding layer 300 is photoresist, and therefore, an ashing process is used to remove the first shielding layer 300.
Referring to fig. 12 and 13 in combination, fig. 12 is a top view, and fig. 13 is a cross-sectional view taken along line A1A2 in fig. 12, and a portion of the mask sidewall 210 is etched to remove a portion of the mask sidewall 210 on any sidewall of the core layer 200, exposing a portion of the sidewall of the core layer 200.
Wherein, for ease of illustration, fig. 12 illustrates only the core layer 200 and the mask sidewall 210.
In this embodiment, in the step of performing the etching treatment on the partial mask sidewall 210, the etching treatment is performed on the partial mask sidewall 210 in the second region 100 b.
By performing the etching treatment on the portion of the mask sidewall 210 in the second region 100b, the shape of the target pattern formed in the second region 100b can meet the design requirement.
Specifically, the step of etching the portion of the mask sidewall 210 includes: forming a second shielding layer (not shown) on the mask material layer 140, wherein the second shielding layer covers the core layer 200 and the top of the mask sidewall 210, and the second shielding layer exposes the mask sidewall 210 to be etched on the sidewall of the core layer 200; the exposed mask sidewall 210 is removed using the second blocking layer as a mask.
In this embodiment, the material of the second shielding layer is photoresist. The photoresist is selected, and the patterning can be directly performed by utilizing the photoetching technology, so that the second shielding layer is formed at a preset position, and the technology is simple. In other embodiments, the second shielding layer may also be a laminated structure, for example: a photoresist layer including a bottom anti-reflective coating layer covering the bottom anti-reflective coating layer.
In this embodiment, an anisotropic dry etching process is used to etch the mask sidewall 210 exposed by the second shielding layer. The anisotropic dry etching process has anisotropic etching characteristics, so that a relatively straight etching section can be obtained, and the shape quality of a target pattern formed later at a corner is improved.
In this embodiment, during the etching process of the portion of the mask sidewall 210 in the second region 100b, one or more mask sidewalls 210 in the first region 100a are further cut off in the extending direction (i.e., the first direction) of the mask sidewall 210.
The layout of the target pattern in the first area 100a meets the design requirement by performing the cutting process on one or more mask spacers 210 in the first area 100 a.
Correspondingly, in the step of forming the second shielding layer, the second shielding layer also exposes the mask sidewall 210 to be etched in the first region 100 a.
In this embodiment, in the same step, the etching treatment is performed on the mask sidewall 210 in the second region 100b and the first region 100a, so that the same Zhang Guangzhao can be used, and the increase of the process cost is not caused.
In other embodiments, the mask sidewall of the first region may not be etched according to the process requirement.
In this embodiment, after removing the exposed mask sidewall 210, the method further includes: and removing the second shielding layer.
Specifically, the material of the second shielding layer is photoresist, and therefore, the first shielding layer 300 is removed by an ashing process.
It should be noted that, in this embodiment, after the core layer 200 of the first region 100a is removed, etching is performed on a portion of the mask sidewall 210. In other embodiments, after etching the mask sidewall 210, the core layer of the first region may be removed, so long as the core layer of the first region is removed before patterning the mask material layer.
Referring to fig. 14 and 15 in combination, fig. 14 is a top view, fig. 15 is a cross-sectional view taken along line A1A2 in fig. 14, and after etching a portion of the mask sidewall 210, the mask material layer 140 is patterned by using the remaining core layer 200 and the mask sidewall 210 as masks, so as to form a mask layer 145; the material layer 120 to be patterned is patterned using the mask layer 145 as a mask to form a target pattern 125.
Wherein, for ease of illustration, fig. 14 illustrates only the target graphic 125.
In this embodiment, the remaining core layer 200 and the mask sidewall 210 are used as the mask patterning mask material layer 140, and the patterns corresponding to the core layer 200 and the mask sidewall 210 are transferred to the mask material layer 140 to form the mask layer 145, so that the patterns are further transferred to the material layer 120 to be patterned through the mask layer 145 to form the target pattern 125.
In this embodiment, after forming the mask layer 145, the core layer 200 and the mask sidewall 210 are removed.
Specifically, in order to be able to remove the core layer 200 and the mask sidewall 210 cleanly, a wet etching process is used to remove the core layer 200 and the mask sidewall 210.
In this embodiment, the material layer 120 to be patterned is patterned by using an anisotropic dry etching process, so as to improve the shape quality of the target pattern 125.
In this embodiment, the material layer 120 to be patterned is a gate material layer, and thus the target pattern 125 is a gate layer.
In this embodiment, in the second region 100b, the target pattern 125 includes a target pattern wide section 125a and a target pattern narrow section 125b in the extending direction thereof, and the width of the target pattern wide section 125a is larger than the width of the target pattern narrow section 125 b.
The target pattern wide section 125a is formed by the core layer 200 (as shown in fig. 12) and the mask side walls 210 (as shown in fig. 12) located at two sides of the core layer 200, the target pattern narrow section 125b is formed by the core layer 200 and the mask side walls 210 located at one side of the core layer 200, and by the foregoing etching treatment of a portion of the mask side walls 210, the appearance quality at the corners of the target pattern wide section 125a and the target pattern narrow section 125b is better, and the probability of forming a round corner at the corner is lower, thereby improving the performance of the semiconductor structure.
It should be noted that, a buffer layer 130 is further formed between the mask material layer 140 and the material layer 120 to be patterned, and therefore, before etching the material layer 120 to be patterned, the buffer layer 130 is further etched.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 12 and 13 in combination, a schematic structural diagram of one embodiment of a semiconductor structure of the present invention is shown. Fig. 12 is a top view, fig. 13 is a cross-sectional view taken along line A1A2 in fig. 12, and fig. 12 illustrates only the core layer 200 and the mask sidewall 210 for convenience of illustration.
The semiconductor structure includes: a substrate 100, on which a material layer 120 to be patterned and a mask material layer 140 covering the material layer 120 to be patterned are formed, wherein the material layer 120 to be patterned is used for forming a target pattern; a core layer 200 located on the mask material layer 140; mask side walls 210 located on the side walls of the core layer 200, and part of the side walls of the core layer 200 are exposed by the mask side walls 210; the core layer 200 and the mask sidewall 210 are used as a mask for patterning the mask material layer 140.
The substrate is used to provide a process basis for forming a target pattern. In this embodiment, taking the semiconductor structure as a fin field effect transistor as an example, the base includes a substrate and a fin portion protruding from the substrate. In other embodiments, the base is a substrate.
Specifically, the substrate 100 includes a first region 100a and a second region 100b, and a target pattern width formed in the first region 100a is smaller than a target pattern width formed in the second region 100 b. In other embodiments, the substrate may also be used to form target patterns of the same width.
In this embodiment, the material layer 120 to be patterned is a gate material layer, and the material layer 120 to be patterned is used to prepare for forming the gate layer. That is, the target pattern is a gate layer.
As an example, the material of the material layer 120 to be patterned is polysilicon.
Accordingly, a gate oxide layer 110 is further formed between the substrate 100 and the material layer 120 to be patterned. As an example, the gate oxide layer 110 is made of silicon oxide.
The masking material layer 140 is used to prepare for the subsequent formation of a patterned masking layer. Wherein the hard mask layer is used as a mask for patterning the material layer 120 to be patterned later.
In this embodiment, the material of the mask material layer 140 is silicon nitride. In other embodiments, the material of the mask material layer may also be silicon oxide. In other embodiments, the material of the mask material layer may also be silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride.
For this purpose, in this embodiment, a buffer layer 130 is further formed between the mask material layer 140 and the material layer 120 to be patterned.
The lattice constant of the buffer layer 130 is located between the mask material layer 140 and the material layer 120 to be patterned, thereby reducing stress of the mask material layer 140 and the material layer 120 to be patterned. In this embodiment, the material of the buffer layer 130 is silicon oxide.
It should be noted that, in other embodiments, the material layer to be patterned is a fin material layer, and the formed target pattern is a fin. In this case, the base is a substrate, and the base and the material layer to be patterned are in an integral structure, or the material layer to be patterned is epitaxially grown on the base.
In other embodiments, the forming method may be further applied to back end of line (BEOL) process, where the material layer to be patterned is an inter-metal dielectric layer, and the formed target pattern is an interconnect opening formed in the inter-metal dielectric layer.
The core layer 200 is used to provide a process basis for forming the mask sidewall 210. In the second region 100b, the core layer 200 and the mask sidewall 210 on the sidewall thereof are used together as a mask for patterning the mask material layer 140.
It should be noted that, the core layer 200 is further removed later, so the etching selection ratio of the material of the core layer 200 to the mask material layer 140 is greater than 50:1, and the material of the core layer 200 is easy to be removed, so that the damage of the subsequent process for removing the core layer 200 to the mask material layer 140 is reduced.
For this purpose, in this embodiment, the material of the core layer 200 may be amorphous silicon. In other embodiments, the material of the core layer may also be amorphous germanium.
In this embodiment, the core layer 200 is only located on the mask material layer 140 of the second region 100 b.
In this embodiment, the mask sidewall 210 is located on a sidewall of the core layer 200, and the mask sidewall 210 exposes a portion of the sidewall on one side of the core layer 200.
After the pattern formed by the core layer 200 and the mask sidewall 210 is transferred to the material layer 120 to be patterned in the second region 100b, the formed target pattern can include a target pattern wide section and a target pattern narrow section in the extending direction, and the width of the target pattern wide section is greater than the width of the target pattern narrow section, thereby meeting the design requirement.
In this embodiment, the mask sidewall 210 is further located on the mask material layer 140 of the first region 100a, where the first region 100a is used as a mask for patterning the mask material layer 140 of the first region 100 a.
The mask sidewall 210 of the first region 100a is formed by using an SADP process, the core layer 200 is further formed on the mask material layer 140 of the first region 100a during the process of forming the semiconductor structure, the mask sidewall 210 is formed on a sidewall of the core layer 200, and after the mask sidewall 210 is formed, the core layer 200 of the first region 100a is removed.
Therefore, in order to reduce the loss of the mask sidewall 210 caused by the process of removing the core layer 200, the etching selectivity of the core layer 200 to the mask sidewall 210 is greater than 10:1. In addition, when etching is performed on part of the mask sidewall 210, the etching selectivity ratio of the mask sidewall 210 to the mask material layer 140 is greater than 10:1, so that damage to the mask material layer 140 caused by the process of etching the mask sidewall 210 is reduced.
In this embodiment, the material of the mask sidewall 210 is silicon oxide. In other embodiments, the material of the mask sidewall may be silicon nitride. In other embodiments, the material of the mask sidewall may be silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride. Wherein, the mask material layer 140 and the mask sidewall 210 are made of different materials.
In this embodiment, the width of the mask sidewall 210 along the second direction is determined according to the width of the target pattern formed in the first region 100 a.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing first embodiment, and no further description is given here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (17)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a material layer to be patterned and a mask material layer covering the material layer to be patterned are formed on the substrate, and the material layer to be patterned is used for forming a target pattern;
forming a core layer on the mask material layer;
forming a mask side wall on the side wall of the core layer;
Etching a part of the mask side wall to remove the mask side wall with part of the length of any side wall of the core layer in the extending direction of the core layer, and exposing the side wall with part of the length of the core layer in the extending direction;
after etching a part of the mask side wall, patterning the mask material layer by taking the residual core layer and the mask side wall as masks to form a mask layer;
and patterning the material layer to be patterned by taking the mask layer as a mask to form a target pattern, wherein the target pattern comprises a target pattern wide section and a target pattern narrow section which are connected in the extending direction of the target pattern wide section, the width of the target pattern wide section is larger than that of the target pattern narrow section, the target pattern wide section and the target pattern narrow section are provided with corners at the connecting positions, the target pattern wide section is formed by the core layer and mask side walls positioned at two sides of the core layer, and the target pattern narrow section is formed by the core layer and the mask side walls positioned at one side of the core layer.
2. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the substrate comprises a first region and a second region, and a target pattern width formed in the first region is smaller than a target pattern width formed in the second region;
in the step of forming a core layer on the mask material layer, the core layer is located on the mask material layer of the first region and the second region;
in the step of etching part of the mask side wall, etching part of the mask side wall in the second region;
Before the patterning of the mask material layer by taking the remaining core layer and the mask side wall as masks, the forming method further comprises the following steps: and removing the core layer of the first region.
3. The method of forming a semiconductor structure of claim 2, wherein after forming the mask sidewall, removing the core layer of the first region before etching a portion of the mask sidewall;
or after etching a part of the mask side wall, removing the core layer of the first region.
4. The method of forming a semiconductor structure of claim 2, wherein removing the core layer of the first region comprises: forming a first shielding layer on the mask material layer in the second region, wherein the first shielding layer covers the core layer and the mask side wall;
removing the core layer of the first region by taking the first shielding layer as a mask;
And removing the first shielding layer after removing the core layer of the first area.
5. A method of forming a semiconductor structure as claimed in any one of claims 1 to 3, wherein the step of etching a portion of the mask sidewall comprises: forming a second shielding layer on the mask material layer, wherein the second shielding layer covers the core layer and the top of the mask side wall, and the second shielding layer exposes the mask side wall to be etched on the side wall of the core layer;
taking the second shielding layer as a mask, and removing the exposed mask side wall;
and removing the second shielding layer after removing the exposed mask side wall.
6. The method of claim 2, further comprising cutting one or more of the mask spacers in the first region in the extending direction of the mask spacers during etching a portion of the mask spacers in the second region.
7. A method of forming a semiconductor structure as claimed in any one of claims 1 to 3 wherein a portion of the mask sidewall is etched using an anisotropic dry etch process.
8. The method of forming a semiconductor structure of claim 1, wherein forming mask spacers on sidewalls of the core layer comprises: forming a side wall material layer which conformally covers the core layer and the mask material layer;
And removing the side wall material layer positioned on the top of the core layer and the mask material layer, and reserving the side wall material layer positioned on the side wall of the core layer as a mask side wall.
9. The method of forming a semiconductor structure of claim 2, wherein in the step of forming a core layer on the mask material layer, a core layer width of the first region is smaller than a core layer width of the second region.
10. The method of claim 1, wherein the material of the mask material layer is silicon nitride or silicon oxide, the material of the core layer is amorphous silicon, amorphous germanium, polysilicon, ODL material, DARC material or BARC material, and the material of the mask sidewall is silicon oxide or silicon nitride, wherein the material of the mask material layer and the material of the mask sidewall are different.
11. The method of forming a semiconductor structure of claim 4, wherein the material of the first masking layer comprises a photoresist.
12. The method of forming a semiconductor structure of claim 5, wherein the material of the second masking layer comprises a photoresist.
13. The method of claim 1, wherein the material layer to be patterned is a fin material layer and the target pattern is a fin;
or the material layer to be patterned is a grid material layer, and the target pattern is a grid layer;
Or the material layer to be patterned is an inter-metal dielectric layer, and the target pattern is an interconnection opening formed in the inter-metal dielectric layer.
14. A semiconductor structure, comprising:
the patterning device comprises a substrate, a material layer to be patterned and a mask material layer covering the material layer to be patterned, wherein the material layer to be patterned is used for forming a target pattern;
The core layer is positioned on the mask material layer;
The mask side wall is positioned on the side wall of the core layer, and in the extending direction of the core layer, the mask side wall exposes the side wall of a part of the length of any side of the core layer;
The core layer and the mask side wall are used for being used for patterning the mask of the mask material layer, the mask is used for enabling the target pattern to comprise a target pattern wide section and a target pattern narrow section which are connected in the extending direction of the mask, the width of the target pattern wide section is larger than that of the target pattern narrow section, the connecting position of the target pattern wide section and the target pattern narrow section is provided with a corner, the target pattern wide section is formed by the core layer and the mask side walls positioned on two sides of the core layer, and the target pattern narrow section is formed by the core layer and the mask side walls positioned on one side of the core layer.
15. The semiconductor structure of claim 14, wherein the substrate comprises a first region and a second region, a target pattern width formed in the first region being smaller than a target pattern width formed in the second region;
the core layer is positioned on the mask material layer of the second area;
the mask side wall is also positioned on the mask material layer of the first region.
16. The semiconductor structure of claim 14, wherein the material of the mask material layer is silicon nitride or silicon oxide, the material of the core layer is amorphous silicon, amorphous germanium, polysilicon, ODL material, DARC material, or BARC material, and the material of the mask sidewall is silicon oxide or silicon nitride, wherein the material of the mask material layer and the mask sidewall are different.
17. The semiconductor structure of claim 14, wherein the material layer to be patterned is a fin material layer and the target pattern is a fin;
or the material layer to be patterned is a grid material layer, and the target pattern is a grid layer;
Or the material layer to be patterned is an inter-metal dielectric layer, and the target pattern is an interconnection opening formed in the inter-metal dielectric layer.
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