CN112951694A - Plasma processing apparatus and method for processing semiconductor wafer - Google Patents
Plasma processing apparatus and method for processing semiconductor wafer Download PDFInfo
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- CN112951694A CN112951694A CN201911174957.7A CN201911174957A CN112951694A CN 112951694 A CN112951694 A CN 112951694A CN 201911174957 A CN201911174957 A CN 201911174957A CN 112951694 A CN112951694 A CN 112951694A
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- 238000012545 processing Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000001816 cooling Methods 0.000 claims abstract description 57
- 238000010438 heat treatment Methods 0.000 claims abstract description 26
- 239000012495 reaction gas Substances 0.000 claims abstract description 10
- 239000002826 coolant Substances 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 25
- 230000008569 process Effects 0.000 claims description 10
- 238000012544 monitoring process Methods 0.000 claims description 9
- 230000003247 decreasing effect Effects 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 3
- 230000001276 controlling effect Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 229920000642 polymer Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32458—Vessel
- H01J37/32522—Temperature
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The present invention relates to a plasma processing apparatus and a method for processing a semiconductor wafer. The plasma processing device comprises a reaction cavity, wherein the reaction cavity comprises an upper electrode assembly, a lower electrode assembly, a cooling channel and a heating device. The upper electrode assembly is arranged above the reaction cavity and is used for conveying reaction gas into the reaction cavity. The lower electrode assembly is arranged below the reaction chamber, is opposite to the upper electrode assembly and is used for bearing the wafer to be processed. The cooling channel is disposed inside the upper electrode assembly for cooling the upper electrode assembly. The heating device is disposed inside the upper electrode assembly, and includes: the plurality of discrete heaters are used for heating different areas of the upper electrode assembly; and a controller connected with the plurality of discrete heaters and respectively controlling the power of each discrete heater.
Description
Technical Field
The present invention relates to semiconductor devices, and more particularly to a plasma processing apparatus and a method for processing a semiconductor wafer.
Background
During plasma etching, the etch rate of some processes is strongly controlled by the temperature distribution of the upper and lower electrodes of the etch chamber. This effect typically has the following logical process:
the deposition distribution of the reaction Polymer (Polymer) in the cavity is adjusted by controlling the temperature of the upper electrode and the lower electrode, and the etching rate of the wafer can be influenced by the intensity of the Polymer deposition at the wafer end. As follows:
1) the higher the upper electrode temperature (or the lower electrode wafer end temperature), the heavier the Polymer at the lower electrode wafer end; within a certain specific range, the faster the wafer etching rate is;
2) the lower the upper electrode temperature (or the higher the lower electrode wafer end temperature), the lighter the Polymer at the lower electrode wafer end; within a certain range, the slower the wafer etch rate.
Therefore, the wafer etching rate can be regulated and controlled by regulating the temperature of the upper electrode and the lower electrode; in addition, it is conceivable that the adjustment of the uniformity and symmetry of the wafer etching rate can be realized by multi-zone control of the temperature distribution of the upper and lower electrodes. Common multi-zone temperature control is primarily directed to the bottom electrode (electrostatic chuck), such as by a dual-coolant zone electrostatic chuck, a dual-He zone electrostatic chuck, a multi-zone dynamic electrostatic chuck, and the like. The main reason for controlling the temperature of the lower electrode through common selection is that the wafer is in direct contact with the electrostatic chuck, the etching effect is more sensitive to the temperature of the electrostatic chuck, and the regulation and control are more effective.
However, the lower electrode regulation has the following disadvantages:
1) if the Multi-zone design adopts an electric heating type, the Multi-zone design cannot be applied to a high-temperature high-power plasma etching process, because the design of the RF filter is difficult to meet the high-power requirement;
2) multi-zone design if the coolant or He cooling mode is used, the design and usage costs are intolerable.
Therefore, in the VNAND process at the present stage, the lower electrode of the etching cavity can only adopt a Dual-zone mode generally, and the asymmetry of the etching rate cannot be regulated and controlled through the multi-zone temperature control of the lower electrode. Therefore, the multi-zone temperature control of the upper electrode is a feasible regulation method. In addition, if the upper electrode does not use multi-zone temperature control, the temperature distribution of the upper electrode often has serious asymmetry, as shown in fig. 1, and the design thereof has the following irreconcilable defects:
1) the Heater 10(Heater channel) cannot be completely closed-loop, resulting in a cooler temperature at the end points of the two leads of the heating electrode;
2) the temperature control cooling channel 20(Coolant channel) has a water temperature gradient change, the water Inlet end (Inlet) is cold, and the water Outlet end (Outlet) is hot, so that the water cooling effect is not uniform.
The above-mentioned defects may cause the temperature distribution to exist in a Cold area and a Hot area (Hot area), and the temperature gradient in the Cold and Hot areas reaches 7% of the average temperature in actual measurement, and when the installation angle of the heater is rotated by 180 °, the Cold and Hot areas are exchanged by 180 °. Such temperature gradients are unacceptable for electrode temperature sensitive etch processes and can cause severe asymmetry in etch rate.
Disclosure of Invention
The present invention is directed to a plasma processing apparatus and a method for processing a semiconductor wafer thereof, which are used to solve the problems encountered in the prior art.
In order to achieve the above object, a first aspect of the present invention provides a plasma processing apparatus, which includes a reaction chamber, wherein the reaction chamber includes an upper electrode assembly, a lower electrode assembly, a cooling channel, and a heating device. The upper electrode assembly is arranged above the reaction cavity and is used for conveying reaction gas into the reaction cavity. The lower electrode assembly is arranged below the reaction chamber, is opposite to the upper electrode assembly and is used for bearing the wafer to be processed. The cooling channel is disposed inside the upper electrode assembly for cooling the upper electrode assembly. The heating device is disposed inside the upper electrode assembly, and includes: the plurality of discrete heaters are used for heating different areas of the upper electrode assembly; and a controller connected with the plurality of discrete heaters and respectively controlling the power of each discrete heater.
Optionally, several discrete heaters are arranged in a ring shape, and are arranged around the inner side or the outer side of the cooling channel.
Optionally, the controller adjusts the power of each discrete heater according to the cooling channel portion corresponding to each discrete heater.
Alternatively, the power of the discrete heaters corresponding to the coolant inlets of the cooling channels to the discrete heaters corresponding to the coolant outlets of the cooling channels is sequentially decreased.
Optionally, the cooling channel comprises at least one coolant inlet and one coolant outlet.
Optionally, the output powers of the plurality of discrete heaters are the same, and the controller controls the power output percentage of each discrete heater respectively.
Optionally, the controller adjusts the power of the corresponding discrete heater according to an etching asymmetry point of the wafer under etching.
Optionally, thermal isolation means are provided between the different discrete heaters.
In order to achieve the above object, a second aspect of the present invention provides a method for processing a semiconductor wafer, the method being performed in a plasma processing apparatus, the method comprising: the wafer is transferred into the reaction chamber and placed above the lower electrode assembly. A reaction gas is supplied into the reaction chamber using the upper electrode assembly. And applying radio frequency power to the reaction cavity, exciting the reaction gas into plasma, and carrying out process treatment on the wafer by using the plasma. And monitoring the wafer processing result and transmitting the monitoring result to the controller. The temperature of the upper electrode assembly is controlled by the cooling channel and the heating device, and the controller adjusts the power of the heating device in different areas according to the monitoring result of wafer processing.
Alternatively, the controller controls the heating power of the discrete heaters corresponding to the coolant inlets of the cooling channels to be sequentially decreased to the discrete heaters corresponding to the coolant outlets of the cooling channels.
Optionally, the cooling channel comprises several coolant inlets and several coolant outlets, and the controller may control the coolant flow or temperature into different coolant inlets to achieve temperature adjustment of the cooling channel in different sections.
Optionally, the output powers of the plurality of discrete heaters are the same, and the controller controls the power output percentage of each discrete heater respectively.
Optionally, the controller adjusts the power of the corresponding discrete heater according to an etching asymmetry point of the wafer under etching.
Compared with the prior art, the plasma processing device and the processing method of the semiconductor wafer thereof respectively control the power of each discrete heater through the controller, thereby realizing the accurate selection and adjustment of the etching rate of certain etching processes.
Drawings
FIG. 1 is a schematic diagram of a heater and temperature controlled cooling channel of a conventional plasma processing apparatus;
FIG. 2 is a schematic view of a plasma processing apparatus of the present invention;
FIG. 3 is a schematic view of a heating device and a cooling channel of the plasma processing apparatus of the present invention;
FIG. 4 is a block diagram of a heating device of the plasma processing apparatus of the present invention;
FIG. 5 is a flowchart of a method for processing a semiconductor wafer in the plasma processing apparatus according to the present invention.
Detailed Description
In order to facilitate understanding of the features, contents, and advantages of the present invention and the effects achieved thereby, the present invention will be described in detail with reference to the accompanying drawings in the form of embodiments, wherein the drawings are provided for illustrative purposes and for supporting the specification, and are not necessarily to be construed as being true in scale and precise arrangement after the practice of the present invention, and therefore, the scope of the present invention in practical terms should not be read as limited by the scale and arrangement of the accompanying drawings.
Please refer to fig. 2 to 4; FIG. 2 is a schematic view of a plasma processing apparatus of the present invention; FIG. 3 is a schematic view of a heating device and a cooling channel of the plasma processing apparatus of the present invention; fig. 4 is a block diagram of a heating apparatus of the plasma processing apparatus of the present invention. As shown, the present invention provides a plasma processing apparatus 300, which comprises a reaction chamber 310, wherein the reaction chamber 310 comprises an upper electrode assembly 320, a lower electrode assembly 330, a cooling channel 200 and a heating apparatus 100.
The upper electrode assembly 320 is disposed above the inside of the reaction chamber 310 while serving to supply a reaction gas into the reaction chamber 310. The lower electrode assembly 330 is disposed below and opposite the upper electrode assembly 320 within the reaction chamber 310 for carrying a wafer to be processed.
The cooling channel 200 is disposed inside the upper electrode assembly 320 for cooling the upper electrode assembly 320.
The heating device 100 is disposed inside the upper electrode assembly 320, and includes: a plurality of discrete heaters 110 for heating different regions of the upper electrode assembly 320; and a controller 120 connected to the plurality of discrete heaters 110 and controlling power of each discrete heater 110, respectively.
The discrete heaters 110 are disposed in a ring shape, and are disposed around the cooling channel 200, but not connected to each other. The controller 120 is connected to the plurality of discrete heaters 110 and controls the power of each discrete heater 110. Wherein thermal isolation means may be provided between different discrete heaters 110.
Further, the controller 120 adjusts the power of each discrete heater 110 according to the portion of the cooling channel 200 corresponding to each discrete heater 110, that is, the power of the discrete heater 110 corresponding to different portion of the cooling channel 200 may be different from that of each discrete heater 110 corresponding to other portion. Examples are as follows:
the power of each discrete heater 110 may be decreased in an order from the discrete heater 110 corresponding to the coolant inlet 210 of the cooling passage 200 to the discrete heater 110 corresponding to the coolant outlet 220 of the cooling passage 200. Because the temperature of the cooling channel 200 is gradually increased from the coolant inlet 210 to the coolant outlet 220, correspondingly, the power of each discrete heater 110 is correspondingly adjusted corresponding to different portions of the cooling channel 200, so that if the temperature of the cooling channel 200 is gradually increased from the coolant inlet 210 to the coolant outlet 220, the power of each discrete heater 110 is correspondingly and sequentially decreased along the direction from the coolant inlet 210 to the coolant outlet 220, so as to achieve the purpose of accurately selecting and adjusting the etching rate.
Wherein the cooling channel 200 comprises at least one coolant inlet 210 and one coolant outlet 220; alternatively, the cooling channels 200 may be designed in segments to individually have the coolant inlet 210 and the coolant outlet 220.
On the other hand, when the output powers of the discrete heaters 110 are the same, the controller 120 can still control the power of each discrete heater 110 by controlling the power output percentage of each discrete heater 110.
In practical application of the heating apparatus 100 of the present invention, the controller 120 can adjust the power of the discrete heater 110 at the corresponding position according to the etching asymmetry point of the wafer during etching, so as to achieve the purpose of accurately selecting and adjusting the etching rate.
It should be noted that each discrete heater 110 has a corresponding temperature control area, and in order to avoid the cross temperature control, the temperature control area corresponding to each discrete heater 110 is subjected to heat insulation treatment.
Referring to fig. 5, fig. 5 is a flow chart illustrating a method for processing a semiconductor wafer in a plasma processing apparatus according to the present invention. As shown, the present invention provides a method for processing a semiconductor wafer, the method being performed in the plasma processing apparatus, the method comprising:
in step S51: the wafer is transferred into the reaction chamber and placed above the lower electrode assembly. In step S52: a reaction gas is supplied into the reaction chamber using the upper electrode assembly.
In step S53: and applying radio frequency power to the reaction cavity, exciting the reaction gas into plasma, and carrying out process treatment on the wafer by using the plasma.
In step S54: and monitoring the wafer processing result and transmitting the monitoring result to the controller.
In step S55: the temperature of the upper electrode assembly is controlled by the cooling channel and the heating device, and the controller adjusts the power of the heating device in different areas according to the monitoring result of wafer processing.
Further, the controller 120 adjusts the power of each discrete heater 110 according to the portion of the cooling channel 200 corresponding to each discrete heater 110, that is, the power of the discrete heater 110 corresponding to different portion of the cooling channel 200 may be different from that of each discrete heater 110 corresponding to other portion. Examples are as follows:
the power of each discrete heater 110 may be decreased in an order from the discrete heater 110 corresponding to the coolant inlet 210 of the cooling passage 200 to the discrete heater 110 corresponding to the coolant outlet 220 of the cooling passage 200. Because the temperature of the cooling channel 200 is gradually increased from the coolant inlet 210 to the coolant outlet 220, correspondingly, the power of each discrete heater 110 is correspondingly adjusted corresponding to different portions of the cooling channel 200, so that if the temperature of the cooling channel 200 is gradually increased from the coolant inlet 210 to the coolant outlet 220, the power of each discrete heater 110 is correspondingly and sequentially decreased along the direction from the coolant inlet 210 to the coolant outlet 220, so as to achieve the purpose of accurately selecting and adjusting the etching rate.
Whereas, the cooling channel 200 includes several coolant inlets 210 and several coolant outlets, the controller 120 may control the coolant flow or temperature entering different coolant inlets 210 to achieve temperature adjustment of the cooling channel 200 for different sections.
On the other hand, when the output powers of the discrete heaters 110 are the same, the controller 120 can still control the power of each discrete heater 110 by controlling the power output percentage of each discrete heater 110.
In practical application of the heating apparatus 100 of the present invention, the controller 120 can adjust the power of the discrete heater 110 at the corresponding position according to the etching asymmetry point of the wafer during etching, so as to achieve the purpose of accurately selecting and adjusting the etching rate.
It should be noted that each discrete heater 110 has a corresponding temperature control area, so as to avoid the cross temperature control, the temperature control area corresponding to each discrete heater 110 can be subjected to heat insulation treatment.
Compared with the prior art, the plasma processing device and the processing method of the semiconductor wafer thereof respectively control the power of each discrete heater through the controller, thereby realizing the accurate selection and adjustment of the etching rate of certain etching processes.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (13)
1. A plasma processing apparatus comprising a reaction chamber, wherein the reaction chamber comprises:
the upper electrode assembly is arranged above the reaction cavity and is used for conveying reaction gas into the reaction cavity;
the lower electrode assembly is arranged below the reaction cavity, is opposite to the upper electrode assembly and is used for bearing a wafer to be processed;
the cooling channel is arranged in the upper electrode assembly and used for cooling the upper electrode assembly; and
a heating device disposed inside the upper electrode assembly, comprising:
a plurality of discrete heaters for heating different regions of the upper electrode assembly; and
and the controller is connected with the plurality of discrete heaters and respectively controls the power of each discrete heater.
2. The plasma processing apparatus of claim 1, wherein the plurality of discrete heaters are arranged in a ring shape, and are arranged around an inner side or an outer side of the cooling channel.
3. The plasma processing apparatus as claimed in claim 2, wherein the controller adjusts power of each of the discrete heaters according to the cooling passage portion corresponding to each of the discrete heaters.
4. The plasma processing apparatus as claimed in claim 3, wherein the power of the discrete heater corresponding to the coolant inlet of the cooling passage to the discrete heater corresponding to the coolant outlet of the cooling passage is sequentially decreased.
5. The plasma processing apparatus of claim 1 wherein the cooling channel comprises at least one coolant inlet and one coolant outlet.
6. The plasma processing apparatus as claimed in claim 1, wherein the output power of the plurality of discrete heaters is the same, and the controller controls the power output percentage of each of the discrete heaters, respectively.
7. The plasma processing apparatus of claim 1, wherein the controller adjusts the power of the corresponding discrete heater according to an etch asymmetry point of the wafer being etched.
8. The plasma processing apparatus of claim 1 wherein thermal isolation means are provided between different of said discrete heaters.
9. A method of processing a semiconductor wafer, the method being performed in the plasma processing apparatus according to any one of claims 1 to 8, comprising the steps of:
transferring the wafer into the reaction chamber and placing the wafer above the lower electrode assembly;
supplying a reaction gas into the reaction chamber using the upper electrode assembly;
applying radio frequency power to the reaction cavity, exciting the reaction gas into plasma, and carrying out process treatment on the wafer by using the plasma;
monitoring the wafer processing result and transmitting the monitoring result to the controller;
and controlling the temperature of the upper electrode assembly by using the cooling channel and the heating device, and adjusting the power of the heating device in different areas by using the controller according to the monitoring result of the wafer processing.
10. The method of claim 9, wherein the controller controls the heating power of the discrete heaters corresponding to the coolant inlets of the cooling channels to the discrete heaters corresponding to the coolant outlets of the cooling channels to be sequentially decreased.
11. The method of claim 9, wherein the cooling channel comprises a plurality of coolant inlets and a plurality of coolant outlets, and wherein the controller controls coolant flow or temperature to different ones of the coolant inlets to achieve temperature adjustment of the cooling channel in different sections.
12. The method of claim 9, wherein the discrete heaters have the same output power, and wherein the controller controls the percentage of power output of each discrete heater.
13. The method of claim 9, wherein the controller adjusts the power of the corresponding discrete heater according to an etching asymmetry point of the wafer during etching.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911174957.7A CN112951694B (en) | 2019-11-26 | 2019-11-26 | Plasma processing apparatus and method for processing semiconductor wafer |
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| CN201911174957.7A CN112951694B (en) | 2019-11-26 | 2019-11-26 | Plasma processing apparatus and method for processing semiconductor wafer |
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| CN112951694B (en) | 2024-05-10 |
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