CN112951694B - Plasma processing apparatus and method for processing semiconductor wafer - Google Patents
Plasma processing apparatus and method for processing semiconductor wafer Download PDFInfo
- Publication number
- CN112951694B CN112951694B CN201911174957.7A CN201911174957A CN112951694B CN 112951694 B CN112951694 B CN 112951694B CN 201911174957 A CN201911174957 A CN 201911174957A CN 112951694 B CN112951694 B CN 112951694B
- Authority
- CN
- China
- Prior art keywords
- discrete
- electrode assembly
- upper electrode
- power
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012545 processing Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000001816 cooling Methods 0.000 claims abstract description 59
- 238000006243 chemical reaction Methods 0.000 claims abstract description 29
- 238000010438 heat treatment Methods 0.000 claims abstract description 24
- 239000012495 reaction gas Substances 0.000 claims abstract description 10
- 239000002826 coolant Substances 0.000 claims description 46
- 238000012544 monitoring process Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- 230000007423 decrease Effects 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 description 22
- 230000001276 controlling effect Effects 0.000 description 8
- 238000013461 design Methods 0.000 description 5
- 230000033228 biological regulation Effects 0.000 description 4
- 230000001105 regulatory effect Effects 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229920013730 reactive polymer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32458—Vessel
- H01J37/32522—Temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention relates to a plasma processing apparatus and a method for processing a semiconductor wafer. The plasma processing device comprises a reaction cavity, wherein the reaction cavity comprises an upper electrode assembly, a lower electrode assembly, a cooling channel and a heating device. The upper electrode assembly is disposed above the reaction chamber and simultaneously serves to deliver a reaction gas into the reaction chamber. The lower electrode assembly is arranged below the reaction cavity and opposite to the upper electrode assembly and is used for bearing a wafer to be processed. The cooling channel is disposed inside the upper electrode assembly for cooling the upper electrode assembly. The heating device is disposed inside the upper electrode assembly, and includes: the plurality of discrete heaters are used for heating different areas of the upper electrode assembly; and a controller connected with the plurality of discrete heaters and respectively controlling the power of each discrete heater.
Description
Technical Field
The present invention relates to a device in the field of semiconductors, and more particularly, to a plasma processing apparatus and a method for processing a semiconductor wafer.
Background
During plasma etching, the etching rate of some processes is strongly controlled by the distribution of the temperature of the upper and lower electrodes of the etching chamber. This effect typically has the following logical process:
the deposition distribution of the reactive Polymer (Polymer) in the cavity is regulated by controlling the temperature of the upper electrode and the lower electrode, and the deposition strength of the wafer end Polyer can influence the etching rate of the wafer. The following is described:
1) The higher the upper electrode temperature (or the lower electrode wafer end temperature), the heavier the lower electrode wafer end Polymer; within a certain specific range, the faster the wafer etching rate is;
2) The lower the upper electrode temperature (or the higher the lower electrode wafer end temperature), the lighter the lower electrode wafer end Polymer; within a certain range, the slower the wafer etch rate.
Therefore, the etching rate of the wafer can be regulated and controlled by regulating the temperature of the upper electrode and the lower electrode; in addition, it is conceivable that the adjustment of the wafer etching rate uniformity and symmetry can be achieved by multi-zone control of the upper and lower electrode temperature distribution. Common multi-zone temperature control is primarily directed to the bottom electrode (electrostatic chuck), such as by a dual-coolant zone electrostatic chuck, dual-He zone electrostatic chuck, multi-zone dynamic electrostatic chuck, or the like. The main reason for controlling the temperature of the lower electrode is that the wafer is in direct contact with the electrostatic chuck, so that the etching effect is more sensitive to the temperature of the electrostatic chuck, and the regulation and control are more effective.
But there are the following disadvantages to the regulation by the lower electrode:
1) If the design of the Multi-zone adopts electric heating, the Multi-zone cannot be applied to a high-temperature high-power plasma etching process, because the design of the RF filter is difficult to meet the requirement of high power;
2) Design of Multi-zone design and use costs are intolerable if either cooling or He cooling modes are used.
Therefore, for the VNAND technology, the lower electrode of the etching cavity can only adopt a Dual-zone mode, and the asymmetry of the etching rate can not be regulated and controlled by the multi-zone temperature control of the lower electrode. Therefore, the multi-region temperature control of the upper electrode is a feasible regulation and control method. In addition, if the upper electrode does not use multi-zone temperature control, there is often serious asymmetry in the temperature distribution of the upper electrode, as shown in fig. 1, and the design has the following defects that are not tunable:
1) The heater 10 (HEATER CHANNEL) cannot achieve complete closed loop, resulting in cooler temperatures at the ends of the two leads of the heater electrode;
2) The temperature-controlled cooling channel 20 (Coolant channel) has a gradient change of water temperature, the water Inlet end (Inlet) is cold, and the water Outlet end (Outlet) is hot, so that the water cooling effect is uneven.
The above defects cause a temperature distribution to exist in Cold and Hot areas (Hot areas), and the actual measurement shows that the temperature gradient in the Cold and Hot areas reaches 7% of the average temperature, and when the heater installation angle is rotated 180 °, the Cold and Hot areas are also exchanged 180 °. Such a temperature gradient is unacceptable for electrode temperature sensitive etching processes, resulting in serious asymmetry in etch rate.
Disclosure of Invention
The present invention is directed to a plasma processing apparatus and a method for processing a semiconductor wafer, which solve the above-mentioned problems of the prior art.
In order to achieve the above object, a first aspect of the present invention provides a plasma processing apparatus, including a reaction chamber, wherein the reaction chamber includes an upper electrode assembly, a lower electrode assembly, a cooling channel, and a heating device. The upper electrode assembly is disposed above the reaction chamber and simultaneously serves to deliver a reaction gas into the reaction chamber. The lower electrode assembly is arranged below the reaction cavity and opposite to the upper electrode assembly and is used for bearing a wafer to be processed. The cooling channel is disposed inside the upper electrode assembly for cooling the upper electrode assembly. The heating device is disposed inside the upper electrode assembly, and includes: the plurality of discrete heaters are used for heating different areas of the upper electrode assembly; and a controller connected with the plurality of discrete heaters and respectively controlling the power of each discrete heater.
Optionally, a plurality of discrete heaters are annularly disposed around the inside or outside of the cooling channel.
Optionally, the controller adjusts the power of each discrete heater according to the cooling channel location corresponding to each discrete heater.
Optionally, the power sequence of the discrete heater corresponding to the coolant inlet of the cooling channel to the discrete heater corresponding to the coolant outlet of the cooling channel decreases.
Optionally, the cooling channel comprises at least one coolant inlet and one coolant outlet.
Optionally, the output power of the plurality of discrete heaters is the same, and the controller controls the power output percentage of each discrete heater respectively.
Optionally, the controller adjusts the power of the corresponding discrete heater according to an etch asymmetry point of the wafer being etched.
Optionally, thermal isolation means are provided between the different discrete heaters.
In order to achieve the above object, a second aspect of the present invention provides a method for processing a semiconductor wafer, the method being performed in a plasma processing apparatus, comprising: the wafer is transferred into the reaction chamber and placed over the lower electrode assembly. The reaction gas is supplied into the reaction chamber by the upper electrode assembly. And applying radio frequency power into the reaction cavity, exciting the reaction gas into plasma, and performing process treatment on the wafer by using the plasma. And monitoring the wafer processing result and transmitting the monitoring result to the controller. The temperature of the upper electrode assembly is controlled by the cooling channel and the heating device, and the controller adjusts the power of the heating devices in different areas according to the monitoring result of the wafer processing.
Optionally, the controller controls the heating power of the discrete heaters corresponding to the coolant inlets of the cooling channels to be sequentially decreased to the discrete heaters corresponding to the coolant outlets of the cooling channels.
Optionally, the cooling channel comprises a plurality of coolant inlets and a plurality of coolant outlets, and the controller can control the flow or temperature of the coolant entering the different coolant inlets to achieve temperature adjustment of the cooling channel of the different sections.
Optionally, the output power of the plurality of discrete heaters is the same, and the controller controls the power output percentage of each discrete heater respectively.
Optionally, the controller adjusts the power of the corresponding discrete heater according to an etch asymmetry point of the wafer being etched.
Compared with the prior art, the plasma processing device and the processing method of the semiconductor wafer respectively control the power of each discrete heater through the controller, thereby realizing the accurate selection and adjustment of the etching rate of certain etching processes.
Drawings
FIG. 1 is a schematic diagram of a heater and a temperature controlled cooling channel of a conventional plasma processing apparatus;
FIG. 2 is a schematic view of a plasma processing apparatus of the present invention;
FIG. 3 is a schematic view of a heating device and a cooling channel of the plasma processing apparatus of the present invention;
FIG. 4 is a block diagram of a heating apparatus of the plasma processing apparatus of the present invention;
Fig. 5 is a flowchart of a method for processing a semiconductor wafer in the plasma processing apparatus according to the present invention.
Detailed Description
For the purpose of promoting an understanding of the nature, content and advantages of this invention and its advantages, reference should be made to the drawings and specific language used to describe the same in connection with the accompanying drawings, which are intended to illustrate and assist in the description, but not necessarily to the actual scale and organization of the invention, so that the invention should not be construed as limited to the actual scope of the claims.
Please refer to fig. 2 to fig. 4; FIG. 2 is a schematic view of a plasma processing apparatus of the present invention; FIG. 3 is a schematic view of a heating device and a cooling channel of the plasma processing apparatus of the present invention; fig. 4 is a block diagram of a heating apparatus of the plasma processing apparatus of the present invention. As shown, in the embodiment, the present invention provides a plasma processing apparatus 300, which includes a reaction chamber 310, wherein the reaction chamber 310 includes an upper electrode assembly 320, a lower electrode assembly 330, a cooling channel 200, and a heating apparatus 100.
The upper electrode assembly 320 is disposed above the inside of the reaction chamber 310 while supplying a reaction gas into the reaction chamber 310. The lower electrode assembly 330 is disposed below the reaction chamber 310, opposite to the upper electrode assembly 320, for carrying a wafer to be processed.
The cooling passage 200 is provided inside the upper electrode assembly 320 for cooling the upper electrode assembly 320.
The heating apparatus 100 is disposed inside the upper electrode assembly 320, and includes: several discrete heaters 110 are used to heat different regions of the upper electrode assembly 320; and a controller 120 connected to the plurality of discrete heaters 110 and controlling power of each of the discrete heaters 110, respectively.
In contrast, the above-mentioned discrete heaters 110 are disposed in a ring shape, and are disposed around the inner side or the outer side of the cooling channel 200, and are not connected to each other. The controller 120 is connected to the plurality of discrete heaters 110 and controls the power of each discrete heater 110, respectively. Wherein thermal isolation means may be provided between the different discrete heaters 110.
Further, the controller 120 adjusts the power of each discrete heater 110 according to the location of the cooling channel 200 corresponding to each discrete heater 110, that is, the power of each discrete heater 110 corresponding to a different location of the cooling channel 200 may be different from that of each discrete heater 110 corresponding to other locations. Examples are as follows:
The power of each discrete heater 110 may be decreased in accordance with the order of the discrete heaters 110 from the coolant inlet 210 of the corresponding cooling channel 200 to the discrete heaters 110 of the coolant outlet 220 of the corresponding cooling channel 200. Since the temperature of the cooling channel 200 increases from the coolant inlet 210 to the coolant outlet 220, the power of each discrete heater 110 is correspondingly adjusted corresponding to different portions of the cooling channel 200, so that if the temperature of the cooling channel 200 increases from the coolant inlet 210 to the coolant outlet 220, the power of each discrete heater 110 decreases in sequence along the direction from the coolant inlet 210 to the coolant outlet 220, thereby achieving the purpose of precisely selecting and adjusting the etching rate.
Wherein the cooling channel 200 comprises at least one coolant inlet 210 and one coolant outlet 220; or the cooling channel 200 may be designed in segments with the coolant inlet 210 and the coolant outlet 220 individually.
On the other hand, when the output powers of the plurality of discrete heaters 110 are the same, the controller 120 can still achieve the purpose of controlling the power of each discrete heater 110 by controlling the power output percentage of each discrete heater 110.
When the heating device 100 of the present invention is actually applied, the controller 120 can adjust the power of the discrete heater 110 at the corresponding position according to the asymmetric point of etching of the wafer during etching, so as to achieve the purpose of precisely selecting and adjusting the etching rate.
It should be noted that, each of the discrete heaters 110 has a corresponding temperature control region, so that the temperature control region corresponding to each of the discrete heaters 110 is subjected to heat insulation treatment in order to avoid the occurrence of cross temperature control.
Referring to fig. 5, fig. 5 is a flowchart of a method for processing a semiconductor wafer in the plasma processing apparatus of the present invention. As shown in the drawings, in an embodiment, the present invention provides a method for processing a semiconductor wafer, the method being performed in the plasma processing apparatus, the method for processing a semiconductor wafer comprising the steps of:
In step S51: the wafer is transferred into the reaction chamber and placed over the lower electrode assembly. In step S52: the reaction gas is supplied into the reaction chamber by the upper electrode assembly.
In step S53: and applying radio frequency power into the reaction cavity, exciting the reaction gas into plasma, and performing process treatment on the wafer by using the plasma.
In step S54: and monitoring the wafer processing result and transmitting the monitoring result to the controller.
In step S55: the temperature of the upper electrode assembly is controlled by the cooling channel and the heating device, and the controller adjusts the power of the heating devices in different areas according to the monitoring result of the wafer processing.
Further, the controller 120 adjusts the power of each discrete heater 110 according to the location of the cooling channel 200 corresponding to each discrete heater 110, that is, the power of each discrete heater 110 corresponding to a different location of the cooling channel 200 may be different from that of each discrete heater 110 corresponding to other locations. Examples are as follows:
The power of each discrete heater 110 may be decreased in accordance with the order of the discrete heaters 110 from the coolant inlet 210 of the corresponding cooling channel 200 to the discrete heaters 110 of the coolant outlet 220 of the corresponding cooling channel 200. Since the temperature of the cooling channel 200 increases from the coolant inlet 210 to the coolant outlet 220, the power of each discrete heater 110 is correspondingly adjusted corresponding to different portions of the cooling channel 200, so that if the temperature of the cooling channel 200 increases from the coolant inlet 210 to the coolant outlet 220, the power of each discrete heater 110 decreases in sequence along the direction from the coolant inlet 210 to the coolant outlet 220, thereby achieving the purpose of precisely selecting and adjusting the etching rate.
In turn, the cooling channel 200 includes a number of coolant inlets 210 and a number of coolant outlets, and the controller 120 may control the flow or temperature of coolant entering the different coolant inlets 210 to achieve temperature regulation of the cooling channel 200 in different sections.
On the other hand, when the output powers of the plurality of discrete heaters 110 are the same, the controller 120 can still achieve the purpose of controlling the power of each discrete heater 110 by controlling the power output percentage of each discrete heater 110.
When the heating device 100 of the present invention is actually applied, the controller 120 can adjust the power of the discrete heater 110 at the corresponding position according to the asymmetric point of etching of the wafer during etching, so as to achieve the purpose of precisely selecting and adjusting the etching rate.
It should be noted that, each of the discrete heaters 110 has a corresponding temperature control region, so that the temperature control region corresponding to each of the discrete heaters 110 can be heat-insulated to avoid the occurrence of cross temperature control.
Compared with the prior art, the plasma processing device and the processing method of the semiconductor wafer respectively control the power of each discrete heater through the controller, thereby realizing the accurate selection and adjustment of the etching rate of certain etching processes.
While the present invention has been described in detail through the foregoing description of the preferred embodiment, it should be understood that the foregoing description is not to be considered as limiting the invention. Many modifications and substitutions of the present invention will become apparent to those of ordinary skill in the art upon reading the foregoing. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (10)
1. A plasma processing apparatus comprising a reaction chamber, wherein the reaction chamber comprises:
An upper electrode assembly disposed above the reaction chamber and for supplying a reaction gas into the reaction chamber;
The lower electrode assembly is arranged below the reaction cavity, is arranged opposite to the upper electrode assembly and is used for bearing a wafer to be processed;
A cooling channel provided inside the upper electrode assembly for cooling the upper electrode assembly; and
Heating device, set up in the upper electrode subassembly is inside, include:
the plurality of discrete heaters are formed into an annular shape, are arranged around the inner side or the outer side of the cooling channel and are positioned on the same plane with the cooling channel, and are used for heating different areas of the upper electrode assembly; and
A controller connected with the plurality of discrete heaters and respectively controlling the power of each discrete heater; the controller adjusts the power of each discrete heater according to the cooling channel part corresponding to each discrete heater;
The power sequence of the discrete heaters corresponding to the coolant inlets of the cooling channels to the discrete heaters corresponding to the coolant outlets of the cooling channels decreases.
2. The plasma processing apparatus of claim 1 wherein said cooling channel comprises at least one coolant inlet and one coolant outlet.
3. The plasma processing apparatus of claim 1 wherein the output power of said plurality of discrete heaters is the same, and said controller controls the power output percentages of each of said discrete heaters, respectively.
4. The plasma processing apparatus of claim 1 wherein the controller adjusts the power of the corresponding discrete heater in accordance with an etch asymmetry point of the wafer being etched.
5. The plasma processing apparatus of claim 1 wherein thermal isolation means is provided between different ones of said discrete heaters.
6. A method of processing a semiconductor wafer, the method being performed in the plasma processing apparatus according to any one of claims 1 to 5, comprising the steps of:
transferring the wafer into the reaction chamber and placing the wafer above the lower electrode assembly;
Supplying a reaction gas into the reaction chamber using the upper electrode assembly;
Applying radio frequency power into the reaction cavity, exciting the reaction gas into plasma, and performing process treatment on the wafer by using the plasma;
Monitoring the wafer processing result and transmitting the monitoring result to the controller;
And controlling the temperature of the upper electrode assembly by utilizing the cooling channel and the heating device, wherein the controller adjusts the power of the heating device in different areas according to the monitoring result of the wafer processing.
7. The method of processing a semiconductor wafer according to claim 6, wherein the controller controls the heating power of the discrete heater corresponding to the coolant inlet of the cooling channel to the discrete heater corresponding to the coolant outlet of the cooling channel to be sequentially decreased.
8. The method of claim 6, wherein the cooling channels comprise a plurality of coolant inlets and a plurality of coolant outlets, the controller being operable to control coolant flow or temperature into different ones of the coolant inlets to effect temperature adjustment of different sections of the cooling channels.
9. The method of claim 6, wherein the output power of the plurality of discrete heaters is the same, and the controller controls the power output percentages of the discrete heaters, respectively.
10. The method of claim 6, wherein the controller adjusts the power of the corresponding discrete heater based on an etch asymmetry point of the wafer being etched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911174957.7A CN112951694B (en) | 2019-11-26 | 2019-11-26 | Plasma processing apparatus and method for processing semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911174957.7A CN112951694B (en) | 2019-11-26 | 2019-11-26 | Plasma processing apparatus and method for processing semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112951694A CN112951694A (en) | 2021-06-11 |
| CN112951694B true CN112951694B (en) | 2024-05-10 |
Family
ID=76225245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911174957.7A Active CN112951694B (en) | 2019-11-26 | 2019-11-26 | Plasma processing apparatus and method for processing semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112951694B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1050666A (en) * | 1996-07-30 | 1998-02-20 | Nec Corp | Plasma-treating apparatus |
| KR20030012732A (en) * | 2001-08-04 | 2003-02-12 | 삼성전자주식회사 | Method for using air cooling dry etch apparatus |
| JP2007096189A (en) * | 2005-09-30 | 2007-04-12 | Epson Imaging Devices Corp | Method for managing plasma cvd device |
| CN101389178A (en) * | 2007-09-14 | 2009-03-18 | 爱德牌工程有限公司 | Substrate processing apparatus having electrode member |
| JP2009173969A (en) * | 2008-01-22 | 2009-08-06 | Tokyo Electron Ltd | Temperature control mechanism, and processing device using the same |
| CN101842877A (en) * | 2007-10-31 | 2010-09-22 | 朗姆研究公司 | Temperature control module using gas pressure to control thermal conductance between liquid coolant and component body |
| CN102446738A (en) * | 2011-11-29 | 2012-05-09 | 上海华力微电子有限公司 | Plasma etching device |
| CN102907181A (en) * | 2010-05-27 | 2013-01-30 | 应用材料公司 | Component temperature control by coolant flow control and heater duty cycle control |
| CN103681304A (en) * | 2012-09-24 | 2014-03-26 | 朗姆研究公司 | Showerhead electrode assembly in a capacitively coupled plasma processing apparatus |
| CN103972130A (en) * | 2013-02-01 | 2014-08-06 | 株式会社日立高新技术 | Plasma processing apparatus and sample stage thereof |
| CN106716608A (en) * | 2014-08-01 | 2017-05-24 | 应用材料公司 | Wafer carrier with independent isolated heater zones |
| CN110352479A (en) * | 2017-06-19 | 2019-10-18 | 应用材料公司 | Semiconductor processing chamber temperature device in situ |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8375890B2 (en) * | 2007-03-19 | 2013-02-19 | Micron Technology, Inc. | Apparatus and methods for capacitively coupled plasma vapor processing of semiconductor wafers |
| US9793097B2 (en) * | 2015-07-27 | 2017-10-17 | Lam Research Corporation | Time varying segmented pressure control |
| KR102587615B1 (en) * | 2016-12-21 | 2023-10-11 | 삼성전자주식회사 | Temperature controller of a plasma-processing apparatus and plasma-processing apparatus including the same |
-
2019
- 2019-11-26 CN CN201911174957.7A patent/CN112951694B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1050666A (en) * | 1996-07-30 | 1998-02-20 | Nec Corp | Plasma-treating apparatus |
| KR20030012732A (en) * | 2001-08-04 | 2003-02-12 | 삼성전자주식회사 | Method for using air cooling dry etch apparatus |
| JP2007096189A (en) * | 2005-09-30 | 2007-04-12 | Epson Imaging Devices Corp | Method for managing plasma cvd device |
| CN101389178A (en) * | 2007-09-14 | 2009-03-18 | 爱德牌工程有限公司 | Substrate processing apparatus having electrode member |
| CN101842877A (en) * | 2007-10-31 | 2010-09-22 | 朗姆研究公司 | Temperature control module using gas pressure to control thermal conductance between liquid coolant and component body |
| JP2009173969A (en) * | 2008-01-22 | 2009-08-06 | Tokyo Electron Ltd | Temperature control mechanism, and processing device using the same |
| CN102907181A (en) * | 2010-05-27 | 2013-01-30 | 应用材料公司 | Component temperature control by coolant flow control and heater duty cycle control |
| CN102446738A (en) * | 2011-11-29 | 2012-05-09 | 上海华力微电子有限公司 | Plasma etching device |
| CN103681304A (en) * | 2012-09-24 | 2014-03-26 | 朗姆研究公司 | Showerhead electrode assembly in a capacitively coupled plasma processing apparatus |
| CN103972130A (en) * | 2013-02-01 | 2014-08-06 | 株式会社日立高新技术 | Plasma processing apparatus and sample stage thereof |
| CN106716608A (en) * | 2014-08-01 | 2017-05-24 | 应用材料公司 | Wafer carrier with independent isolated heater zones |
| CN110352479A (en) * | 2017-06-19 | 2019-10-18 | 应用材料公司 | Semiconductor processing chamber temperature device in situ |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112951694A (en) | 2021-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102259258B1 (en) | Advanced temperature control for wafer carrier in plasma processing chamber | |
| JP7301903B2 (en) | Substrate carrier using proportional thermal fluid delivery system | |
| TWI481297B (en) | Method and apparatus for controlling spatial temperature distribution | |
| US7649729B2 (en) | Electrostatic chuck assembly | |
| US9410753B2 (en) | Substrate temperature adjusting method and a method of changing the temperature control range of a heater in a substrate processing apparatus | |
| US20140287375A1 (en) | Insulation structure and method of manufacturing semiconductor device | |
| WO2010053173A1 (en) | Apparatus and method for controlling temperature of semiconductor wafer | |
| US20220277982A1 (en) | Temperature tunable multi-zone electrostatic chuck | |
| JP6240532B2 (en) | Electrostatic chuck temperature control method | |
| CN112951694B (en) | Plasma processing apparatus and method for processing semiconductor wafer | |
| CN113130279B (en) | Lower electrode assembly, plasma processing device and working method thereof | |
| CN220895451U (en) | Temperature control system | |
| US20220010428A1 (en) | Substrate support, apparatus for processing substrate, and method of adjusting temperature of substrate | |
| US11929240B2 (en) | Substrate support, substrate processing apparatus, and substrate processing method | |
| TWI837299B (en) | Temperature tunable multi-zone electrostatic chuck | |
| KR20110083979A (en) | Plasma processing apparatus | |
| JP4230716B2 (en) | Substrate processing equipment | |
| CN115692294A (en) | Semiconductor processing equipment and control method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |