CN112951302B - Nonvolatile memory cell, memory and device - Google Patents
Nonvolatile memory cell, memory and device Download PDFInfo
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- CN112951302B CN112951302B CN202110134691.4A CN202110134691A CN112951302B CN 112951302 B CN112951302 B CN 112951302B CN 202110134691 A CN202110134691 A CN 202110134691A CN 112951302 B CN112951302 B CN 112951302B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
- G11C16/105—Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
Abstract
The invention provides a nonvolatile storage unit, a memory and equipment, which comprise a data writing module, a first node, a second node, a pull-up network, a pull-down network and a temporary storage module, wherein the data writing module is used for writing data into the first node; the data writing module is respectively connected with the first node and the second node and is used for writing a first level and a second level into the first node and the second node respectively; the pull-up network and the pull-down network are used for maintaining the level of the first node and the second node; the temporary storage module comprises a first magnetic storage unit, a second magnetic storage unit and a reinforcing circuit, and the temporary storage module can effectively prevent the nonvolatile storage from being interfered by SEU in the data storage and data backup process, so that the radiation resistance and the reliability of the nonvolatile storage unit are improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a nonvolatile memory cell, a memory, and a device.
Background
Data loss is caused after power failure of a Static Random Access Memory (SRAM) utilizing charge charging/discharging, and the phenomenon of Single Event Upset (SEU) is easily caused by high-energy particles in space, so that normal operation of an aircraft is seriously threatened. In addition, the SRAM has the problems of large power consumption, easy data loss and the like, and the requirement in the aerospace field is difficult to meet. In recent years, some new nonvolatile SRAM (NVSRAM) has been introduced. The Magnetic Tunnel Junction (MTJ) realizes data storage by using a spin orbit torque effect and a spin transfer torque effect together, is considered to be one of the most potential nonvolatile electronic devices, has the characteristics of nonvolatility, low power consumption, quick access, inherent irradiation resistance and the like, and has great application potential in the field of future aerospace. In the working mode, data are stored through the SRAM. Before the power supply is powered down, the data information is stored in the MTJ which is cooperatively written to form data backup. After the power is on, the data in the MTJ is stored in the SRAM to complete data recovery, so that the problem of power failure data loss of the conventional volatile storage unit is effectively solved, and static power consumption is reduced.
However, when data is stored in the SRAM, a sensitive node exists between the two inverters connected end to end. In addition, during data backup, the control transistor is in an off state, and when the control transistor is hit by a radiation particle with enough energy, the transient current pulse generated causes data information error written into the MTJ. Therefore, the conventional NVSRAM is susceptible to SEU, soft errors occur, reliability of stored data is affected, and the NVSRAM cannot be applied to a space radiation environment.
Disclosure of Invention
One objective of the present invention is to provide a nonvolatile memory cell, which can effectively avoid the interference of SEU in the NVSRAM storage and data backup processes, thereby improving the radiation resistance and reliability of the NVSRAM. It is another object of the present invention to provide a nonvolatile memory. It is a further object of this invention to provide such a computer apparatus.
In order to achieve the above object, the present invention discloses a nonvolatile memory cell, which includes a data writing module, a first node, a second node, a pull-up network, a pull-down network, and a temporary storage module;
the data writing module is respectively connected with the first node and the second node and is used for writing a first level and a second level into the first node and the second node respectively; the pull-up network and the pull-down network are used for maintaining the levels of the first node and the second node;
the temporary storage module comprises a first magnetic storage unit, a second magnetic storage unit and a reinforcing circuit, wherein a current input end and a current output end of the first magnetic storage unit are respectively connected with the first node and the third node, a current input end and a current output end of the second magnetic storage unit are respectively connected with the third node and the second node, the resistance states of the first magnetic storage unit and the second magnetic storage unit are respectively corresponding to the first level and the second level on the basis of the potential difference of the first node and the second node in response to a temporary storage signal, and the reinforcing circuit is used for keeping the level of the third node.
Preferably, the data writing module includes a first writing switching element and a second writing switching element;
a control terminal of the first write switch element is used for receiving a write signal, a first terminal of the first write switch element is connected with a first signal input terminal for providing a first level, and a second terminal of the first write switch element is connected with the first node;
a control terminal of the second write switch element is configured to receive the write signal, a first terminal of the second write switch element is connected to a second signal input terminal that provides a second level, and a second terminal of the second write switch element is connected to the second node;
the first write switch element turns on the first signal input terminal and the first node in response to the write signal, writing the first level to the first node; the second write switch element turns on the second signal input terminal and the second node in response to the write signal, and writes the second level to the second node.
Preferably, the pull-up network includes a first pull-up switching element, a second pull-up switching element, a third pull-up switching element, a fourth pull-up switching element, a first redundant node, and a second redundant node;
a control end of the first pull-up switching element is connected with the second redundant node, a first end of the first pull-up switching element is connected with a first power supply end, and a second end of the first pull-up switching element is connected with the first redundant node;
the control end of the second pull-up switching element is connected with the first redundant node, the first end of the second pull-up switching element is connected with the first power supply end, and the second end of the second pull-up switching element is connected with the second redundant node;
a control end of the third pull-up switching element is connected with a second power end, a first end of the third pull-up switching element is connected with the first redundant node, and a second end of the third pull-up switching element is connected with the first node;
and the control end of the fourth pull-up switching element is connected with a second power supply end, the first end of the fourth pull-up switching element is connected with the second redundant node, and the second end of the fourth pull-up switching element is connected with the second node.
Preferably, the pull-down network includes a first pull-down switching element, a second pull-down switching element, a third pull-down switching element, a fourth pull-down switching element, a third redundant node, and a fourth redundant node;
the control end of the first pull-down switching element is connected with a third power supply end, the first end of the first pull-down switching element is connected with the first node, and the second end of the first pull-down switching element is connected with the third redundant node;
a control end of the second pull-down switching element is connected with the third power supply end, a first end of the second pull-down switching element is connected with the second node, and a second end of the second pull-down switching element is connected with the fourth redundant node;
the control end of the third pull-down switch element is connected with the fourth redundant node, the first end of the third pull-down switch element is connected with the third redundant node, and the second end of the third pull-down switch element is connected with the ground end;
and the control end of the fourth pull-down switch element is connected with the third redundant node, the first end of the fourth pull-down switch element is connected with the fourth redundant node, and the second end of the fourth pull-down switch element is connected with the ground end.
Preferably, the temporary storage module further includes a temporary storage control circuit, configured to turn on the first node and a current input terminal of the first magnetic storage unit in response to the temporary storage signal, and turn on the second node and a current output terminal of the second magnetic storage unit in response to the temporary storage signal.
Preferably, the first magnetic storage unit includes a first spin orbit torque layer and a first magnetic tunnel junction provided on the first spin orbit torque layer; the second magnetic storage unit includes a second spin orbit torque layer and a first magnetic tunnel junction disposed on the second spin orbit torque layer.
Preferably, the temporary storage control circuit comprises a first temporary storage switch element, a second temporary storage switch element, a third temporary storage switch element and a fourth temporary storage switch element;
the control end of the first temporary storage switch element is used for receiving the temporary storage signal, the first end of the first temporary storage switch element is connected with the first node, and the second end of the first temporary storage switch element is connected with the current input end of the first magnetic storage unit;
a control end of the second temporary storage switching element is connected with a fourth power supply end, a first end of the second temporary storage switching element is connected with the first node, and a second end of the second temporary storage switching element is connected with the top end of the first magnetic tunnel junction;
a control end of the third temporary storage switching element is connected with the fourth power supply end, a first end of the third temporary storage switching element is connected with the second node, and a second end of the third temporary storage switching element is connected with the top end of the second magnetic tunnel junction;
and the control end of the fourth temporary storage switching element is used for receiving the temporary storage signal, the first end of the fourth temporary storage switching element is connected with the second node, and the second end of the fourth temporary storage switching element is connected with the current output end of the second magnetic tunnel junction.
Preferably, the reinforcement circuit is configured to charge the third node to maintain the level of the third node when a single event upset occurs in the third node in response to an enable signal.
Preferably, the ruggedized circuit includes a first ruggedized switching element and a second ruggedized switching element;
the first end of the first reinforced switch element is connected with a fifth power supply end, and the control end is respectively connected with the second end and the third node;
the control end of the second reinforced switch element is used for receiving an enabling signal, the first end of the second reinforced switch element is connected with the third node, and the second end of the second reinforced switch element is connected with the grounding end.
Preferably, the temporary storage module further includes a precharge circuit configured to write a high level to the first node and the second node in response to a precharge signal when data is restored, and the first node becomes a first level and the second node becomes a second level under the action of the first magnetic storage unit and the second magnetic storage unit in different resistance states.
The invention also discloses a nonvolatile memory, which comprises a plurality of nonvolatile memory units arranged in an array.
The invention also discloses a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor,
the processor and/or the memory include non-volatile storage units as described above.
Aiming at the sensitive node in the nonvolatile storage unit, the invention adopts the pull-up network and the pull-down network to avoid the propagation of the SEU effect of the sensitive node in the nonvolatile storage unit, so that when the sensitive node in the nonvolatile storage unit is subjected to level inversion due to SEU, the initial state can be quickly recovered through the pull-up network and the pull-down network, and the first level and the second level written by the first node and the second node are kept. Meanwhile, the reinforcing circuit is arranged in the temporary storage module, so that the level stability of the sensitive node between the first magnetic storage unit and the second magnetic storage unit is kept, and when the level of the third node is turned over due to SEU, the reinforcing circuit can charge the third node in time, and the accuracy of data storage and backup is ensured. The invention can effectively avoid the interference of SEU in the storage and data backup processes of the NVSRAM, thereby improving the radiation resistance and the reliability of the nonvolatile storage unit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram illustrating one embodiment of a non-volatile memory cell of the present invention;
FIG. 2 shows a schematic block diagram of a computer device suitable for use in implementing embodiments of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
According to one aspect of the invention, the present embodiment discloses a non-volatile memory cell. As shown in fig. 1, the nonvolatile memory cell includes a data write module, a first node Q, a second node QB, a pull-up network, a pull-down network, and a temporary storage module.
The data writing module is respectively connected to the first node Q and the second node QB, and is configured to write a first level and a second level into the first node Q and the second node QB, respectively; the pull-up network and the pull-down network are used to maintain the levels of the first node Q and the second node QB.
The temporary storage module comprises a first magnetic storage unit, a second magnetic storage unit and a reinforcing circuit, wherein a current input end and a current output end of the first magnetic storage unit are respectively connected with a first node Q and a third node P, a current input end and a current output end of the second magnetic storage unit are respectively connected with the third node P and a second node QB, the resistance state of the first magnetic storage unit and the resistance state of the second magnetic storage unit are respectively corresponding to the first level and the second level on the basis of the potential difference of the first node Q and the second node QB in response to a temporary storage signal W _ EN, and the reinforcing circuit is used for keeping the level of the third node P.
Aiming at the sensitive nodes in the nonvolatile storage unit, the invention adopts the pull-up network and the pull-down network to avoid the propagation of SEU effect of the sensitive nodes in the nonvolatile storage unit, so that when the sensitive nodes in the nonvolatile storage unit are subjected to level inversion due to SEU, the sensitive nodes can be quickly recovered to the initial state through the pull-up network and the pull-down network, and the first level and the second level written in the first node Q and the second node QB are kept. Meanwhile, the reinforcement circuit is arranged in the temporary storage module, so that the level stability of the sensitive node between the first magnetic storage unit and the second magnetic storage unit is kept, and when the level of the third node P is turned over due to SEU, the reinforcement circuit can timely charge the third node P, and the accuracy of data storage and backup is ensured. The invention can effectively avoid the interference of SEU in the storage and data backup processes of the NVSRAM, thereby improving the radiation resistance and the reliability of the nonvolatile storage unit.
In a preferred embodiment, as shown in fig. 1, the data writing module includes a first write switch element N11 and a second write switch element N12. The control terminal of the first write switch element N11 is configured to receive the write signal WL, the first terminal of the first write switch element is connected to a first signal input terminal providing a first level, and the second terminal of the first write switch element is connected to the first node Q. The second write switch element N12 has a control terminal for receiving the write signal WL, a first terminal connected to a second signal input terminal providing a second level, and a second terminal connected to the second node QB. The first write switching element N11 turns on the first signal input terminal and the first node Q in response to the write signal WL, writing the first level to the first node Q; the second write switching element N12 turns on the second signal input terminal and the second node QB in response to the write signal WL, writing the second level to the second node QB. In the preferred embodiment, the first level of the first signal input terminal can be written into the first node Q by controlling the on state of the first write switching element N11, and the second level of the second signal input terminal can be written into the second node QB by controlling the on state of the second write switching element N12. The first level and the second level may correspond to different logic numbers, for example, the first level corresponds to a logic number "1", and the second level corresponds to a logic number "0", that is, temporary storage of the logic number "1" and the logic number "0" at the first node Q and the second node QB may be achieved by inputting the write signal WL to the control terminals of the first write switch element N11 and the second write switch element N12, respectively. In other embodiments, the writing of the first level and the second level may be implemented by other circuit structures, and a person skilled in the art may determine the specific structure of the data writing module according to actual requirements, which is not limited by the present invention.
In a preferred embodiment, as shown in fig. 1, the pull-up network includes a first pull-up switching element P21, a second pull-up switching element P22, a third pull-up switching element P23, a fourth pull-up switching element P24, a first redundant node S1 and a second redundant node S2. A control end of the first pull-up switching element P21 is connected to the second redundant node S2, a first end of the first pull-up switching element is connected to a first power supply end Vdd1, and a second end of the first pull-up switching element is connected to the first redundant node S1; a control end of the second pull-up switching element P22 is connected to the first redundant node S1, a first end is connected to a first power supply terminal Vdd1, and a second end is connected to the second redundant node S2; a control end of the third pull-up switching element P23 is connected to a second power supply end Vdd2, a first end of the third pull-up switching element P is connected to the first redundant node S1, and a second end of the third pull-up switching element P23 is connected to the first node Q; a control terminal of the fourth pull-up switching element P24 is connected to the second power supply terminal Vdd2, a first terminal thereof is connected to the second redundant node S2, and a second terminal thereof is connected to the second node QB.
In a preferred embodiment, as shown in fig. 1, the pull-down network includes a first pull-down switching element N21, a second pull-down switching element N22, a third pull-down switching element N23, a fourth pull-down switching element N24, a third redundant node S3, and a fourth redundant node S4. Wherein, the control terminal of the first pull-down switching element N21 is connected to the third power terminal Vdd3, the first terminal is connected to the first node Q, and the second terminal is connected to the third redundant node S3; a control terminal of the second pull-down switching element N22 is connected to the third power supply terminal Vdd3, a first terminal thereof is connected to the second node QB, and a second terminal thereof is connected to the fourth redundant node S4; a control end of the third pull-down switching element N23 is connected to the fourth redundant node S4, a first end is connected to the third redundant node S3, and a second end is connected to a ground end GND; a control end of the fourth pull-down switching element N24 is connected to the third redundant node S3, a first end is connected to the fourth redundant node S4, and a second end is connected to a ground GND.
It can be understood that in the data writing and normal operation state of the nonvolatile memory cell, the temporary storage module does not receive the temporary storage signal W _ EN and does not store data. At this time, the first node Q is at the first level and the second node QB is at the second level by the write signal WL, and the level states of the first node Q and the second node QB are temporary, which belongs to a volatile structure. During the period, when data is written in and normally operates, the temporary storage module serving as the nonvolatile structure does not temporarily store data, and mutual isolation of the volatile structure and the nonvolatile structure is realized.
In a normal operation state, the third pull-up switching element P23 and the fourth pull-up switching element P24 are turned on by the second power source terminal Vdd2, and the first pull-down switching element N21 and the second pull-down switching element N22 are also turned on by the third power source terminal Vdd3, so that the first node Q and the second node QB are insensitive nodes, and the levels of the first node Q and the second node QB can be kept stable.
In addition, four redundant nodes, namely a first redundant node S1, a second redundant node S2, a third redundant node S3 and a fourth redundant node S4, exist in the pull-up network and the pull-down network, and when the four redundant nodes generate SEU effect to cause level inversion, the pull-up network and the pull-down network can also enable the level of the redundant node with SEU to be quickly restored, so that the levels of the first node Q and the second node QB are ensured to be stable, and correct writing of data is ensured. Specifically, for example, when the write signal WL is input to the control terminals of the first and second write switch elements N11 and N12, the first and second write switch elements N11 and N12 are turned on, the first levels of the first and second input terminals BL and BLB are written to the first node Q, and the second levels of the second input terminal BLB are written to the second node QB, assuming that the first and second levels correspond to logic numbers "1" and "0", respectively. At this time, the levels of the first and third redundant nodes S1 and S3 are a first level, i.e., digital "1", and the levels of the second and fourth redundant nodes S2 and S4 are a second level, i.e., digital "0". The second pull-up switching element P22 and the third pull-down switching element N23 are turned off, so the second redundant node S2 and the third redundant node S3 are sensitive nodes. If the second redundant node S2 has an SEU to cause a level to be pulled high, the first pull-up switching element P21 is turned off, and other nodes still maintain an initial state at this time and are not affected, and a transient current caused by the SEU can be released through the fourth pull-up switching element P24, the second pull-down switching element N22 and the fourth pull-down switching element N24, so that the flipped second redundant node S2 is quickly recovered, and correct writing of data of the two nodes, i.e., the first node Q and the second node QB, is ensured.
In a preferred embodiment, the temporary storage module further includes a temporary storage control circuit for turning on the current input terminals of the first node Q and the first magnetic storage element in response to the temporary storage signal W _ EN, and turning on the current output terminals of the second node QB and the second magnetic storage element in response to the temporary storage signal W _ EN. The nonvolatile memory cell can be applied to a computer or other devices, and before the computer or other devices enter a standby state, data written in by the first node Q and the second node QB needs to be stored, at this time, a temporary storage signal W _ EN is input to the temporary storage module, so that the resistance states of the first magnetic memory cell and the second magnetic memory cell in the temporary storage module correspond to the data of the first node Q and the second node QB. Since the first magnetic storage unit and the second magnetic storage unit are nonvolatile memory devices, the logic data written by the first node Q and the second node QB can be still stored after the device is powered off in a standby mode.
In a preferred embodiment, the first magnetic storage unit includes a first spin orbit torque layer and a first magnetic tunnel junction MTJ1 provided on the first spin orbit torque layer; the second magnetic storage unit comprises a second spin orbit torque layer and a first magnetic tunnel junction MTJ1MTJ1 arranged on the second spin orbit torque layer. It is understood that a Magnetic tunnel junction is a basic Memory cell of a Magnetic Random Access Memory (MRAM). Spin-transfer torque MTJ (STT-MTJ) has the disadvantages of long incubation time, read-write interference and the like, and further development of the STT-MTJ is limited. Spin-orbit torque MTJ (Spin-orbit torque MTJ) receives wide attention from the industry and academia because it has the advantages of fast writing speed, separate read/write path, and low power consumption. Based on the preferred embodiment, the first magnetic storage unit and the second magnetic storage unit adopt the SOT data writing method, thereby improving the writing speed and reliability. More preferably, the STT is a technique that can flip the magnetic moment of the magnetic tunnel junction device, and the SOT is a technique that a heavy metal layer is disposed under the magnetic tunnel junction, and a current flows through the heavy metal layer to flip the magnetic moment of the magnetic tunnel junction. However, the magnetization switching direction of the SOT-MTJ is uncertain due to a symmetrical structure, an extra magnetic field needs to be added to realize the deterministic switching during the SOT writing, the process difficulty is increased, and the development of the SOT-MTJ is limited. In order to solve the problems, a data writing mode of cooperation of STT and SOT can be adopted, the direction of STT writing current is changed to realize the deterministic reversal of the magnetization direction, so that the storage of '0' and '1' is completed, and the writing speed can reach sub-nanosecond level.
In a preferred embodiment, the temporary storage control circuit includes a first temporary storage switching element N31, a second temporary storage switching element N32, a third temporary storage switching element N33, and a fourth temporary storage switching element N34.
A control end of the first temporary storage switching element N31 is configured to receive the temporary storage signal W _ EN, a first end of the first temporary storage switching element is connected to the first node Q, and a second end of the first temporary storage switching element is connected to a current input end of the first magnetic storage unit; a control end of the second temporary storage switching element N32 is connected to a fourth power supply end Vdd4, a first end is connected to the first node Q, and a second end is connected to a top end of the first magnetic tunnel junction MTJ1; a control terminal of the third temporary storage switching element N33 is connected to the fourth power supply terminal Vdd4, a first terminal thereof is connected to the second node QB, and a second terminal thereof is connected to a top end of the second magnetic tunnel junction MTJ 2; the control terminal of the fourth temporary storage switching element N34 is configured to receive the temporary storage signal W _ EN, the first terminal of the fourth temporary storage switching element N is connected to the second node QB, and the second terminal of the fourth temporary storage switching element N is connected to the current output terminal of the second magnetic tunnel junction MTJ 2.
It is to be understood that, in the preferred embodiment, the STT and SOT cooperative writing manner is adopted, and data corresponding to the levels of the first node Q and the second node QB is stored in the first magnetic storage unit and the second magnetic storage unit, even if the resistance states of the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 correspond to the levels of the first node Q and the second node QB. In the normal operation state, the second temporary storage switching element N32 and the third temporary storage switching element N33 are turned off by the fourth power source terminal Vdd 4. The first temporary storage switching element N31 and the second temporary storage switching element N32 are also in an off state without the temporary storage signal W _ EN or the level of the temporary storage signal W _ EN, so that the temporary storage module does not perform a data storage operation. In the data temporary storage stage, the first temporary storage switching element N31 to the fourth temporary storage switching element N34 are turned on by controlling the levels of the fourth power supply terminal Vdd4 and the temporary storage signal W _ EN, a potential difference exists between the first node Q of the first level and the second node QB of the second level, the first node Q, the first magnetic storage unit, the second magnetic storage unit and the second node QB form a path, and a current is formed under the action of the potential difference, after current flows through the first spin orbit torque layer and the second spin orbit torque layer, the magnetic torque directions of free layers of the first magnetic tunnel junction MTJ1MTJ 2MTJ2 and the second magnetic tunnel junction MTJ2MTJ2 are changed, so that the resistance states of the first magnetic tunnel junction MTJ1MTJ 2 and the second magnetic tunnel junction MTJ2 are changed, the resistance states of the first magnetic tunnel junction MTJ1MTJ 2 and the second magnetic tunnel junction MTJ2 are respectively corresponding to a first level and a second level, and data writing operation is realized.
In a preferred embodiment, the reinforcement circuit is configured to charge the third node P to maintain the level of the third node P when a single event upset occurs on the third node P in response to an enable signal R _ EN.
It is understood that for the unreinforced temporary storage module, a third node P of the sensitive node is formed between the first magnetic storage unit and the second magnetic storage unit. When SEU occurs on the third node P, the third node P is pulled to a low potential, which changes the direction of the current flowing through the first magnetic storage unit or the second magnetic storage unit, and further changes the resistance state of the first magnetic tunnel junction MTJ1 or the second magnetic tunnel junction MTJ2, thereby causing an error in data storage. Therefore, in the preferred embodiment, by providing the reinforcement circuit, the third node P can be charged in time when an SEU occurs at the third node P, the level of the third node P is pulled high, the accuracy of the direction of the current flowing through the first magnetic storage unit or the second magnetic storage unit is ensured, and the resistance state of the first magnetic tunnel junction MTJ1MTJ 2MTJ 1MTJ 2MTJ is accurately or quickly restored.
In a preferred embodiment, the hardened circuit includes a first hardened switching element P35 and a second hardened switching element N36. Wherein, the first terminal of the first reinforced switch element P35 is connected to a fifth power supply terminal Vdd5, and the control terminal is connected to the second terminal and the third node P, respectively; the control terminal of the second ruggedized switch element N36 is configured to receive the enable signal R _ EN, the first terminal of the second ruggedized switch element is connected to the third node P, and the second terminal of the second ruggedized switch element is connected to the ground GND.
It is understood that when the data is temporarily stored, the enable signal R _ EN is input to the control terminal of the second ruggedized switching element N36 to turn off the second ruggedized switching element N36, and the first ruggedized switching element P35 having the control terminal connected to the second terminal can maintain the level of the third node P. When the level of the third node P is pulled down due to SEU, the fifth power supply terminal Vdd5 may charge the third node P, so that the level of the third node P can be pulled up as soon as possible, and the resistance state of the first magnetic tunnel junction MTJ1 or the second magnetic tunnel junction MTJ2 is restored.
In a preferred embodiment, the temporary storage module further includes a precharge circuit for writing a high level to the first node Q and the second node QB in response to a precharge signal PRE when data is restored, and the first node Q becomes a first level and the second node QB becomes a second level by the first magnetic storage unit and the second magnetic storage unit in different resistance states.
It is to be understood that, in the preferred embodiment, when the device is in standby mode and data needs to be restored, the first node Q and the second node QB may be first written to high level by the precharge circuit. Then, the high levels of the first and second nodes Q and QB have potential differences from the first and second magnetic storage cells, respectively, to form currents. High-level formed currents of the first node Q and the second node QB are inputted from top ends of the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 respectively, the resistance states of the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 are different, so that the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 have different resistances. Therefore, the current flowing through the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 have different changing speeds, and the voltage of the node (the first node Q or the second node QB) corresponding to the high resistance magnetic tunnel junction is first discharged to a low level, so that the node discharged to the low level can be maintained at the low level by the pull-up network and the pull-down network, and the other node (the second node QB or the first node Q) can be maintained at the high level, thereby implementing data recovery.
In a preferred embodiment, the pre-charge circuit may include a first pre-charge switching device P41 and a second pre-charge switching device P42. The control terminal of the first precharge switching element P41 is configured to receive the precharge signal PRE, and has a first terminal connected to the first power supply terminal Vdd1 and a second terminal connected to the first node Q. The second precharge switching element P42 has a control terminal for receiving the precharge signal PRE, a first terminal connected to the first power terminal Vdd1, and a second terminal connected to the second node QB. In the preferred embodiment, the first and second precharge switching elements P41 and P42 are turned on in response to the precharge signal PRE, so that the first power source terminal Vdd1 may charge the first and second nodes Q and QB, respectively, to facilitate fast reading of data stored in the temporary storage block.
The invention will be further illustrated by means of a specific example. As shown in fig. 1, the first write switch element N11, the second write switch element N12, the first pull-down switch element N21, the second pull-down switch element N22, the third pull-down switch element N23, the fourth pull-down switch element N24, the first temporary storage switch element N31, the second temporary storage switch element N32, the third temporary storage switch element N33, the fourth temporary storage switch element N34, and the second hardened switch element N36 are NMOS transistors. The first pre-charge switching device P41, the second pre-charge switching device P42, the first pull-up switching device P21, the second pull-up switching device P22, the third pull-up switching device P23, the fourth pull-up switching device P24 and the first reinforcement switching device P35 are PMOS transistors. The first power source terminal Vdd1 and the fifth power source terminal Vdd5 are high, the second power source terminal Vdd2 is low, and the third power source terminal Vdd3 is high.
When the flash memory normally operates, the PRE-charge signal PRE is at a high level, the write-in signal WL is at a high level, the temporary storage signal W _ EN is at a low level, the enable signal R _ EN is at a low level, and the fourth power terminal Vdd4 is at a low level. The transistors P41, P42, N31, N32, N33, N34, and N36 are in an off state. The transistors N11, N12, P23, P24, N21, and N22 are turned on, the nonvolatile structure and the volatile structure are isolated from each other, and the first node Q and the second node QB are insensitive nodes. If an SEU occurs at the additional redundant nodes (S1-S4), the levels of the first node Q and the second node QB can still maintain the initial state. It is assumed that the first input terminal BL inputs a high level, corresponding to "1", and the second input terminal BLB inputs a low level, corresponding to "0". Nodes S1 and S3 are high, nodes S2 and S4 are low, P22 and N23 are turned off, P21 and N24 are turned on, and nodes S2 and S3 are sensitive nodes. When SEU occurs in S2, the level is pulled high, P21 is turned off, but other nodes are still in an initial state and are not affected, and transient current can be released through P24, N22 and N24, so that the turned S2 node can be quickly recovered, and the storage nodes Q and QB can be ensured to be written correctly.
When data is temporarily stored, that is, before entering the standby state, the data of the first node Q and the second node QB need to be written into the temporary storage module, so as to complete data backup. During data temporary storage, the PRE-charge signal PRE is at a high level, the write-in signal WL is at a low level, the temporary storage signal W _ EN is at a low level, the enable signal R _ EN is at a low level, and the fourth power supply terminal Vdd4 is at a high level. The transistors N11 and N12 become off-state, and N31, N32, N33, N34 become on-state. Due to the potential difference between nodes Q and QB, current flows at nodes Q, MTJ, MTJ2 and QB. If Q is high and QB is low, the current direction is Q to P and then to QB. The current directions flowing through the two MTJs can be ensured to be opposite, and the backup operation of 1 and 0 is realized. When SEU occurs at the node P, P is pulled to a low potential, the direction of current flowing through the MTJ2 is changed, and a storage error occurs in the storage state of the MTJ 2. For a memory cell with a reinforcing circuit, the transistor P35 is added, so that the sensitive node can be charged quickly, the storage state of the MTJ2 can be restored quickly, and a new sensitive node is not introduced by the added redundant structure.
After the data is temporarily stored, the power supply is turned off, and the equipment comprising the storage unit enters a standby mode, so that the data cannot be lost. After the device waits for a result, the device needs to enter a recovery mode to recover data.
When the device is powered back up, the PRE-charge signal PRE goes low to charge nodes Q and QB. Then, the enable signal R _ EN and the fourth power source terminal Vdd4 become high level, and N32, N33, and N36 are turned on. Since the memory states of MTJ1 and MTJ2 are different, the high resistance state and the low resistance state are presented, respectively, and the drain currents flowing through N32 and N33 are different. The QB node is first lowered to low, turning on P21, pulling the Q node high, completing data recovery.
The invention isolates the sensitive nodes by utilizing the pull-up network and the pull-down network, avoids the SEU transmission, can realize the quick recovery of the SEU, does not add redundant storage nodes and control signals, and has simple circuit structure. Moreover, aiming at the characteristic of cooperative writing of STT and SOT, soft errors are easy to occur in the MTJ during data backup, a reinforcing circuit comprising a first reinforcing switch element P35 is added in the temporary storage module, and the gate end and the drain end of the reinforcing circuit are connected, so that the radiation resistance of the nonvolatile memory unit can be effectively improved. In addition, when the data is recovered, the PRE-charging signal PRE is added, so that the data can be rapidly recovered, and no current path is arranged in the PRE-charging process, so that no extra power consumption is generated.
Those skilled in the art can understand that the triode in this embodiment can be an N-type triode or a P-type triode, and the high and low levels of various signals are matched with the type of the triode to realize the corresponding functions. The technical personnel in the field can know that the P-type triode needs to be matched with a low-level signal when being conducted, and the N-type triode needs to be matched with a high-level signal when being conducted, so that the N-type triode or the P-type triode is adopted, the level of a triode grid (control end) is set to realize the corresponding on-off function, and the data reading purpose of the invention is realized. The control end of the triode provided by the embodiment of the invention is a grid electrode, the first end can be a source electrode, and the second end is a drain electrode, or vice versa, the first end can be a drain electrode, and the second end is a source electrode.
In addition, the triode provided by the embodiment of the invention can be a field effect triode, wherein the triode can be an enhancement type field effect triode and can also be a depletion type field effect triode. The triode can adopt a low-temperature polysilicon TFT, can reduce the manufacturing cost and the product power consumption, has faster electron mobility, and can also adopt an oxide semiconductor TFT.
As a preferred implementation mode, the magnetic tunnel junction can be in a common shape such as a circle, a rectangle or a square, so as to reduce the cost and facilitate the continuous miniaturization of the size, and meanwhile, the magnetic tunnel junction is suitable for various memory structures such as a double-interface structure and a multi-interface structure. In other embodiments, an oval shape may be used, and the invention is not limited thereto.
Preferably, the spin orbit torque layer is rectangular, so that the area of the top surface of the spin orbit torque layer is larger than the area occupied by the magnetic tunnel junction arranged on the spin orbit torque layer, even though the magnetic tunnel junction can be arranged on the spin orbit torque layer, and the outer edge of the magnetic tunnel junction is positioned on the inner side of the outer edge of the spin orbit torque layer. Wherein, the spin orbit torque layer can be selected from heavy metal strip film or antiferromagnetic strip film.
It should be noted that, one or more magnetic tunnel junctions on the spin orbit torque layer may be provided, and preferably, a plurality of magnetic tunnel junctions may be provided on the same spin orbit torque layer, so that one-time data write operation to the plurality of magnetic tunnel junctions may be implemented, the number of control transistors inputting the spin orbit torque current I may be reduced, and thus, the integration level is improved and the power consumption of the circuit is reduced.
In a preferred embodiment, a top electrode may be provided on top of the magnetic tunnel junction, and a current input electrode and an output electrode may be provided on opposite sides of the spin orbit torque layer, respectively, for input of the sense currents (I1, I2) and the spin orbit torque current I. Among them, the material of the electrode is preferably tantalum Ta, aluminum Al, gold Au, or copper Cu.
Preferably, the material of the free layer and the fixed layer may be a ferromagnetic metal, and the material of the barrier layer may be an oxide. The magnetic tunnel junction has perpendicular magnetic anisotropy, which means that the magnetization directions of the free layer and the pinned layer forming the magnetic tunnel junction are in the perpendicular direction. The ferromagnetic metal can be a mixed metal material formed by at least one of cobalt iron CoFe, cobalt iron boron CoFeB or nickel iron NiFe, and the proportion of the mixed metal materials can be the same or different. The oxide can be one of magnesium oxide, mgO, aluminum oxide, al2O3 and the like, and is used for generating a tunneling magnetoresistance effect. In practical applications, the ferromagnetic metal and the oxide may be made of other feasible materials, and the invention is not limited thereto.
The free layer of the magnetic tunnel junction is fixedly contacted with the spin orbit moment layer, each layer of the magnetic tunnel junction and the spin orbit moment layer can be sequentially plated on the substrate from bottom to top by the traditional methods of ion beam epitaxy, atomic layer deposition or magnetron sputtering, and then one or more magnetic tunnel junctions are prepared and formed by the traditional nanometer device processing technologies of photoetching, etching and the like.
In a preferred embodiment, the spin orbit torque layer is a spin orbit torque layer made of a heavy metal thin film, an antiferromagnetic thin film, or other material. The heavy metal film or the antiferromagnetic film can be made in a rectangular shape, and the top area of the heavy metal film or the antiferromagnetic film is preferably larger than the bottom area of the outline formed by all the magnetic tunnel junctions, so that one or more magnetic tunnel junctions can be arranged, and the bottom shapes of the magnetic tunnel junctions are completely embedded in the top shapes of the heavy metal film or the antiferromagnetic film. Preferably, the spin-orbit torque layer is made of one of platinum Pt, tantalum Ta, tungsten W, or the like. In practical applications, the spin-orbit torque layer may be formed by using other feasible materials, which is not limited by the present invention.
In this embodiment, the first magnetic tunnel junction MTJ1 and/or the second magnetic tunnel junction MTJ2 includes a fixed layer on top, a free layer in contact with the spin orbit torque layer, and a barrier layer disposed between the fixed layer and the free layer, and the magnetic tunnel junction is a three-layer structure including only one free layer. In other embodiments, the free layer may be provided in plural, i.e., two or more free layers. The magnetic tunnel junction comprises a fixed layer at the top, a plurality of free layers and barrier layers arranged between every two adjacent layers, wherein the free layer at the bottommost layer is arranged in contact with the spin orbit torque layer. For example, in one particular example, when two free layers are included, the magnetic memory cell structure may include a spin-orbit torque layer, a second free layer, a barrier layer, a first free layer, a barrier layer, and a fixed layer sequentially disposed on the spin-orbit torque layer.
Based on the same principle, the embodiment also discloses a nonvolatile memory. The nonvolatile memory comprises a plurality of magnetic random access memory cells arranged in an array.
Memory, including permanent and non-permanent, removable and non-removable media, may implement the information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of memory applications include, but are not limited to, random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.
Since the principle of solving the problem of the nonvolatile memory is similar to that of the above memory, the implementation of the nonvolatile memory can refer to the implementation of the above memory, and is not described herein again.
Based on the same principle, the embodiment also discloses a computer device which comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor.
The processor and/or the memory include a non-volatile memory unit as described in the present embodiment.
The nonvolatile memory unit explained in the above embodiments may be specifically provided in a product device having a certain function. A typical implementation device is a computer device, which may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
In a typical example, the computer device specifically includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor and/or the memory includes the nonvolatile memory unit according to the embodiment.
Referring now to FIG. 2, shown is a schematic diagram of a computer device 600 suitable for use in implementing embodiments of the present application.
As shown in fig. 2, the computer apparatus 600 includes a Central Processing Unit (CPU) 601 that can perform various appropriate jobs and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage section 608 into a Random Access Memory (RAM)) 603. In the RAM603, various programs and data necessary for the operation of the system 600 are also stored. The CPU601, ROM602, and RAM603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
The following components are connected to the I/O interface 605: an input portion 606 including a keyboard, a mouse, and the like; an output section 607 including a Cathode Ray Tube (CRT), a liquid crystal feedback (LCD), and the like, and a speaker and the like; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. A driver 610 is also connected to the I/O interface 605 as needed. A removable medium 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 610 as necessary, so that a computer program read out therefrom is mounted as necessary on the storage section 608.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art to which the present application pertains. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (11)
1. A nonvolatile memory cell is characterized by comprising a data writing module, a first node, a second node, a pull-up network, a pull-down network and a temporary storage module;
the data writing module is respectively connected with the first node and the second node and is used for writing a first level and a second level into the first node and the second node respectively; the pull-up network and the pull-down network are used for maintaining the level of the first node and the second node;
the temporary storage module comprises a first magnetic storage unit, a second magnetic storage unit and a reinforcing circuit, wherein a current input end and a current output end of the first magnetic storage unit are respectively connected with the first node and the third node, a current input end and a current output end of the second magnetic storage unit are respectively connected with the third node and the second node, the resistance states of the first magnetic storage unit and the second magnetic storage unit respectively correspond to the first level and the second level based on the potential difference of the first node and the second node in response to a temporary storage signal, and the reinforcing circuit is used for keeping the level of the third node;
the reinforcement circuit is used for responding to an enabling signal and charging the third node to maintain the level of the third node when the third node generates single event upset.
2. The nonvolatile memory cell of claim 1 wherein the data write module comprises a first write switch element and a second write switch element;
a control terminal of the first write switch element is used for receiving a write signal, a first terminal of the first write switch element is connected with a first signal input terminal for providing a first level, and a second terminal of the first write switch element is connected with the first node;
a control terminal of the second write switch element is configured to receive the write signal, a first terminal of the second write switch element is connected to a second signal input terminal that provides a second level, and a second terminal of the second write switch element is connected to the second node;
the first write switch element turns on the first signal input terminal and the first node in response to the write signal, writing the first level to the first node; the second write switch element turns on the second signal input terminal and the second node in response to the write signal, and writes the second level to the second node.
3. The non-volatile memory cell of claim 1, wherein the pull-up network comprises a first pull-up switching element, a second pull-up switching element, a third pull-up switching element, a fourth pull-up switching element, a first redundant node, and a second redundant node;
the control end of the first pull-up switching element is connected with the second redundant node, the first end of the first pull-up switching element is connected with the first power supply end, and the second end of the first pull-up switching element is connected with the first redundant node;
a control end of the second pull-up switching element is connected with the first redundant node, a first end of the second pull-up switching element is connected with a first power supply end, and a second end of the second pull-up switching element is connected with the second redundant node;
a control end of the third pull-up switching element is connected with a second power end, a first end of the third pull-up switching element is connected with the first redundant node, and a second end of the third pull-up switching element is connected with the first node;
and the control end of the fourth pull-up switching element is connected with a second power supply end, the first end of the fourth pull-up switching element is connected with the second redundant node, and the second end of the fourth pull-up switching element is connected with the second node.
4. The nonvolatile memory cell of claim 1 wherein the pull-down network comprises a first pull-down switching element, a second pull-down switching element, a third pull-down switching element, a fourth pull-down switching element, a third redundant node, and a fourth redundant node;
the control end of the first pull-down switching element is connected with a third power supply end, the first end of the first pull-down switching element is connected with the first node, and the second end of the first pull-down switching element is connected with the third redundant node;
a control end of the second pull-down switching element is connected with the third power supply end, a first end of the second pull-down switching element is connected with the second node, and a second end of the second pull-down switching element is connected with the fourth redundant node;
the control end of the third pull-down switch element is connected with the fourth redundant node, the first end of the third pull-down switch element is connected with the third redundant node, and the second end of the third pull-down switch element is connected with the ground end;
and the control end of the fourth pull-down switch element is connected with the third redundant node, the first end of the fourth pull-down switch element is connected with the fourth redundant node, and the second end of the fourth pull-down switch element is connected with the grounding end.
5. The non-volatile memory cell of claim 1, wherein the temporary storage module further comprises a temporary storage control circuit for turning on the first node and a current input of the first magnetic memory cell in response to the temporary storage signal, and turning on the second node and a current output of the second magnetic memory cell in response to the temporary storage signal.
6. The nonvolatile memory cell of claim 5 wherein the first magnetic memory cell comprises a first spin torque orbit layer and a first magnetic tunnel junction disposed on the first spin torque orbit layer; the second magnetic storage unit includes a second spin orbit torque layer and a second magnetic tunnel junction disposed on the second spin orbit torque layer.
7. The non-volatile memory cell of claim 6 wherein the temporary storage control circuit comprises a first temporary storage switching element, a second temporary storage switching element, a third temporary storage switching element and a fourth temporary storage switching element;
the control end of the first temporary storage switch element is used for receiving the temporary storage signal, the first end of the first temporary storage switch element is connected with the first node, and the second end of the first temporary storage switch element is connected with the current input end of the first magnetic storage unit;
a control end of the second temporary storage switching element is connected with a fourth power supply end, a first end of the second temporary storage switching element is connected with the first node, and a second end of the second temporary storage switching element is connected with the top end of the first magnetic tunnel junction;
a control end of the third temporary storage switching element is connected with the fourth power supply end, a first end of the third temporary storage switching element is connected with the second node, and a second end of the third temporary storage switching element is connected with the top end of the second magnetic tunnel junction;
and the control end of the fourth temporary storage switching element is used for receiving the temporary storage signal, the first end of the fourth temporary storage switching element is connected with the second node, and the second end of the fourth temporary storage switching element is connected with the current output end of the second magnetic tunnel junction.
8. The nonvolatile memory cell of claim 6 wherein the reinforcing circuit includes a first reinforcing switching element and a second reinforcing switching element;
the first end of the first reinforced switch element is connected with a fifth power supply end, and the control end is respectively connected with the second end and the third node;
the control end of the second reinforced switch element is used for receiving an enabling signal, the first end of the second reinforced switch element is connected with the third node, and the second end of the second reinforced switch element is connected with the grounding end.
9. The non-volatile memory cell of claim 1, wherein the temporary storage module further comprises a precharge circuit for writing a high level to the first node and the second node in response to a precharge signal when the data is restored, the first node becoming a first level and the second node becoming a second level under the influence of the first magnetic memory cell and the second magnetic memory cell in different resistance states.
10. A non-volatile memory comprising a plurality of non-volatile memory cells according to any of claims 1 to 9 arranged in an array.
11. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor,
the processor and/or the memory comprise a non-volatile memory unit as claimed in any one of claims 1-9.
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