CN112948166B

CN112948166B - Data processing method and related product

Info

Publication number: CN112948166B
Application number: CN202110296212.9A
Authority: CN
Inventors: 姜一扬; 张黄鹏
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-10-16
Filing date: 2019-10-16
Publication date: 2021-12-21
Anticipated expiration: 2039-10-16
Also published as: CN110908826A; CN112948166A; CN110908826B

Abstract

The embodiment of the application discloses a data processing method and a related product, which comprises the steps of acquiring original data and storing the original data into a first storage area in a memory; if the storage period of the original data exceeds a first preset time length, at any intermediate time in the storage period of the original data, reading intermediate data stored in the first storage area at the intermediate time, storing the intermediate data in a second storage area in the memory, at the reading time when the original data needs to be read, reading second data stored in the second storage area at the reading time, reading first data stored in the first storage area at the reading time, and correcting errors of the first data in the first storage area according to the second data to obtain corrected original data.

Description

Data processing method and related product

Technical Field

The present application relates to the field of storage technologies, and in particular, to a data processing method and a related product.

Background

In some memory storage channels, the a priori errors are random, and in the prior art, random errors in the codewords are corrected by an error correction code. Generally, to meet the requirement of stronger error correction capability, a powerful error correction code is applied. When data with a longer storage period and data with a shorter storage period exist at the same time, the data with the shorter storage period does not need high checking capability, because a stronger error correcting code is used for error correction, the hardware utilization rate of the error correcting code module is higher or the coding rate is lower, if the error correcting code module with the low checking capability is used, the hardware utilization rate can be reduced, but when the data error in the data with the longer storage period exceeds the error correcting capacity of the error correcting code module, the correct original data cannot be read because all data errors cannot be corrected. Therefore, how to maintain the strong error correction capability of the error correction code module needs to be considered on the premise of reducing the hardware utilization rate of the error correction code module.

Disclosure of Invention

The embodiment of the application provides a data processing method and a related product, which can reduce the hardware utilization rate of an error correction code module and keep stronger error correction capability by storing intermediate data at an intermediate moment in advance and correcting errors according to the intermediate data at a reading moment.

In a first aspect, an embodiment of the present application provides a data processing method, where the method includes:

acquiring original data and storing the original data in a first storage area in a memory;

if the storage period of the original data exceeds a first preset time length, at any intermediate time in the storage period of the original data, reading intermediate data stored in the first storage area at the intermediate time, and storing the intermediate data into a second storage area in the memory, wherein the intermediate data is an expression form of the original data in the first storage area at any intermediate time; and

reading second data stored in the second storage area at the reading time and reading first data stored in the first storage area at the reading time when the original data needs to be read; and

and correcting the error of the first data in the first storage area according to the second data to obtain corrected original data.

In a second aspect, an embodiment of the present application provides a data processing apparatus, where the apparatus includes:

an acquisition unit configured to acquire original data and store the original data in a first storage area in a memory;

the obtaining unit is further configured to, if a storage period of the original data exceeds a first preset duration, read intermediate data stored in the first storage area at any intermediate time in the storage period of the original data, and store the intermediate data in a second storage area in the memory, where the intermediate data is an expression form of the original data in the first storage area at any intermediate time; and

a reading unit, configured to read, at a reading time when the original data needs to be read, second data stored in the second storage area at the reading time, and read first data stored in the first storage area at the reading time; and

and the error correction unit is used for correcting the error of the first data in the first storage area according to the second data to obtain corrected original data.

In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor, and the program includes instructions for executing the steps in the first aspect of the embodiment of the present application.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program for electronic data exchange, where the computer program enables a computer to perform some or all of the steps described in the first aspect of the embodiment of the present application.

In a fifth aspect, embodiments of the present application provide a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps as described in the first aspect of the embodiments of the present application. The computer program product may be a software installation package.

The embodiment of the application has the following beneficial effects:

it can be seen that the data processing method described in the embodiment of the present application obtains the original data and stores the original data in the first storage area in the memory; if the storage period of the original data exceeds a first preset time length, at any intermediate time in the storage period of the original data, reading intermediate data stored in the first storage area at the intermediate time, storing the intermediate data in a second storage area in the memory, at the reading time when the original data needs to be read, reading second data stored in the second storage area at the reading time, reading first data stored in the first storage area at the reading time, and correcting errors of the first data in the first storage area according to the second data to obtain corrected original data.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1A is a schematic diagram illustrating an example of error correction of data by an error correction code provided in an embodiment of the present application;

fig. 1B is a schematic flowchart of a data processing method according to an embodiment of the present application;

FIG. 1C is a schematic diagram of the threshold voltage shift of a CTF provided in the embodiments of the present application;

FIG. 1D is a schematic diagram of another CTF threshold voltage shift provided in the embodiments of the present application;

fig. 1E is a schematic diagram illustrating a first preset voltage value list according to an embodiment of the present disclosure;

FIG. 1F is a schematic diagram illustrating changes over time of data in a first storage area and a second storage area according to an embodiment of the present application;

FIG. 1G is a graph illustrating a distribution curve between the number of memory cells and a reference voltage according to an embodiment of the present disclosure;

FIG. 2 is a schematic flow chart diagram of another data processing method provided in the embodiments of the present application;

fig. 3A is a schematic flowchart of encoding according to an embodiment of the present application;

fig. 3B is a schematic flowchart of decoding according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

fig. 5A is a block diagram of functional units of a data processing apparatus according to an embodiment of the present application;

fig. 5B is a modified structure of the data processing apparatus shown in fig. 5A according to an embodiment of the present application.

Detailed Description

The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The following describes embodiments of the present application in detail.

Referring to fig. 1A, fig. 1A is a schematic diagram illustrating an example of data error correction performed by an error correction code according to the present application, where D1, D2, and D3.

Referring to fig. 1B, fig. 1B is a schematic flowchart of a data processing method according to an embodiment of the present application, where the data processing method includes:

101. raw data is acquired and stored to a first storage area in a memory.

The original data is data to be stored, and the manner of acquiring the original data may be that the electronic device receives data transmitted by an external device, or the electronic device acquires data generated by itself.

Alternatively, the memory may comprise a flash memory.

Optionally, in step 101, storing the original data in the first storage area of the memory may include the following steps:

encoding the original data as a first information bit to obtain a first check bit; and

and programming the first information bit and the first check bit to a first storage area in the memory to obtain a first code word related to the original data.

In the embodiment of the present application, the original data is stored in the first storage area of the memory, and the original data may be encoded as the first information bit D1, so that the encoded first parity bit P1 may be obtained. The first information bit D1 and the first check bit P1 may then be programmed into a first storage area in the memory, resulting in a first codeword associated with the original data, specifically, programming may be performed in the memory channel by injecting charge into the memory channel using a charge trap memory (CTF) structure, wherein the first storage area includes a plurality of storage units, and for each storage unit in the first storage area, corresponding charges can be injected according to the code required to be stored in the memory cell, so that the threshold voltage of the memory cell reaches a preset threshold voltage corresponding to the data required to be stored, the threshold voltage refers to an attribute voltage for characterizing data stored in a corresponding memory cell, for example, if the data to be stored in the memory cell is 0, the charge can be injected into the memory cell to make the threshold voltage of the memory cell reach the preset threshold voltage of 0.35V; if the data to be stored in the memory cell is 1, charge can be injected into the memory cell to make the threshold voltage of the memory cell reach the predetermined threshold voltage of 0.8V. Referring to fig. 1C, fig. 1C is a schematic diagram of a threshold voltage shift of a CTF provided in an embodiment of the present application, as shown in fig. 1C, a charge drift may occur during a process of injecting charges into a memory cell, so that a threshold voltage of a corresponding memory cell shifts, for example, the threshold voltage of the memory cell should reach a preset threshold voltage of 0.35V, and the threshold voltage of the memory cell may actually be 0.37V or 0.31V due to the charge drift, so that the threshold voltages of all memory cells coded as 1 are not 0.35V, and during a programming stage, the number of memory cells at the threshold voltage is the largest, and the number of memory cells with more threshold voltage shifts is the smaller.

102. If the storage period of the original data exceeds a first preset time length, at any intermediate time in the storage period of the original data, reading intermediate data stored in the first storage area at the intermediate time, and storing the intermediate data in a second storage area in the memory, wherein the intermediate data is an expression form of the original data in the first storage area at any intermediate time.

The storage period refers to a time length of original data to be stored, the storage period may be 4 years, for example, and the first preset time length may be 3 years, for example, which is not limited herein.

In the embodiment of the present application, considering that in the process of storing original data, charges corresponding to each memory cell may leak, and as the storage time increases, the more serious the leakage is, the higher the threshold voltage is, the more serious the leakage is, so that the threshold voltage of each memory cell may decrease, as shown in fig. 1D, fig. 1D is a schematic diagram of a threshold voltage offset of another CTF provided in the embodiment of the present application, where the threshold voltage of each memory cell in the first storage region decreases, which may cause a decoding error in a stage of reading the original data. Generally, if the storage period of the original data is short, the amount of errors in the original data that cause data errors in the storage period is small, and the error correction capacity of the error correction code module can be realized such that the data errors can be corrected by only one error correction, and the corrected original data can be obtained, for example, the error correction capacity of the error correction code module is 72 bits/1150 bytes, and the error correction can be performed in the presence of 72-bit data errors. However, when the storage period of the original data is long, a data error of more than 72 bits, for example, a 144-bit data error may occur during the storage, thereby making it difficult to completely correct the generated data error. Therefore, in the embodiment of the application, at any intermediate time in the original data storage period, the intermediate data stored in the first storage area at any intermediate time can be read, and any intermediate data can be stored in the second storage area in the memory, wherein the original data is stored in the first storage area, and due to the threshold voltage of the storage unit being lowered, data errors occur in part of the storage units, so that the expression form of the corrected original data in the first storage area at any intermediate time, that is, the intermediate data, can be obtained.

Optionally, in the step 102, reading the intermediate data stored in the first storage area at the intermediate time may include the following steps:

21. at any intermediate moment, acquiring a first reading voltage value; and

22. and reading the first storage area according to the first reading voltage value to obtain the intermediate data.

The first read voltage value is used for reading data of each memory cell in the first storage area, and the data stored in the memory cells can be determined according to the magnitude relation between the first read voltage value and the threshold voltage of the memory cells, for example, the first read voltage value is 3V, the threshold voltage of the first memory cell is 1.7V, and the threshold voltage of the second memory cell is 5V, which indicates that the data of the first memory cell may be different from the data of the second memory cell.

Optionally, the obtaining the first read voltage value in step 21 may include the following steps:

2101. at any intermediate moment, acquiring the stored time length and the writing and erasing times of the original data, wherein the stored time length is less than or equal to the storage period; and

2102. and inquiring a first preset voltage value list according to the stored time length and the programming and erasing times to obtain the first reading voltage value corresponding to the stored time length and the programming and erasing times.

The method comprises the steps of obtaining stored time length and programming and erasing times of original data, inquiring a first preset voltage value list created in advance according to the stored time length and the programming and erasing times, obtaining a first reading voltage value corresponding to the stored time length and the programming and erasing times, and accordingly reading data in a first storage area according to the first reading voltage value.

Optionally, the electronic device may create the first preset voltage value list in advance, and create the first preset voltage value list, and the method may include the following steps:

2103. the method comprises the steps that reading voltage values corresponding to each group of reference storage duration and writing and erasing times in a plurality of groups of reference storage durations and writing and erasing times are obtained in advance according to preset sample data to obtain a plurality of reading voltage values;

2104. and creating the first preset voltage value list according to the multiple groups of reference storage time lengths, the programming and erasing times and the multiple read voltage values.

The method includes the steps of training sample data in advance, specifically, obtaining a read voltage value of each of a plurality of groups of reference storage time lengths and writing and erasing times in the storage process of the sample data, and then creating a first preset voltage value list according to the plurality of groups of reference storage time lengths, the writing and erasing times and the plurality of read voltage values. Referring to fig. 1E, fig. 1E is a schematic diagram illustrating a first preset voltage value list according to an embodiment of the present disclosure, wherein each group of the storage duration and the program/erase count corresponds to a read voltage value.

Optionally, in step 2103, obtaining a plurality of read voltage values corresponding to each of the plurality of groups of reference storage durations and program/erase times to obtain a plurality of read voltage values, may include the following steps:

writing and erasing times i are recorded aiming at the sample data under a reference storage duration i, wherein the reference storage duration is any reference storage duration, and the following operations are executed:

2111. when the sample data is stored for a reference storage time length i, determining voltage distribution of a plurality of reference threshold voltages of a plurality of storage units for storing the sample data, and determining a first state or a second state of each storage unit in the plurality of storage units;

2112. determining a first voltage range in which a plurality of first reference threshold voltages of a plurality of first memory cells in the first state are located according to the voltage distribution; and determining a second voltage range in which a plurality of second reference threshold voltages of a plurality of second memory cells in the second state are located;

2113. determining an overlapping voltage range of the first and second voltage ranges;

2114. arranging a plurality of first reference threshold voltages which are larger than the left end point of the overlapping voltage range in the plurality of first reference threshold voltages in a descending order to obtain a first sequence, and determining that the nth first reference threshold voltage in the first sequence is a read voltage value corresponding to the reference storage time length i and the programming and erasing times i, wherein n is a preset value; or,

2115. and arranging the second reference threshold voltages smaller than the right end point of the overlapping voltage range in the second reference threshold voltages in a descending order to obtain a second sequence, and determining the nth second reference threshold voltage in the second sequence as a read voltage value corresponding to the reference storage time length i and the programming and erasing times i.

For example, in an initial state where sample data is just stored, the reference threshold voltages of the plurality of memory cells in the first state are distributed in a third voltage range, for example, 0.3V to 0.5V, and the reference threshold voltages of the memory cells in the second state are distributed in a fourth voltage range, for example, 0.5V to 0.8V; after the reference storage time length i, the reference threshold voltage of each memory cell will shift, the reference threshold voltages of all memory cells will decrease, the reference threshold voltage distribution range of the memory cells in the first state is the first voltage range, such as 0.1V-0.4V, and the reference threshold voltage distribution range of the memory cells in the second state is the second voltage range, such as 0.3V-0.7V; and overlapping voltage ranges exist in the third voltage range and the fourth voltage range, the overlapping voltage range is 0.3V-0.4V, at this time, the multiple first reference threshold voltages which are larger than the left end point of the overlapping voltage range in the multiple first reference threshold voltages can be arranged according to a sequence from small to large to obtain a first sequence, and the nth first reference threshold voltage in the first sequence is determined to be a read voltage value corresponding to the reference storage time length i and the programming and erasing times i. For example, a plurality of first reference threshold voltages larger than 0.3V in the plurality of first reference threshold voltages are arranged in a descending order to obtain a first sequence, and a 72 th first reference threshold voltage in the first sequence is determined to be a read voltage value corresponding to a reference storage duration i and a programming/erasing frequency i. Or, arranging a plurality of second reference threshold voltages smaller than 0.4V in the plurality of second reference threshold voltages in a descending order to obtain a second sequence, and determining a 72 th second reference threshold voltage in the second sequence as a read voltage value corresponding to the reference storage time length i and the programming and erasing times i.

Optionally, in step 102, the step of storing the intermediate data in the second storage area of the memory may include the following steps:

encoding the intermediate data as a second information bit to obtain a second check bit; and

and programming the second check bit to a second storage area in the memory to obtain a second code word related to the intermediate data.

In the embodiment of the present application, the intermediate data is stored in the first storage area of the memory, and the intermediate data may be encoded as the second information bit D2, so that the encoded second parity bit P2 may be obtained. A second parity bit P2 may then be programmed into a second storage area in the memory, resulting in a second codeword associated with the intermediate data.

The physical addresses of the first storage area and the second storage area are different, so that in order to avoid interference on original data caused by charge drift in the process of encoding the intermediate data, the intermediate data is stored in a second storage area different from the physical address of the first storage area, and data errors caused by interference between the intermediate data and the original data in the storage process can be prevented.

103. And reading the second data stored in the second storage area at the reading time and reading the first data stored in the first storage area at the reading time when the original data needs to be read.

The first data is the expression form of the original data in the first storage area at the reading moment, and the second data is the expression form of the intermediate data in the second storage area at the reading moment.

In the embodiment of the present application, please refer to fig. 1F, and fig. 1F is a schematic diagram illustrating a change of data in a first storage area and a second storage area over time according to the embodiment of the present application. At the initial moment, storing original data into a first storage area; at any intermediate moment, the expression form of the original data in the first storage area at any intermediate moment is intermediate data, and the intermediate data is stored in the second storage area; the stored data of the first memory area and the second memory area can be read at the reading time when the original data needs to be read, wherein at the reading time, the original data is represented in the first memory area at the reading time as first data, and the intermediate data is represented in the second memory area at the reading time as second data.

Optionally, in step 103, reading the second data stored in the second storage area at the reading time may include the following steps:

31. acquiring a judgment voltage value at the reading moment; and

32. and reading a second check bit in the second storage area according to the judgment voltage value to obtain the second data.

The decision voltage value is used to read data of each memory cell in the second storage area, and specifically, a read operation may be performed on the second check bit P2 in the second storage area according to the decision voltage value, so as to obtain the second data P2'.

Optionally, in the step 31, acquiring the decision voltage value may include the following steps:

3101 a second preset voltage value list is queried according to the stored time length and the program erase times to obtain the decision voltage value corresponding to the stored time length and the program erase times.

Optionally, the electronic device may create a second preset voltage value list in advance, and create the second preset voltage value list, and the method may include the following steps:

3102. obtaining a plurality of groups of reference storage time lengths and writing and erasing times of the sample data in advance, wherein the reference storage time lengths and the writing and erasing times of each group correspond to judgment voltage values to obtain a plurality of judgment voltage values;

3103. and creating the second preset voltage value list according to the multiple groups of reference storage time lengths, the programming and erasing times and the multiple judgment voltage values.

Optionally, in step 3102, obtaining the decision voltage values corresponding to each of the multiple sets of reference storage durations and program/erase times to obtain multiple decision voltage values may include the following steps:

writing and erasing times i are recorded aiming at the sample data under a reference storage duration i, wherein the reference storage duration i is any reference storage duration, and the following operations are executed:

3111. when the sample data is stored for a reference storage time length i, determining the number distribution of the storage units of which the reference voltage thresholds of the plurality of first storage units in the first state are under different voltage values to obtain a first distribution curve, and determining the number distribution of the storage units of which the reference voltage thresholds of the plurality of second storage units in the second state are under different voltage values to obtain a second distribution curve;

3112 determining a reference voltage threshold corresponding to an intersection of the first distribution curve and the second distribution curve as a read voltage value corresponding to the reference storage time length i and the program/erase times i.

Referring to fig. 1G, fig. 1G is a schematic diagram illustrating a distribution curve between the number of memory cells and a reference value voltage according to an embodiment of the present disclosure. The number of memory cells in the same reference threshold voltage may be counted in a plurality of memory cells of the sample data, wherein a first state or a second state of each memory cell may be determined, and then a first distribution curve may be generated according to a plurality of first reference threshold voltages of the plurality of first memory cells in the first state, wherein in the first distribution curve, a voltage value of each reference threshold voltage corresponds to a number of memory cells, indicating that the reference threshold voltages of the plurality of memory cells are all the voltage values. A second distribution curve may also be generated based on a plurality of second reference threshold voltages of a plurality of second memory cells in a second state. And then determining a reference voltage threshold corresponding to the intersection point of the first distribution curve and the second distribution curve as a decision voltage value corresponding to the reference storage time length i and the programming and erasing times i.

Optionally, in the step 32, performing a read operation on the second storage area according to the decision voltage value to obtain the second data may include the following steps:

3201. determining a physical address of the second parity bit according to a logical address of the second parity bit in the second storage area;

3202. and reading the physical address of the second check bit according to the judgment voltage value to obtain the second data.

When data reading is performed, the physical address of the second parity bit P2 can be determined according to the logical address of the pre-recorded and saved second parity bit P2, and then reading is performed according to the physical address of the second parity bit P2, so that the second data P2' is obtained.

Optionally, in step 103, reading the first data stored in the first storage area at the reading time may include the following steps:

33. acquiring a second read voltage value from the preset voltage list at the reading moment; and

34. and reading the first information bit and the first check bit in the first storage area according to the second reading voltage value to obtain the first data and check bit data.

The second read voltage value is used for reading data of each memory cell in the first storage area, and specifically, the first information bit D1 and the first check bit P1 in the first storage area can be read according to the second read voltage value, so as to obtain the first data D2 'and the check bit data P1'.

Optionally, in step 34, the physical address of the second parity P2 further includes the physical address of the first information bit and the first parity, and the reading of the first information bit and the first parity in the first storage area according to the second read voltage value to obtain the first data and the parity data may include the following steps:

3401. and reading the physical addresses of the first information bit and the first check bit in the first storage area according to the second reading voltage value to obtain the first data and the check bit data.

Since the physical address of the first storage area is different from that of the second storage area, and the physical address of the second parity bit P2 is also different from that of the first information bit D1 and the first parity bit P1, the physical addresses of the first information bit D1 and the first parity bit P1 can be stored in the physical address of the second parity bit P2, so that after the physical address of the second parity bit P2 is obtained, the physical addresses of the first information bit D1 and the first parity bit P1 can be obtained from the physical address of the second parity bit P2, and the physical addresses of the first information bit D1 and the first parity bit P1 in the first storage area are read according to the second read voltage value, thereby obtaining the first data D2 'and the parity bit data P1'.

104. And correcting the error of the first data in the first storage area according to the second data to obtain corrected original data.

In the embodiment of the application, the first data and the second data are both data with errors generated in the storage process of the original data, and at the reading moment, the first data in the first storage area can be corrected through the second data in the second storage area, so that all data errors generated by the first data can be corrected, and correct original data can be obtained.

Optionally, in the step 104, performing error correction on the first data in the first storage area according to the second data to obtain corrected original data, may include the following steps:

41. decoding the first data and the second data, and if the decoding is successful, obtaining the intermediate data;

42. and decoding the intermediate data and the check bit data read from the first storage area to obtain corrected original data.

The first data D2 'and the second data P2' can be decoded, and if the decoding is successful, the intermediate data D2 is obtained; then, the intermediate data D2 and the check bit data P1' read from the first storage area are decoded to obtain a first information bit D1, i.e. the corrected original data. Accordingly, the first data can be subjected to error correction twice by the above-described twice decoding, wherein the first error correction can obtain intermediate data, and then the second error correction is performed based on the intermediate data to obtain corrected original data, and for example, if there are 144 bits of data errors occurring from the original data to the first data at the reading time, 72 bits of the data errors can be corrected by the first decoding, and the remaining 72 bits can be corrected by the second decoding to obtain correct original data. Thus, the original data with longer storage period can be corrected by the error correction code module with the error correction capacity of 72 bits/1150 bytes, thereby not only reducing the hardware utilization rate of the error correction code module, but also improving the error correction capability.

Optionally, after the step 41, the following steps may be further included:

and if the decoding of the first data and the second data fails, returning to the step 34, and obtaining a second read voltage value from the preset voltage list.

If the decoding of the first data D2 'and the second data P2' fails in step 41, a new second read voltage value in the preset voltage list may be obtained again, and then the first information bit D1 and the first parity bit P1 in the first storage area are read according to the new second read voltage value to obtain new first data D2 'and new parity bit data P1', and then the new first data is corrected according to the second data.

Referring to fig. 2, fig. 2 is a schematic flow chart of a data processing method according to an embodiment of the present application, consistent with the embodiment shown in fig. 1B, where the data processing method includes:

201. and acquiring original data and coding the original data as a first information bit to obtain a first check bit.

202. And programming the first information bit and the first check bit to a first storage area in the memory to obtain a first code word related to the original data.

203. And if the storage period of the original data exceeds a first preset time length, acquiring a first reading voltage value at any intermediate time in the storage period of the original data.

204. And reading the first storage area according to the first reading voltage value to obtain intermediate data.

Wherein the intermediate data is a representation of the original data in the first storage area at the any intermediate time.

205. And coding the intermediate data as a second information bit to obtain a second check bit.

206. And programming the second check bit to a second storage area in the memory to obtain a second code word related to the intermediate data.

207. And acquiring a judgment voltage value at the reading moment when the original data needs to be read.

208. And reading a second check bit in the second storage area according to the judgment voltage value to obtain the second data.

And the second data is the expression form of the intermediate data in the second storage area at the reading moment.

209. And acquiring a second read voltage value from the preset voltage list at the reading moment.

210. And reading the first information bit and the first check bit in the first storage area according to the second reading voltage value to obtain the first data and check bit data.

And the first data is the expression form of the original data in the first storage area at the reading moment.

211. And decoding the first data and the second data, and if the decoding is successful, obtaining the intermediate data.

212. And decoding the intermediate data and the check bit data read from the first storage area to obtain corrected original data.

For the detailed description of the steps 201 to 212, reference may be made to corresponding steps of the data processing method described in the foregoing fig. 1B, and details are not repeated here.

It can be seen that, in the data processing method described in this embodiment of the present application, the original data is obtained and encoded as the first information bit to obtain the first check bit, the first information bit and the first check bit are programmed into the first storage area in the memory to obtain the first codeword related to the original data, if the storage period of the original data exceeds the first preset time duration, the first read voltage value is obtained at any intermediate time in the storage period of the original data, the first storage area is read according to the first read voltage value to obtain the intermediate data, the intermediate data is encoded as the second information bit to obtain the second check bit, the second check bit is programmed into the second storage area in the memory to obtain the second codeword related to the intermediate data, the decision voltage value is obtained at the reading time when the original data needs to be read, reading a second check bit in the second storage area according to the decision voltage value to obtain second data, acquiring a second read voltage value from the preset voltage list at the reading moment, reading a first information bit and a first check bit in a first storage area according to the second read voltage value to obtain first data and check bit data, wherein the first data is an expression form of original data in the first storage area at the reading moment, decoding the first data and the second data to obtain intermediate data if the decoding is successful, decoding the intermediate data and the check bit data read from the first storage area to obtain corrected original data, in this way, by storing the intermediate data at any intermediate time in advance, and performing error correction based on the intermediate data at the read time, under the condition of longer storage period of the original data, the stronger error correction capability of the error correction code module can be maintained.

Referring to fig. 3A-3B, fig. 3A is a schematic flowchart of a process of performing encoding according to an embodiment of the present application, and fig. 3B is a schematic flowchart of a process of performing decoding according to an embodiment of the present application, where as shown in fig. 3A, in the data processing method, the method of performing encoding includes:

acquiring original data and coding the original data as a first information bit D1 to obtain a first check bit P1; programming the first information bit D1 and the first check bit P1 into a first storage area in the memory results in a first codeword associated with the original data.

If the storage period of the original data exceeds a first preset time length, acquiring a first reading voltage value at any intermediate time in the storage period of the original data; reading the first storage area according to the first reading voltage value to obtain intermediate data; encoding the intermediate data as a second information bit D2 to obtain a second check bit P2; and programming the second check bit P2 to a second storage area in the memory to obtain a second code word related to the intermediate data D2.

As shown in fig. 3B, in the data processing method, the encoding method includes:

acquiring a judgment voltage value at the reading time when the original data needs to be read; reading a second check bit P2 in the second storage area according to the decision voltage value to obtain second data P2'; acquiring a second read voltage value from the preset voltage list at the reading moment; reading the first information bit D1 and the first check bit P1 in the first storage area according to the second reading voltage value to obtain the first data D2 'and check bit data P1'; and decoding the first data D2 'and the second data P2', and if the decoding is successful, obtaining the intermediate data D2.

And decoding the intermediate data D2 and the check bit data P1' read from the first storage area to obtain corrected original data D1.

If the decoding of the first data D2 'and the second data P2' fails, the step of obtaining a second read voltage value from the preset voltage list is returned to.

For the detailed description of the above steps, reference may be made to corresponding steps of the data processing method described in the above fig. 1B, and details are not repeated here.

It can be seen that, in the data processing method described in this embodiment of the present application, the original data is obtained and encoded as the first information bit to obtain the first check bit, the first information bit and the first check bit are programmed into the first storage area in the memory to obtain the first codeword related to the original data, if the storage period of the original data exceeds the first preset time duration, the first read voltage value is obtained at any intermediate time in the storage period of the original data, the first storage area is read according to the first read voltage value to obtain the intermediate data, the intermediate data is encoded as the second information bit to obtain the second check bit, the second check bit is programmed into the second storage area in the memory to obtain the second codeword related to the intermediate data, the decision voltage value is obtained at the reading time when the original data needs to be read, reading a second check bit in a second storage area according to the judgment voltage value to obtain second data, obtaining a second read voltage value from a preset voltage list at the reading moment, reading a first information bit and a first check bit in a first storage area according to the second read voltage value to obtain first data and check bit data, wherein the first data is the expression form of original data in the first storage area at the reading moment, decoding the first data and the second data, if the decoding fails, returning to the step of obtaining the second read voltage value from the preset voltage list, if the decoding succeeds, obtaining intermediate data, decoding the intermediate data and the check bit read from the first storage area to obtain corrected original data, and thus, the corrected original data can be obtained by storing the intermediate data at any intermediate moment in advance and correcting errors according to the intermediate data at the reading moment, under the condition of longer storage period of the original data, the stronger error correction capability of the error correction code module can be maintained.

Referring to fig. 4 in keeping with the above embodiments, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and as shown in the drawing, the electronic device 400 includes a processor 410, a memory 420, a communication interface 430, and one or more programs 421, where the one or more programs 421 are stored in the memory and configured to be executed by the processor, and in an embodiment of the present application, the programs include instructions for performing the following steps:

In one possible example, in terms of the first storage area storing the raw data in the memory, the program 421 includes instructions for performing the following steps:

In one possible example, in terms of said reading of intermediate data stored in said first memory area at said intermediate time, the above-mentioned program 421 includes instructions for:

at any intermediate moment, acquiring a first reading voltage value; and

and reading the first storage area according to the first reading voltage value to obtain the intermediate data.

In one possible example, in the obtaining the first read voltage value, the program includes instructions for:

at any intermediate moment, acquiring the stored time length and the writing and erasing times of the original data, wherein the stored time length is less than or equal to the storage period; and

and inquiring a first preset voltage value list according to the stored time length and the programming and erasing times to obtain the first reading voltage value corresponding to the stored time length and the programming and erasing times.

In one possible example, the program further includes instructions for performing the steps of:

the method comprises the steps that reading voltage values corresponding to each group of reference storage duration and writing and erasing times in a plurality of groups of reference storage durations and writing and erasing times are obtained in advance according to preset sample data to obtain a plurality of reading voltage values;

and creating the first preset voltage value list according to the multiple groups of reference storage time lengths, the programming and erasing times and the multiple read voltage values.

In one possible example, in obtaining the plurality of read voltage values by obtaining the read voltage values corresponding to each of the plurality of sets of reference storage durations and program erase times, the program includes instructions for performing the following steps:

when the sample data is stored for a reference storage time length i, determining voltage distribution of a plurality of reference threshold voltages of a plurality of storage units for storing the sample data, and determining a first state or a second state of each storage unit in the plurality of storage units;

determining a first voltage range in which a plurality of first reference threshold voltages of a plurality of first memory cells in the first state are located according to the voltage distribution; and determining a second voltage range in which a plurality of second reference threshold voltages of a plurality of second memory cells in the second state are located;

determining an overlapping voltage range of the first and second voltage ranges;

arranging a plurality of first reference threshold voltages which are larger than the left end point of the overlapping voltage range in the plurality of first reference threshold voltages in a descending order to obtain a first sequence, and determining that the nth first reference threshold voltage in the first sequence is a read voltage value corresponding to the reference storage time length i and the programming and erasing times i, wherein n is a preset value; or,

and arranging the second reference threshold voltages smaller than the right end point of the overlapping voltage range in the second reference threshold voltages in a descending order to obtain a second sequence, and determining the nth second reference threshold voltage in the second sequence as a read voltage value corresponding to the reference storage time length i and the programming and erasing times i.

In one possible example, in said second storage area for storing said intermediate data in said memory, the above program comprises instructions for:

In one possible example, in respect of the reading of the second data stored by the second storage area at the time of the reading, the above-mentioned program comprises instructions for:

acquiring a judgment voltage value at the reading moment; and

and reading a second check bit in the second storage area according to the judgment voltage value to obtain the second data.

In one possible example, in the obtaining the decision voltage value, the program includes instructions for performing the steps of:

and inquiring a second preset voltage value list according to the stored time length and the programming and erasing times of the original data to obtain the judgment voltage value corresponding to the stored time length and the programming and erasing times.

acquiring a plurality of groups of reference storage time lengths and writing and erasing times of preset sample data in advance, wherein the judgment voltage values corresponding to each group of reference storage time lengths and writing and erasing times are obtained to obtain a plurality of judgment voltage values;

and creating the second preset voltage value list according to the multiple groups of reference storage time lengths, the programming and erasing times and the multiple judgment voltage values.

In one possible example, in obtaining the plurality of decision voltage values by obtaining the decision voltage values corresponding to each of the plurality of sets of reference storage durations and program erase times, the program includes instructions for performing the following steps:

when the sample data is stored for a reference storage time length i, determining the number distribution of the storage units of which the reference voltage thresholds of the plurality of first storage units in the first state are under different voltage values to obtain a first distribution curve, and determining the number distribution of the storage units of which the reference voltage thresholds of the plurality of second storage units in the second state are under different voltage values to obtain a second distribution curve;

and determining a reference voltage threshold corresponding to the intersection point of the first distribution curve and the second distribution curve as a read voltage value corresponding to the reference storage time length i and the programming and erasing times i.

In one possible example, in the aspect that the second data is obtained by performing a read operation on the second storage area according to the decision voltage value, the program includes instructions for performing the following steps:

determining a physical address of the second parity bit according to a logical address of the second parity bit in the second storage area;

and reading the physical address of the second check bit according to the judgment voltage value to obtain the second data.

In one possible example, in respect of the reading of the first data stored by the first memory area at the time of the reading, the above-mentioned program comprises instructions for:

acquiring a second read voltage value from the preset voltage list at the reading moment; and

and reading the first information bit and the first check bit in the first storage area according to the second reading voltage value to obtain the first data and check bit data.

In one possible example, the physical address of the second parity bit further includes the physical address of the first information bit and the first parity bit, and the program 421 includes instructions for, in the reading of the first information bit and the first parity bit in the first storage area according to the second read voltage value to obtain the first data and the parity bit data:

and reading the physical addresses of the first information bit and the first check bit in the first storage area according to the second reading voltage value to obtain the first data and the check bit data.

In one possible example, in terms of the error correcting the first data in the first storage area according to the second data to obtain the corrected original data, the program 421 includes instructions for performing the following steps:

decoding the first data and the second data, and if the decoding is successful, obtaining the intermediate data;

and decoding the intermediate data and the check bit data read from the first storage area to obtain corrected original data.

In one possible example, the program 421 described above further includes instructions for performing the steps of:

and if the decoding of the first data and the second data fails, returning to the step of acquiring a second read voltage value from the preset voltage list.

In one possible example, the memory may include a flash memory.

The above description has introduced the solution of the embodiment of the present application mainly from the perspective of the method-side implementation process. It is understood that the electronic device comprises corresponding hardware structures and/or software modules for performing the respective functions in order to realize the above-mentioned functions. Those of skill in the art will readily appreciate that the present application is capable of hardware or a combination of hardware and computer software implementing the various illustrative elements and algorithm steps described in connection with the embodiments provided herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the electronic device may be divided into the functional units according to the method example, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

Fig. 5A is a block diagram of functional units of the data processing apparatus 500 provided in the embodiment of the present application. The data processing apparatus 500, said apparatus 500 comprising: an acquisition unit 501, a reading unit 502, and an error correction unit 503, wherein,

the acquiring unit 501 is configured to acquire original data and store the original data in a first storage area in a memory;

the obtaining unit 501 is further configured to, if a storage period of the original data exceeds a first preset duration, read intermediate data stored in the first storage area at any intermediate time in the storage period of the original data, and store the intermediate data in a second storage area in the memory, where the intermediate data is an expression form of the original data in the first storage area at any intermediate time; and

the reading unit 502 is configured to, at a reading time when the original data needs to be read, read second data stored in the second storage area at the reading time, and read first data stored in the first storage area at the reading time; and

the error correction unit 503 is configured to perform error correction on the first data in the first storage area according to the second data, so as to obtain corrected original data.

Optionally, in terms of the storing the original data in the first storage area of the memory, the obtaining unit 501 is specifically configured to:

Optionally, in terms of reading the intermediate data stored in the first storage area at the intermediate time, the obtaining unit 501 is specifically configured to:

at any intermediate moment, acquiring a first reading voltage value; and

Optionally, in the aspect of acquiring the first read voltage value, the acquiring unit 501 is specifically configured to:

Alternatively, as shown in fig. 5B, fig. 5B is a modified structure of the data processing apparatus shown in fig. 5A, which, compared with fig. 5A, further includes: the creating unit 504 is specifically as follows:

the creating unit 504 is configured to obtain, in advance, for preset sample data, read voltage values corresponding to each of the multiple groups of reference storage durations and the multiple writing and erasing times, so as to obtain multiple read voltage values; and

Optionally, in the aspect of obtaining the read voltage values corresponding to each of the multiple groups of reference storage durations and program/erase times to obtain multiple read voltage values, the creating unit 504 is specifically configured to:

Optionally, in terms of the storing the intermediate data in the second storage area of the memory, the obtaining unit 501 is specifically configured to:

Optionally, in terms of reading the second data stored in the second storage area at the reading time, the reading unit 502 is specifically configured to:

acquiring a judgment voltage value at the reading moment; and

Optionally, in terms of obtaining the decision voltage value, the reading unit 502 is specifically configured to:

Optionally, the creating unit 504 is further configured to:

Optionally, in the aspect of obtaining the decision voltage values corresponding to each of the multiple groups of reference storage durations and program/erase times to obtain multiple decision voltage values, the creating unit 504 is specifically configured to:

Optionally, in the aspect that the reading operation is performed on the second storage area according to the decision voltage value to obtain the second data, the reading unit 502 is specifically configured to:

Optionally, in terms of reading the first data stored in the first storage area at the reading time, the reading unit 502 is specifically configured to:

Optionally, the physical addresses of the second parity bits further include physical addresses of the first information bits and the first parity bits, and in terms of reading the first information bits and the first parity bits in the first storage area according to the second read voltage value to obtain the first data and the parity bits, the reading unit 502 is specifically configured to:

reading the physical addresses of the first information bit and the first check bit in the first storage area according to the second reading voltage value to obtain the first data and the check bit data

Optionally, in terms of performing error correction on the first data in the first storage area according to the second data to obtain corrected original data, the error correction unit 503 is specifically configured to:

Optionally, the error correction unit 503 is further configured to:

Optionally, the memory may comprise a flash memory.

It can be seen that the data processing apparatus described in the embodiment of the present application obtains the original data and stores the original data in the first storage area in the memory; if the storage period of the original data exceeds a first preset time length, at any intermediate time in the storage period of the original data, reading intermediate data stored in the first storage area at the intermediate time, storing the intermediate data in a second storage area in the memory, at the reading time when the original data needs to be read, reading second data stored in the second storage area at the reading time, reading first data stored in the first storage area at the reading time, and correcting errors of the first data in the first storage area according to the second data to obtain corrected original data.

It is to be understood that the functions of each program module of the data processing apparatus in this embodiment may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the relevant description of the foregoing method embodiment, which is not described herein again.

Embodiments of the present application also provide a computer storage medium, where the computer storage medium stores a computer program for electronic data exchange, the computer program enabling a computer to execute part or all of the steps of any one of the methods described in the above method embodiments, and the computer includes an electronic device.

Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments. The computer program product may be a software installation package, the computer comprising an electronic device.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above-mentioned method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A method of data processing, the method comprising:

performing error correction twice on the first data of the first storage area according to the second data to obtain corrected original data; decoding the first data and the second data, and if the decoding is successful, obtaining the intermediate data; and decoding the intermediate data and the check bit data of the original data read from the first storage area to obtain the corrected original data.

2. The method of claim 1, wherein storing the raw data to a first storage area in a memory comprises:

3. The method according to claim 1 or 2, wherein the reading of the intermediate data stored in the first storage area at the intermediate time comprises:

at any intermediate moment, acquiring a first reading voltage value; and

4. The method of claim 3, wherein obtaining the first read voltage value comprises:

5. The method of claim 4, further comprising:

6. The method of claim 5, wherein obtaining the read voltage values corresponding to each of the plurality of sets of reference storage durations and program/erase times comprises:

writing and erasing times j are recorded aiming at the sample data under a reference storage duration i, wherein the reference storage duration i is any reference storage duration, and the following operations are executed:

determining an overlapping voltage range of the first and second voltage ranges, wherein a plurality of the read voltage values lie within the overlapping voltage range.

7. The method of claim 6, wherein obtaining the read voltage values corresponding to each of the plurality of sets of reference storage durations and program/erase times further comprises:

arranging a plurality of first reference threshold voltages which are larger than the left end point of the overlapping voltage range in the plurality of first reference threshold voltages in a descending order to obtain a first sequence, and determining that the nth first reference threshold voltage in the first sequence is a read voltage value corresponding to the reference storage time length i and the programming and erasing times j, wherein n is a preset value; or,

and arranging the second reference threshold voltages smaller than the right end point of the overlapping voltage range in the second reference threshold voltages in a descending order to obtain a second sequence, and determining the nth second reference threshold voltage in the second sequence as a read voltage value corresponding to the reference storage time length i and the programming and erasing times j.

8. The method of claim 6, wherein storing the intermediate data to a second storage area in the memory comprises:

programming the second parity bit into a second storage area in the memory resulting in a second codeword associated with the intermediate data.

9. The method of claim 8, wherein reading the second data stored by the second storage area at the reading time comprises:

acquiring a judgment voltage value at the reading moment; and

10. The method of claim 9, wherein obtaining the decision voltage value comprises:

11. The method of claim 10, further comprising:

12. The method of claim 11, wherein obtaining the decision voltage values corresponding to each of the plurality of sets of reference storage durations and program-erase times comprises:

and determining a reference voltage threshold corresponding to the intersection point of the first distribution curve and the second distribution curve as a read voltage value corresponding to the reference storage time length i and the programming and erasing times j.

13. The method according to any one of claims 9-12, wherein the reading the second storage area according to the decision voltage value to obtain the second data comprises:

14. The method according to claim 10, wherein the reading the first data stored in the first storage area at the reading time comprises:

15. The method of claim 14, wherein the physical addresses of the second parity bits further include physical addresses of the first information bits and the first parity bits, and wherein reading the first information bits and the first parity bits in the first storage area according to the second read voltage value to obtain the first data and parity bits comprises:

16. The method according to claim 14 or 15, wherein said performing two error corrections on the first data of the first storage area according to the second data to obtain the corrected original data comprises:

decoding the first data and the second data, and if the decoding is successful, obtaining intermediate data, wherein the intermediate data is obtained after the first data is subjected to first error correction;

and decoding the intermediate data and the check bit data read from the first storage area to obtain corrected original data, wherein the corrected original data is obtained by performing second error correction on the first data.

17. The method of claim 16, further comprising:

18. The method of claim 1, wherein the memory comprises flash memory.

19. A data processing apparatus, characterized in that the apparatus comprises:

a reading unit, configured to read, at a reading time when the original data needs to be read, second data stored in the second storage area at the reading time, and read first data and check bit data stored in the first storage area at the reading time; and

the error correction unit is used for carrying out error correction twice on the first data of the first storage area according to the second data to obtain corrected original data; the error correction unit is specifically configured to decode the first data and the second data, and if the decoding is successful, obtain the intermediate data; and decoding the intermediate data and the check bit data read from the first storage area to obtain corrected original data.

20. The apparatus according to claim 19, wherein the error correction unit is specifically configured to:

21. An electronic device comprising a processor, a memory for storing one or more programs and configured for execution by the processor, the programs comprising instructions for performing the steps of the method of any of claims 1-18.

22. A computer-readable storage medium, characterized in that a computer program for electronic data exchange is stored, wherein the computer program causes a computer to perform the method according to any one of claims 1-18.