CN101496110B - Distortion estimation and cancellation in memory devices - Google Patents

Distortion estimation and cancellation in memory devices Download PDF

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CN101496110B
CN101496110B CN2007800261211A CN200780026121A CN101496110B CN 101496110 B CN101496110 B CN 101496110B CN 2007800261211 A CN2007800261211 A CN 2007800261211A CN 200780026121 A CN200780026121 A CN 200780026121A CN 101496110 B CN101496110 B CN 101496110B
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voltage level
cross
data
memory
analog
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CN101496110A (en
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O·沙尔维
N·萨莫
E·格吉
A·梅斯罗斯
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苹果公司
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Priority to US82706706P priority
Priority to US60/827,067 priority
Priority to US86739906P priority
Priority to US60/867,399 priority
Priority to US88502407P priority
Priority to US60/885,024 priority
Priority to US88642907P priority
Priority to US60/886,429 priority
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Priority to PCT/IL2007/000576 priority patent/WO2007132453A2/en
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements

Abstract

一种用于操作存储器(28)的方法,包括将数据作为相应的第一电压电平存储在存储器的一组模拟存储单元(32)中。 A method for operating a memory (28), comprising a set of data as in the analog memory cells of the memory (32) corresponding to a first voltage level storage. 在存储所述数据之后,从相应的模拟存储单元读取第二电压电平。 After storing the data read from the second voltage level corresponding analog memory cells. 第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致第二电压电平不同于相应的第一电压电平。 Effects of the second voltage level being cross-coupled interference, the interference causes cross-coupling a second voltage level different from the corresponding first voltage level. 通过处理第二电压电平来估计对模拟存储单元之间的交叉耦合干扰进行量化的交叉耦合系数。 By processing the second voltage level estimate of cross-coupled interference between the quantized analog memory unit cross-coupling coefficients. 使用所估计的交叉耦合系数,从所读取的第二电压电平重构存储在该组模拟存储单元中的数据。 Using a cross coupling coefficient estimated data reconstructed from the second voltage level stored in the set of the read analog memory cells.

Description

存储设备中的失真估计和消除 Storage devices and eliminate distortion estimation

[0001] 相关申请的交叉引用 CROSS [0001] REFERENCE TO RELATED APPLICATIONS

[0002] 本申请要求享有下列专利申请的权益:提交于2006年5月12日的美国临时专利申请60/747,106、提交于2006年11月28日的美国临时专利申请60/867,399、提交于2006年7月4日的美国临时专利申请60/806,533、提交于2006年9月27日的美国临时专利申请60/827,067、提交于2007年I月16日的美国临时专利申请60/885,024和提交于2007年I月24日的美国临时专利申请60/886,429,上述申请的公开内容在此以援引方式全部纳入本文中。 [0002] This application claims the benefit of the following patent applications: US Provisional Patent US provisional patent filed on May 12, 2006 Application 60 / 747,106, filed on November 28, 2006 Application 60 / 867,399 US provisional Patent filed on July 4, 2006 application 60 / 806,533, filed in US provisional Patent September 27, 2006 application 60 / 827,067, filed on May 16, 2007 I US provisional Patent application No. 60 / 885,024 and US provisional Patent disclosures filed on May 24, 2007 I application 60 / 886,429, filed in the above-cited this to totally incorporated herein by reference.

技术领域 FIELD

[0003] 本申请主要涉及存储设备,具体涉及用于对存储设备中的失真进行估计和补偿的方法和系统。 [0003] The present application relates to a storage device, particularly relates to a storage device for distortion estimation and compensation methods and systems.

背景技术 Background technique

[0004] 多种存储设备,例如闪存和动态随机存取存储器(DRAM),使用模拟存储单元阵列来存储数据。 [0004] The plurality of memory devices, such as flash memory, and dynamic random access memory (DRAM), use analog memory cell array to store data. 例如,在2003年4月在IEEE学报91卷第4期第489-502页由Bez等人发表的“Introduction to FlashMemory”中,描述了闪存设备,该文献在此处以援引方式全部纳入本文。 For example, in April 2003 in the IEEE Journal 91, No. 4 pp. 489-502 published by Bez et al., "Introduction to FlashMemory", describes a flash memory device, which is incorporated herein by citing totally incorporated herein by reference. [0005] 在此类存储设备中,每个模拟存储单元通常包括一个晶体管,该晶体管保持了一定数量的电荷,所述电荷表示存储在所述存储单元中的信息。 [0005] In such a storage device, each analog memory cell typically comprises a transistor, the transistor remains a certain amount of charge, the charge represents the information stored in the storage unit. 写入一特定存储单元的电荷影响所述存储单元的“门限电压”,也即,需要施加电压到存储单元以使得所述存储单元传导一定数量的电流。 Write a particular memory cell of the memory cell charge Effect "threshold voltage", i.e., the voltage to be applied to the memory cell to the memory cell current so that a certain amount of conduction.

[0006] 一些存储设备,通常称为“单层单元”(SLC)设备,在每个存储单元中存储单比特信息。 [0006] Some storage devices, commonly referred to as a "single unit" (the SLC) device, storing a single bit of information in each storage unit. 通常,所述存储单元的可能的门限电压的范围被分为两个区域。 Typically, the range of possible threshold voltages of the memory cell is divided into two areas. 落入这两个区域中的一个区域的电压值代表比特值“0”,而属于另一个区域的电压值代表“I”。 Fall within the voltage value indicative of a bit value in the region of the two regions of "0", and the other representing the voltage value belonging to the region "I". 更高密度的设备,通常称为“多层单元”(MLC)设备,每个存储单元存储两个或更多个比特。 A higher density of devices, commonly referred to as "multi-level cell" (the MLC) devices, each memory cell stores two or more bits. 在多层单元中,门限电压的范围被分为多于两个区域,其中每个区域代表多于一个比特。 In multi-level cell, the threshold voltage range is divided into more than two regions, where each area represents more than one bit.

[0007] 例如,在纽约州纽约市举办的1996年IEEE国际电子器件大会(IEDM)的学报上的第169-172 页上由Eitan 等人发表的“MultilevelFlash Cells and their Trade-Offs”,描述了多层闪存单元和设备,该文献在此以援引方式全部纳入本文。 [0007] For example, on pages 169-172 of the 1996 IEEE International Journal of Electronic Devices Meeting (IEDM) in New York, NY, held published by Eitan et al., "MultilevelFlash Cells and their Trade-Offs", describes the and multi-level flash cell device, which is hereby incorporated in its entirety herein cited. 该文献对数种多层闪存单元进行比较,例如共地型、DINOR型、AND型、NOR型和NAND型存储单元。 The literature on several multi-level flash cell is compared, such as co-ground type, a DINOR type, AND type, NOR type and NAND type memory cell.

[0008] Eitan等人在1999年9月21至24日在日本东京举行的固态器件与材料国际会议(SSDM)的学报的第522 至524 页发表的“Can NR0M,a2-bit,Trapping Storage NVM Cell,Give a Real Challenge toFloating Gate Cells?”描述了另一种模拟存储单兀,称为氮化物只读存储器(NROM),该文献在此以援引方式纳入本文。 [0008] Eitan et al., Pp. 522-524 Journal of solid-state devices international conference held in Tokyo, Japan, 1999 September 21 to 24 and Materials (SSDM) published "Can NR0M, a2-bit, Trapping Storage NVM Cell, Give a Real Challenge toFloating Gate Cells? "describes another single analog storage Wu, called a nitride read only memory (the NROM), which is hereby incorporated herein in cited. 在2002年2月3日〜7日在美国加州旧金山市举办的IEEE国际固态电子器件学会(ISSCC 2002)的学报的第100-101页由Maayan 等人发表的“A 512 MbNROM Flash Data Storage Memory with 8 MB/s DataRate ”中,描述了NROM存储单元,其在此处以援引方式纳入本文。 On page 100-101 published by Maayan et al., "A 512 Journal February 3, 2002 ~ IEEE International Electron Devices Society solid at San Francisco, California, USA, held on the 7th (ISSCC 2002) of MbNROM Flash Data Storage Memory with 8 MB / s DataRate ", the NROM memory cell is described, which is incorporated herein cited herein.

[0009] 模拟存储单元的其他示例性类型为,铁电RAM(FRAM)单元、磁RAM(MRAM)单元、电荷捕获闪存(CTF)和相变RAM(PRAM,也称为相变存储器PCM)单元。 [0009] Other exemplary types of analog memory cells, ferroelectric RAM (FRAM) cell, a magnetic RAM (MRAM) cell, a charge trap flash (CTF) and phase-change RAM (PRAM, also known as phase-change memory PCM) cells . 例如,在2004年5月16日至19日在塞尔维亚和黑山的Nis举办的第24届微电子国际学会(MIEL)学报第一卷第377-384 页上由Kim 和Koh 发表的“Future Memory Technologyincluding Emerging NewMemories”中,描述了FRAM、MRAM和PRAM单元,其在此处以援引方式全部纳入本文。 For example, at the 24th International Institute of Microelectronics of Nis in Serbia and Montenegro held in 2004, May 16 to 19 (MIEL) Journal vol. I, page 377-384, published by Kim and Koh "Future Memory Technologyincluding Emerging NewMemories ", there is described FRAM, MRAM and PRAM unit, which is incorporated herein in its entirety herein cited.

[0010] 读取自模拟存储单元的门限电压值有时会失真。 [0010] read from an analog memory cell threshold voltage sometimes distorted. 这种失真有各种不同的原因,例如耦合自相邻存储单元的电场、由阵列中其他存储单元上的存储存取操作而导致的干扰噪声、以及由于设备老化导致的门限电压漂移。 This distortion has various reasons, for example, the electric field coupled from the adjacent memory cells, the memory access by the interference noise of other memory cells in the array due to an operation, and the threshold voltage due to the drift caused by the aging device. 一些常见的失真机制已由Bez等人在上文所引用的文章中进行了描述。 Some common distortion mechanism has been Bez, who is described in the article cited above. 在2002年5月的IEEE电子器件快报(23 :5)第264-266页上发表的“Effects of Floating Gate Interference on NAND FlashMemory Cell Operation,,中,Lee等人还描述了在失真效应,其在此处以援引方式全部纳入本文。 In May 2002, the IEEE Electron Device Letters: published in the (235) pp. 264-266 "Effects of Floating Gate Interference on NAND FlashMemory Cell Operation ,, in, Lee et al. Also describes the distortion effects, which here to invoke totally incorporated herein by reference.

[0011] 美国专利5,867,429,描述了一种用于对在高密度闪速可电擦除可编程只读存储(EEPROM)单元阵列中的浮置栅极之间耦合的电场进行补偿的方法,其公开内容在此以援引方式全部纳入本文。 [0011] U.S. Patent No. 5,867,429, describes a high density of electric field coupling between the floating gate of the flash cell array can be electrically erasable programmable read only memory (EEPROM) is compensated the method, the disclosure of which is hereby incorporated herein by citing all the way. 根据所公开的方法,对一个存储单元的读取是通过首先读取所有与正被读取的存储单元场耦合的存储单元的状态来补偿。 According to the method disclosed, the reading of a memory cell is compensated by the first reads the status of all memory cells and the memory cells being read field coupling. 然后将与每个耦合的存储单元的状态或浮置栅极电压相关的数目,乘以存储单元之间的耦合比。 Then the number associated with each state storage unit coupled to the floating gate or the voltage, multiplied by the ratio of the coupling between the memory cells. 在每个存储单元的各状态之间的断点电平是由一个补偿了耦合自相邻存储单元的电压的量来调整的。 Breakpoint levels between states of each memory cell is determined by a compensation amount of coupling from neighboring memory cells to voltage adjustment.

发明内容 SUMMARY

[0012] 本发明的实施方案提供了一种用于操作存储器的方法,包括: [0012] Embodiments of the invention provide a method for operating a memory, comprising:

[0013] 将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中,所述第一电压电平选自可能的值的集合; [0013] As the data corresponding to a first voltage level stored in a set of analog memory cells of the memory, the first voltage level is selected from a set of possible values;

[0014] 在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平; [0014] After storing the data, reads the corresponding second voltage level from said analog memory unit, the second voltage level is affected by cross coupling of interference, the interference causes cross-coupling the second voltage level is different from the corresponding first voltage level;

[0015] 处理所述第二电压电平以获得相应的硬判决,每个硬判决均对应于所述第一电压电平的可能的值中的相应值; [0015] processing the second voltage level to obtain the corresponding hard decision, each hard decision values ​​corresponding to respective all possible values ​​of the first voltage level in;

[0016] 基于所述第二电压电平和所述相应的硬判决估计交叉耦合系数,该交叉耦合系数量化所述模拟存储单元之间的交叉耦合干扰;以及 [0016] The cross coupling coefficient based on the estimated level and the hard decisions corresponding to the second voltage level, the cross coupling cross coupling interference between the quantized coefficients of the analog memory means; and

[0017] 使用所估计的交叉耦合系数,从所读取的第二电压电平重构存储在该组模拟存储单元中的数据。 [0017] using the estimated cross-coupling coefficient data reconstructed from the second voltage level stored in the set of the read analog memory cells.

[0018] 在一些实施方案中,估计交叉耦合系数包括使用块估计过程处理所述第二电压电平和所述相应的硬判决。 [0018] In some embodiments, the cross coupling coefficient estimating comprises estimating process using a block processing the second voltage level and the corresponding hard decision. 替代地,估计交叉耦合系数包括使用收敛到所述交叉耦合系数的序列估计过程以循序扫描所述第二电压电平以及所述相应的硬判决。 Alternatively, the cross coupling coefficient estimates converge to include the use of the cross-coupling coefficient sequence estimation procedure to sequentially scan the second voltage level and the corresponding hard decision. 估计交叉耦合系数可以包括采用一个减少在所述所读取的第二电压电平和所述相应的硬判决之间的距离度量的估计过程。 Cross coupling coefficient estimation may include the use of a reduction in the voltage level of the second level and the read process of the estimated distance metric between the respective hard decisions.

[0019] 在一个实施方案中,所述方法包括既基于读取自第一模拟存储单兀的第二电压电平又基于读取自第二模拟存储单元的第二电压电平,估算在所述存储器中由所述第一模拟存储单元导致的针对所述第二模拟存储单元的交叉耦合干扰。 [0019] In one embodiment, the method comprises both a second voltage level based on a first analog read from the storage unit based on the Wu and second voltage level read from the second analog memory cell, the estimate cross-coupled interference for the second analog memory means by the first analog memory cells in said memory caused.

[0020] 在另一个实施方案中,重构数据包括使用如下过程之一将所述交叉耦合干扰从所述第二电压电平中除去,所述过程为:线性均衡过程、判决反馈均衡(DFE)过程、最大后验(MAP)估计过程以及最大似然序列估计(MLSE)过程。 [0020] In another embodiment, the reconstructed data comprises using one of the following procedures to the cross-coupled interference removing from the second voltage level, the process is: linear equalization, decision feedback equalization (DFE ) process, maximum a posteriori (MAP) estimation process and a maximum likelihood sequence estimation (the MLSE) process. 在又一个实施方案中,估计交叉耦合系数与重构数据包括在第一处理阶段中估计所述交叉耦合系数,并且在后继于所述第一处理阶段的第二处理阶段中消除所估计的交叉耦合干扰。 In yet another embodiment, the cross coupling coefficient estimation and reconstruction data comprises estimating the coefficients in the first cross-coupled process stage, and in the subsequent stage of the first process to the second process stage to eliminate the estimated cross coupled interference. 在又一个实施方案中,估计交叉耦合系数与重构数据包括将所估计的交叉耦合系数用于所述第二处理阶段的后继情况,并且仅当未能重构所述数据时才重复所述第一处理阶段。 In yet another embodiment, when the estimated cross-coupling coefficient and the reconstructed data comprising the estimated cross coupling coefficient for the second case the subsequent processing stage, and only when the data fails to reconstruct the repeated The first processing stage.

[0021] 在一个公开的实施方案中,存储数据包括使用纠错码(ECC)编码所述数据,重构数据包括基于所估计的交叉耦合系数计算纠错度量并且使用所述纠错度量解码所述ECC。 [0021] In one embodiment of the disclosed embodiment, the data comprises storing error correction code (ECC) encoding the data, reconstructed data comprising an error correction metric is calculated based on the estimated cross-coupling coefficient and using the error correction decoding metric said ECC.

[0022] 根据本发明的一个实施方案,还提供了一种用于操作存储器的方法,包括: [0022] According to one embodiment of the present invention there is also provided a method for operating a memory, comprising:

[0023] 将数据作为相应的第一电压电平存储在所述存储器的模拟存储单元中,其中所述模拟存储单元的子集具有相关失真; [0023] The data corresponding to a first voltage level stored in the analog memory cells of the memory, wherein a subset of said analog memory means having an associated distortion;

[0024] 在存储所述数据之后,从所述子集中的一个或多个模拟存储单元读取相应的第二电压电平,该第二电压电平由于所述相关失真而不同于所述第一电压电平; [0024] After storing the data, reads the corresponding second voltage level from a plurality of analog memory cells or the subset, the second voltage level because the correlation different from said first distortion a voltage level;

[0025] 处理读取自所述一个或多个模拟存储单元的第二电压电平,以便估计在所述第二电压电平中的相应失真度(distortion level); [0025] The process of reading from the second voltage level or a plurality of analog memory cells, in order to estimate the distortion in the corresponding voltage level in a second (distortion level);

[0026] 从所述子集中的其他模拟存储单元读取一个第二电压电平; [0026] a second read voltage level from the other analog memory cells in the subset;

[0027] 基于所估计的所述子集中的一个或多个模拟存储单元的相应失真度,预测读取自所述其他模拟存储单元的第二电压电平中的失真度; [0027] Based on the one or more respective distortion analog memory cells in the subset being estimated, predicted degree of distortion analog read from the other memory cell of a second voltage level;

[0028] 使用预测的失真度,校正读取自所述其他模拟存储单元的第二电压电平;以及 [0028] using the predicted distortion, correction read from said second voltage level other analog memory unit; and

[0029] 基于所校正的第二电压电平,重构在所述其他模拟存储单元中存储的数据。 [0029] The second voltage level based on the corrected reconstructed data stored in the other analog memory unit.

[0030] 在一些实施方案中,存储单元的子集包括选自下列一组子集类型中的至少一个子集类型:位于公共位线上的存储单元、位于公共字线上的存储单元、具有公共电路的存储单元和彼此位置接近的存储单元。 [0030] In some embodiments, a subset of the selected memory cell includes at least a subset of the subset of the type consisting of a set of types: bit lines in a common storage unit, the storage unit located in a common word line, having common circuit memory cell and a position close to each other in the storage unit.

[0031 ] 在一个实施方案中,处理第二电压电平包括仅缓存单个值,该值指示从所述子集中的一个或多个模拟存储单元中读取的第二电压电平的失真度,且其中预测失真度包括基于缓存的所述单个值计算预测的失真度。 [0031] In one embodiment, the process comprises a second voltage level cache only a single value indicating the degree of distortion of a second voltage level read from the one or more analog memory cells of said subset, and wherein the distortion prediction distortion comprises calculating the predicted value based on the single cache. 在另一个实施方案中,预测失真包括追踪对于所述模拟存储单元的子集为共有的失真参数,并且将所述失真参数存储在数据结构中。 In another embodiment, the prediction for the total distortion including distortion tracking parameters for a subset of the analog memory means, and said data structure is stored in the distortion parameter.

[0032] 根据本发明的一个实施方案,还提供了一种用于操作存储器的方法,包括: [0032] According to one embodiment of the present invention there is also provided a method for operating a memory, comprising:

[0033] 将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中; [0033] As the data corresponding to a first voltage level stored in a set of analog memory cells of the memory;

[0034] 在所述存储器中的第一模拟存储单元上执行存储器存取操作; [0034] performing a first memory access operation on the analog memory in the memory unit;

[0035] 响应于执行的存储器存取操作,从所述存储器中的第二模拟存储单元读取第二电压电平; [0035] In response to a memory access operation executed, reads the second voltage level from said second analog memory storage unit;

[0036] 处理所述第二电压电平,从而估计在所述第二电压电平中的扰动电平(level ofdisturbance),该扰动电平是由在所述第一模拟存储单元上执行的存储器存取操作所导致; [0036] processing the second voltage level, so that the estimated disturbance level (level ofdisturbance) in said second voltage level, the level is determined by the disturbance of memory operation performed on the first analog memory unit resulting access operation;

[0037] 使用所估计的扰动电平,校正所述第二电压电平;以及 [0037] using the estimated disturbance level, correcting the second voltage level; and

[0038] 基于所校正的第二电压电平,重构在所述第二模拟存储单元中存储的数据。 [0038] a second voltage level based on the corrected reconstructed data stored in the second analog memory cells. [0039] 在一些实施方案中,存储器存取操作包括选自下列一组操作中的至少一种操作:编程操作、读操作和擦除操作。 [0039] In some embodiments, the memory access operation includes operations selected from the group at least one operation: a program operation, read operation and erase operation. 处理和校正第二电压电平可以包括将所估计的扰动电平与预定义电平作比较,且仅当所估计的扰动电平超过所述预定义电平时才校正所述第二电压电平。 And a correction process may include a second voltage level be compared with a predefined level of disturbance level estimated, and only if the estimated disturbance level exceeds the predefined level is corrected in the second voltage level. 在一个实施方案中,校正第二电压电平包括对所述第二模拟存储单元中存储的数据重新编程。 In one embodiment, the second correction voltage level comprises reprogramming the second analog data storage unit. 在另一个实施方案中,校正第二电压电平包括将存储在所述第二模拟存储单元中的数据复制到不同于所述第二模拟存储单元的其他模拟存储单元中。 In another embodiment, the second correction voltage level comprises copying the analog data stored in the second storage unit to the other analog memory cells is different from the second analog memory unit. 替代地,校正第二电压电平可包括增大用于将数据存储在所述第二模拟存储单元中的第一电压电平。 Alternatively, the correction may include a second voltage level is increased for a first voltage level of the data stored in said second analog memory unit. 可以在不对所述数据作存储和读取的空闲时段期间执行对第二电压电平的处理。 Process may be performed on a second voltage level during the data for storage and does not read the idle period.

[0040] 在一个公开的实施方案中,读取第二电压电平包括从相应的多个第二模拟存储单元读取多个第二电压电平,且处理第二电压电平包括对多个由于存储器存取操作而从已擦除电平转换到已编程电平的第二模拟存储单元进行评估。 [0040] In one embodiment of the disclosed embodiment, the second voltage level reading comprises reading a plurality of second voltage levels from the respective plurality of second analog memory unit, and the processing of the second voltage level comprises a plurality of Since the memory access operation is converted from the erased level to a programmed level of the second analog memory cells for evaluation. 在另一个实施方案中,存储数据包括将所述数据循序存储在所述模拟存储单元的多个组中,读取第二电压电平包括以逆序读取所述模拟存储单元的多个组,且处理第二电压电平包括估计响应于在所述第一模拟存储单元之前读取的所述组中的模拟存储单元的第二电压对所述第一模拟存储单元导致的扰动电平。 In another embodiment, the data comprises storing the data sequentially stored in a plurality of groups of said analog memory unit, reads the second voltage level comprises a plurality of groups in the reverse order of reading the analog memory means, and the processing comprises estimating a second voltage level in response to the voltage of the second set of read prior to the first analog memory unit of analog memory means for storing the first analog unit level disturbance caused.

[0041] 根据本发明的一个实施方案,还提供了一种用于操作存储器的方法,包括: [0041] According to one embodiment of the present invention there is also provided a method for operating a memory, comprising:

[0042] 将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中; [0042] As the data corresponding to a first voltage level stored in a set of analog memory cells of the memory;

[0043] 在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,所述第二电压电平中的至少一些不同于所述相应的第一电压电平; [0043] After storing the data, reads the corresponding second voltage level from said analog memory means, a second voltage level different from at least some of said corresponding first voltage level;

[0044] 识别潜在地导致针对读取自目标模拟存储单元的第二电压电平的失真的模拟存储单元的子集; [0044] identify a subset of potentially cause distortion analog memory cells for a second target voltage level read from the analog memory unit;

[0045] 基于数据被存储在所述模拟存储单元中的相应时间和数据被存储在所述目标模拟存储单元中的时间之间的关系,将所述子集中的模拟存储单元分成多个类; [0045] Based on the relationship between the target time simulation data storage unit and corresponding time data stored in the analog memory unit is stored in the analog memory means into a plurality of the subset of the classes;

[0046]为所述类的每一个估计由该类中的模拟存储单元针对所述目标模拟存储单元中的第二电压电平所导致的相应失真; [0046] estimated by the class corresponding to the distortion in the analog memory cells for a second target voltage level of the analog memory unit resulting for each of said classes;

[0047] 使用为所述类中的一个或多个类中的每一个所估计的相应失真,校正读取自所述目标模拟存储单元的第二电压电平;以及 [0047] Using the estimated for each class corresponding to the distortion of the one or more classes, reads the second correction voltage level from said target analog memory unit; and

[0048] 基于所校正的第二电压电平,重构在所述目标模拟存储单元中存储的数据。 [0048] a second voltage level based on the corrected reconstructed data is stored in the target analog memory unit.

[0049] 在一些实施方案中,存储数据和读取第二电压电平包括应用编程与验证(P&V)过程。 [0049] In some embodiments, storing data and reading the second voltage level includes an application programming and verification (P & V) process. 在一个实施方案中,分类模拟存储单元包括识别所述子集中的比所述目标模拟存储单元更为新近地将数据存储在其中的模拟存储单元,且其中校正第二电压电平包括基于仅在所识别的模拟存储单元中的失真来校正读取自所述目标模拟存储单元的第二电压电平。 In one embodiment, the analog memory means comprises a classification identifying the subset of analog memory cells than the target to the more recent data stored in said analog memory means therein, and wherein the correction comprises a second voltage level based only on analog memory means in the identified distortion correction reads the second target voltage level from the analog memory cells. 在一个替代性的实施方案中,分类模拟存储单元包括:定义第一类,其包括在所述子集中的比所述目标模拟存储单元更为新近地将数据存储在其中的模拟存储单元;第二类,其包括在所述子集中的比所述目标模拟存储单元更早地将数据存储在其中的模拟存储单元;和第三类,其包括在所述子集中的与所述目标模拟存储单元并发地将数据存储在其中的模拟存储单元。 In an alternative embodiment, the classification unit analog memory comprising: defining a first class, which is included in the subset of analog memory cells than the more recent target data stored therein to the analog memory means; first type II, which comprises the subset of the target than earlier analog memory unit in which the analog memory unit data; and a third category which includes in the subset of the target analog memory concurrently unit the data stored in analog memory cells therein.

[0050] 在另一个实施方案中,读取第二电压电平、估计失真和校正第二电压电平包括,以第一分辨率处理读取自所述目标模拟存储单元的第二电压电平,并且以比所述第一分辨率更不精确的第二分辨率处理读取自所述子集中的模拟存储单元的第二电压电平。 [0050] In another embodiment, a second read voltage level, and the estimated distortion correction comprises a second voltage level, a first resolution to a second process of reading from the target voltage level of the analog memory unit a second voltage level, and are less accurate than the first resolution, the second resolution read from the processing of the subset of analog memory cells. 在又一个实施方案中,存储数据包括存储所述数据被存储在所述模拟存储单元时的时间标记,且分类模拟存储单元包括查询所存储的标记。 In yet another embodiment, the storage of data comprises storing the data at the time when the analog memory flag storage unit, and the analog memory means comprises a classification flag stored query. 在另一个实施方案中,估计失真包括响应于选自下列一组参数中的至少一个参数来估计失真度,所述参数包括:所述模拟存储单元的编程次数、存储在所述模拟存储单元中的数据、所述模拟存储单元相对于所述目标模拟存储单元的位置以及所述目标存储单元最近已经经历的编程-擦除循环的次数。 In another embodiment, the estimated distortion comprises in response to at least one parameter selected from the set of parameters to estimate distortion, said parameters comprising: programming the frequency of the analog memory unit, stored in the analog memory unit data, the analog memory unit with respect to the target simulation program storage unit and a position of the target memory cell has recently been experienced - the number of erase cycles.

[0051]根据本发明的一个实施方案,还提供了一种用于操作存储器的方法,包括: [0051] According to one embodiment of the present invention there is also provided a method for operating a memory, comprising:

[0052] 接受用于存储在所述存储器中的数据; [0052] for receiving the data stored in the memory;

[0053] 确定相应的第一电压电平,用于对所述存储器的一组模拟存储单元编程,从而使得所述模拟存储单元存储表示所述数据的物理量的相应值; [0053] determining a corresponding first voltage level, the analog memory cells for programming the memory is set such that the analog memory unit stores a corresponding value of the physical quantity data;

[0054] 使用确定的第一电压电平对所述组中的模拟存储单元编程; [0054] determined using a first voltage level of the analog memory cells programmed in the group;

[0055] 在对所述模拟存储单元编程之后,从相应的模拟存储单元读取第二电压电平并且从所述第二电压电平重构数据。 [0055] After the analog memory cells for programming, reading from a second voltage level of the corresponding analog memory cells and reconstructs data from the second voltage level.

[0056] 在一些实施方案中,确定第一电压电平包括当将所述数据存储在目标模拟存储单元中时,对由存储在一个或多个其他模拟存储单元中的物理量的值所导致的针对存储在所述目标模拟存储单元中的物理量的值的失真进行估计,并且响应于所估计的失真预先校正用于所述目标模拟存储单元编程的第一电压电平。 [0056] In some embodiments, comprises determining a first voltage level when the target when the analog memory unit, the value of the physical quantity is stored in one or more other analog memory unit stores data resulting from the estimating distortion values ​​for the distortion of the target physical quantity stored in the analog memory unit, and in response to the estimated beforehand for correcting the target memory cell programming a first analog voltage level. 在另一个实施方案中,重构数据包括:当读取所述第二电压电平时,基于所读取的第二电压电平对由存储在一个或多个其他模拟存储单元中的物理量的值所导致的针对存储在目标模拟存储单元中的物理量的值的失真进行估计;使用所估计的失真校正读取自所述目标模拟存储单元的第二电压电平;并且基于所校正的第二电压电平重构存储在所述目标模拟存储单元中的数据。 In another embodiment, the reconstructed data comprising: when reading the second voltage level, second voltage level based on the read value of the physical quantity is stored in one or more other analog memory unit resulting estimated distortion value for the physical quantity is stored in the target analog memory unit; using the estimated distortion correction reads the second target voltage level from said analog memory means; and a second voltage based on the corrected the simulated target data storage unit stores the reconstructed level.

[0057] 编程模拟存储单元可以包括验证已编程的第一电压电平。 [0057] The analog memory unit may include a program verify voltage level of a first programmed. 在一些实施方案中,物理量包括电荷。 In some embodiments, the physical quantity comprising a charge.

[0058] 根据本发明的一个实施方案,还提供了一种用于操作存储器的方法,包括: [0058] According to one embodiment of the present invention there is also provided a method for operating a memory, comprising:

[0059] 将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中; [0059] As the data corresponding to a first voltage level stored in a set of analog memory cells of the memory;

[0060] 在存储所述数据之后,从所述组中的模拟存储单元读取第二电压电平,所述第二电压电平中的至少一些不同于所述相应的第一电压电平; [0060] After storing the data read from the second voltage level of the analog memory cells in the group, the second voltage level different from at least some of said corresponding first voltage level;

[0061] 估计读取自所述模拟存储单元中的第二电压电平中的失真度;以及 [0061] The estimated distortion of the second voltage level is read from the analog memory unit; and

[0062] 当所估计的失真度违反了预定的失真判据时,将所述数据重新编程到所述存储器的模拟存储单元中。 [0062] When the estimated distortion violates a predetermined distortion criterion, the reprogramming data to the analog memory cells of the memory.

[0063] 在一些实施方案中,预定的失真判据包括一个定义最大可容忍的失真度的门限。 [0063] In some embodiments, the distortion criterion comprises a predetermined threshold defines the maximum tolerable level of distortion.

[0064] 根据本发明的一个实施方案,还提供了一种用于操作存储器的方法,包括: [0064] According to one embodiment of the present invention there is also provided a method for operating a memory, comprising:

[0065] 将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中; [0065] As the data corresponding to a first voltage level stored in a set of analog memory cells of the memory;

[0066] 在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,所述第二电压电平中的至少一些不同于所述相应的第一电压电平; [0066] After storing the data, reads the corresponding second voltage level from said analog memory means, a second voltage level different from at least some of said corresponding first voltage level;

[0067] 识别潜在地导致针对读取自目标模拟存储单元的第二电压电平的失真的模拟存储单元的子集; [0067] identifying a subset of potentially cause distortion analog memory cells for a second target voltage level read from the analog memory unit;

[0068] 估计在所述目标模拟存储单元被编程的第一瞬时由在所述子集中的模拟存储单元导致的针对所述目标模拟存储单元的第一失真度与所述目标模拟存储单元被读取的第二瞬时由在所述子集中的模拟存储单元导致的针对所述目标模拟存储单元的第二失真度之间的差;以及 [0068] estimate for the target analog memory cells of the first distortion and the target analog memory cells in the first instant target analog memory cell is programmed by results in the subset of analog memory unit instantaneous read by the second subset of the analog memory cells due to a difference between the second target distortion for the analog memory unit; and

[0069] 使用所估计的差,校正读取自所述目标模拟存储单元的第二电压电平。 [0069] using the estimated difference correction reads the second target voltage level from the analog memory cells.

[0070] 根据本发明的一个实施方案,还提供了一种用于操作存储器的方法,包括: [0070] According to one embodiment of the present invention there is also provided a method for operating a memory, comprising:

[0071] 将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中; [0071] As the data corresponding to a first voltage level stored in a set of analog memory cells of the memory;

[0072] 在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平; [0072] After storing the data, reads the corresponding second voltage level from said analog memory unit, the second voltage level is affected by cross coupling of interference, the interference causes cross-coupling the second voltage level is different from the corresponding first voltage level;

[0073] 估计交叉耦合系数,其通过处理所述第二电压电平而将所述模拟存储单元之间的交叉耦合干扰量化;以及[0074] 使用所估计的交叉耦合系数,从所读取的第二电压电平重构存储在该组模拟存储单元中的数据。 [0073] Estimated cross coupling coefficient, by processing the second voltage level to cross coupling interference between the quantized analog memory means; and a cross-coupling coefficients [0074] using the estimated from the read a second voltage level data stored in the set of reconstructed analog memory cells.

[0075] 在一些实施方案中,既基于读取自第一模拟存储单元的第二电压电平又基于读取自第二模拟存储单元的第二电压电平,评估由第一模拟存储单元针对存储器中第二模拟存储单元导致的交叉耦合干扰。 [0075] In some embodiments, both based on a second voltage level of the analog read from the first memory cell and a second voltage level based on the reading from the second analog memory cell, for the evaluation of the first analog memory unit the second analog memory storage unit caused by cross-coupled interference.

[0076] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0076] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0077] 接口,其操作性地与包含多个模拟存储单元的存储器通信;以及 [0077] interfaces, operatively in communication with a memory comprising a plurality of analog memory means; and

[0078] 存储器信号处理器(MSP),其被耦合到所述接口并且被布置为:将数据作为选自可能的值的集合的相应的第一电压电平存储在一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平;处理所述第二电压电平以获得相应的硬判决,每个硬判决均对应于所述第一电压电平的可能的值中的相应值;基于所述第二电压电平和所述相应的硬判决估计交叉耦合系数,该交叉耦合系数量化所述模拟存储单元之间的交叉耦合干扰;以及使用所估计的交叉耦合系数,从所述第二电压电平重构存储在该组模拟存储单元中的数据。 [0078] The memory signal processor (MSP), which is coupled to the interface and arranged to: the selected data as possible values ​​corresponding first voltage level in a set of stored set of analog memory unit; after storing the data, reads the corresponding second voltage level from said analog memory unit, the second voltage level is affected by cross coupling of interference, the cross-coupling interference causes the second voltage level is different the respective first voltage level; processing the second voltage level to obtain the corresponding hard decision, each hard decision values ​​corresponding to respective all possible values ​​of the first voltage level in; based calm said hard decision estimating the respective second voltage cross coupling coefficients, the quantization coefficient of cross coupling cross coupling interference between said analog memory means; and using the estimated cross-coupling coefficient, from the second voltage level of the data in the set of reconstructed analog memory storage unit.

[0079] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0079] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0080] 接口,其操作性地与包含多个模拟存储单元的存储器通信,所述存储器的模拟存储单元的子集具有相关失真;以及 [0080] interface operatively subset analog memory cells of the memory communications, said memory comprising a plurality of analog memory cells having an associated distortion; and

[0081] 存储器信号处理器(MSP),其被耦合到所述接口并且被布置为:将数据作为相应的第一电压电平存储在所述模拟存储单元中;在存储所述数据之后,从所述子集中的一个或多个模拟存储单元读取相应的第二电压电平,该第二电压电平由于所述相关失真而不同于所述第一电压电平;处理读取自所述一个或多个模拟存储单元的第二电压电平,以便估计在所述第二电压电平中的相应失真度;从所述子集中的其他模拟存储单元读取一个第二电压电平;基于所估计的所述子集中的一个或多个模拟存储单元的相应失真度,预测读取自所述其他模拟存储单元的第二电压电平中的失真度;使用预测的失真度,校正读取自所述其他模拟存储单元的第二电压电平;以及基于所校正的第二电压电平,重构在所述其他模拟存储单元中存储的数据。 [0081] The signal processor memory (the MSP), which is coupled to the interface and arranged to: the data as a respective first voltage level stored in the analog memory unit; after storing the data, from the one or more subset of analog memory cells to read the corresponding second voltage level, the second voltage level due to the distortion of the correlation is different from the first voltage level; the process of reading from one or more second voltage level of the analog memory cell, in order to estimate the corresponding distortion level of the second voltage; a second voltage level read from the other analog memory cells in the subset; based the estimated one or more distortion corresponding analog memory cells in the subset, the prediction read from the distortion of the second voltage level other of analog memory unit; using the predicted distortion, correction read from the second voltage level other analog memory unit; and a second voltage level based on the corrected reconstructed data stored in the other analog memory cells.

[0082] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0082] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0083] 接口,其操作性地与包含多个模拟存储单元的存储器通信;以及[0084] 存储器信号处理器(MSP),其被耦合到所述接口并且被布置为:将数据作为相应的第一电压电平存储在一组模拟存储单元中;在所述存储器中的第一模拟存储单元上执行存储器存取操作;响应于执行的存储器存取操作,从所述存储器中的第二模拟存储单元读取第二电压电平;处理所述第二电压电平,从而估计在所述第二电压电平中的扰动电平,该扰动电平是由在所述第一模拟存储单元上执行的存储器存取操作所导致;使用所估计的扰动电平,校正所述第二电压电平;以及基于所校正的第二电压电平,重构在所述第二模拟存储单元中存储的数据。 [0083] interfaces, operatively in communication with a memory comprising a plurality of analog memory cells; and [0084] a signal processor memory (the MSP), which is coupled to the interface and arranged to: the data as respective first a voltage level of a set stored in the analog memory unit; performing a first memory access operation on the analog memory cells in the memory; in response to a memory access operation performed from the second analog memory stores unit reads a second voltage level; processing the second voltage level, so that the estimated disturbance level of a second voltage level, the disturbance level is performed on the first analog memory unit the resulting memory access operation; using the estimated disturbance level, correcting the second voltage level; and a second voltage level based on the corrected reconstructed data stored in the second analog memory unit .

[0085] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0085] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0086] 接口,其操作性地与包含多个模拟存储单元的存储器通信;以及 [0086] interfaces, operatively in communication with a memory comprising a plurality of analog memory means; and

[0087] 存储器信号处理器(MSP),其被耦合到所述接口并且被布置为:将数据作为相应的第一电压电平存储在一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,所述第二电压电平中的至少一些不同于所述相应的第一电压电平;识别潜在地导致针对读取自目标模拟存储单元的第二电压电平的失真的模拟存储单元的子集;基于数据被存储在所述模拟存储单元中的相应时间和数据被存储在所述目标模拟存储单元中的时间之间的关系,将所述子集中的模拟存储单元分成多个类;为所述类的每一个估计由该类中的模拟存储单元针对所述目标模拟存储单元中的第二电压电平所导致的相应失真;使用为所述类中的一个或多个类中的每一个所估计的相应失真,校正读取自所述目标模拟存储单元的第二电压电平;以及基于所校 [0087] The signal processor memory (the MSP), which is coupled to the interface and arranged to: a first voltage corresponding to a data level stored in a set of analog memory cells; after storing the data, from the analog memory unit reads a second voltage level corresponding to the second voltage level different from at least some of said corresponding first voltage level; identifying potentially cause a target for a read from the analog memory unit a subset of the analog memory unit distortion second voltage level; and the corresponding time data is based on data stored in the analog memory unit is stored a relationship between the target time of the analog memory unit, the the analog memory means into a plurality of classes in the subset; estimating distortion caused by the corresponding class in the analog memory cells for a second target voltage level of the analog memory unit resulting for each of said classes; using estimating distortion for the corresponding class in the class in one or more of each of a second correction read voltage level from the target analog memory unit; and based on the correction 的第二电压电平,重构在所述目标模拟存储单元中存储的数据。 A second voltage level, the target data reconstructed in analog memory in the storage unit.

[0088] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0088] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0089] 接口,其操作性地与包含多个模拟存储单元的存储器通信;以及 [0089] interfaces, operatively in communication with a memory comprising a plurality of analog memory means; and

[0090] 存储器信号处理器(MSP),其被耦合到所述接口并且被布置为:接受用于存储在所述存储器中的数据;确定相应的第一电压电平,用于对一组模拟存储单元编程,从而使得所述模拟存储单元存储表示所述数据的物理量的相应值;使用所述第一电压电平对所述组中的模拟存储单元编程;在对所述模拟存储单元编程之后,从相应的模拟存储单元读取第二电压电平;并且从所述第二电压电平重构数据。 [0090] The signal processor memory (the MSP), which is coupled to the interface and arranged to: receive data for storage in the memory; determining a respective first voltage level, a set of simulation value corresponding memory cell programming, so that the analog memory unit stores the data representing a physical quantity; using the first voltage level of the analog memory cell of the group; after the analog memory cell programming reading from a second voltage level corresponding analog memory cells; and reconstruct data from the second voltage level.

[0091] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0091] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0092] 接口,其操作性地与包含多个模拟存储单元的存储器通信;以及 [0092] interfaces, operatively in communication with a memory comprising a plurality of analog memory means; and

[0093] 存储器信号处理器(MSP),其被耦合到所述接口并且被布置为:将数据作为相应的第一电压电平存储在一组模拟存储单元中;在存储所述数据之后,从所述组中的模拟存储单元读取第二电压电平,所述第二电压电平中的至少一些不同于所述相应的第一电压电平;估计读取自所述模拟存储单元中的第二电压电平中的失真度;以及当所估计的失真度违反了预定的失真判据时,将所述数据重新编程到所述组中的模拟存储单元中。 [0093] The signal processor memory (the MSP), which is coupled to the interface and arranged to: a first voltage corresponding to a data level stored in a set of analog memory cells; after storing the data, from in the group of analog memory unit reads a second voltage level, the second voltage level different from at least some of said corresponding first voltage level; estimates read from the analog memory unit distortion of the second voltage level; and when the estimated distortion violates a predetermined distortion criterion, the reprogramming data into the set of analog memory cells.

[0094] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0094] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0095] 接口,其操作性地与包含多个模拟存储单元的存储器通信;以及 [0095] interfaces, operatively in communication with a memory comprising a plurality of analog memory means; and

[0096] 存储器信号处理器(MSP),其被耦合到所述接口并且被布置为:将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,所述第二电压电平中的至少一些不同于所述相应的第一电压电平;识别潜在地导致针对读取自目标模拟存储单元的第二电压电平的失真的模拟存储单元的子集;估计在所述目标模拟存储单元被编程的第一瞬时由在所述子集中的模拟存储单元导致的针对所述目标模拟存储单元的第一失真度与所述目标模拟存储单元被读取的第二瞬时由在所述子集中的模拟存储单元导致的针对所述目标模拟存储单元的第二失真度之间的差;以及使用所估计的差,校正读取自所述目标模拟存储单元的第二电压电平。 [0096] The memory signal processor (MSP), which is coupled to the interface and arranged to: a first voltage corresponding to a data level stored in a set of analog memory cells of the memory; stored in the after the data, reads the corresponding second voltage level from said analog memory means, a second voltage level different from at least some of said corresponding first voltage level; for identifying potentially result read from target analog memory cell subset distortion analog memory cells a second voltage level; estimating said transient target in a first analog memory cell is programmed by results in the subset of analog memory means for the between the second distortion for the target instantaneous analog memory cells of the second target first distortion analog memory unit and the target analog memory cell is read by the analog memory cell subset resulting difference; and using the estimated difference correction reads the second target voltage level from the analog memory cells.

[0097] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0097] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0098] 接口,其操作性地与包含多个模拟存储单元的存储器通信;以及 [0098] interfaces, operatively in communication with a memory comprising a plurality of analog memory means; and

[0099] 存储器信号处理器(MSP),其被耦合到所述接口并且被布置为:将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平;估计交叉耦合系数,其通过处理所述第二电压电平而将所述模拟存储单元之间的交叉耦合干扰量化;以及使用所估计的交叉耦合系数,从所读取的第二电压电平重构存储在该组模拟存储单元中的数据。 [0099] The memory signal processor (MSP), which is coupled to the interface and arranged to: a first voltage corresponding to a data level stored in a set of analog memory cells of the memory; stored in the after the data read from the analog memory cells corresponding to a second voltage level, the second voltage level is affected by cross coupling of interference, which causes the cross-coupled interference is different from the second voltage level corresponding a first voltage level; cross coupling coefficient estimation, by processing the second voltage level to cross coupling interference between the quantized analog memory means; and using the estimated cross-coupling coefficients from the read a second voltage level data stored in the set of reconstructed analog memory cells.

[0100] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0100] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0101] 存储器,其包含多个模拟存储单元;以及 [0101] a memory, comprising a plurality of analog memory means; and

[0102] 存储器信号处理器(MSP),其被耦合到所述存储器并且被布置为:将数据作为选自可能的值的集合的相应的第一电压电平存储在一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平;处理所述第二电压电平以获得相应的硬判决,每个硬判决都对应于所述第一电压电平的可能的值中的相应值;估计交叉耦合系数,其基于所述第二电压电平和所述相应的硬判决,对所述模拟存储单元之间的交叉耦合干扰进行量化;以及使用所述交叉耦合系数,从所述第二电压电平重构存储在该组模拟存储单元中的数据。 [0102] The memory signal processor (MSP), which is coupled to the memory and arranged to: the selected data as possible values ​​corresponding first voltage level in a set of stored set of analog memory unit; after storing the data, reads the corresponding second voltage level from said analog memory unit, the second voltage level is affected by cross coupling of interference, the cross-coupling interference causes the second voltage level is different the respective first voltage level; processing the second voltage level to obtain the corresponding hard decision, each hard decision value may correspond to a respective value of said first voltage level in; estimating cross coupling coefficient based on said second voltage level and the respective hard decisions, of cross-coupled interference between the quantized analog memory unit; and using the cross-coupling coefficient, from the second voltage level the set of reconstructed data is stored in the analog memory cells.

[0103] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0103] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0104] 存储器,其包含多个模拟存储单元,其中所述存储单元的子集具有相关失真;以及 [0104] a memory, comprising a plurality of analog memory cells, wherein a subset of said memory cells having an associated distortion; and

[0105] 存储器信号处理器(MSP),其被耦合到所述存储器并且被布置为:将数据作为相应的第一电压电平存储在一组模拟存储单元中;在存储所述数据之后,从阵列的一列中的一个或多个模拟存储单元读取相应的第二电压电平,该第二电压电平由于失真而不同于所述第一电压电平;处理读取自所述一个或多个模拟存储单元的第二电压电平,以便估计在所述第二电压电平中的相应失真度;从所述列中的其他模拟存储单元读取一个第二电压电平;基于所估计的所述列中的一个或多个模拟存储单元的相应失真度,预测读取自所述其他模拟存储单元的第二电压电平中的失真度;使用所预测的失真度,校正读取自所述其他模拟存储单元的第二电压电平;以及基于所校正的第二电压电平,重构在所述其他模拟存储单元中存储的数据。 [0105] The signal processor memory (the MSP), which is coupled to the memory and arranged to: a first voltage corresponding to the data as stored in a set level of the analog memory unit; after storing the data, from an array of one or more respective analog memory unit reads a second voltage level, the second voltage level due to the distortion differs from the first voltage level; read from the one or more processing a second voltage level of the analog memory cell, in order to estimate the corresponding distortion level of the second voltage; a second voltage level read from the other analog memory cells in the column; based on the estimated distortion of the respective column or a plurality of analog memory cells, the read prediction distortion from the other analog memory cells in the second voltage level; using the predicted degree of distortion correction is read from the said second voltage level other analog memory unit; and a second voltage level based on the corrected reconstructed data stored in the other analog memory cells.

[0106] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0106] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0107] 存储器,其包含多个模拟存储单元;以及 [0107] a memory, comprising a plurality of analog memory means; and

[0108] 存储器信号处理器(MSP),其被耦合到所述存储器并且被布置为:将数据作为相应的第一电压电平存储在一组模拟存储单元中;在所述存储器中的第一模拟存储单元上执行存储器存取操作;响应于执行的存储器存取操作,从所述存储器中的第二模拟存储单元读取第二电压电平;处理所述第二电压电平,从而估计在所述第二电压电平中的扰动电平,该扰动电平是由在所述第一模拟存储单元上执行的存储器存取操作所导致;使用所估计的扰动电平,校正所述第二电压电平;以及基于所校正的第二电压电平,重构在所述第二模拟存储单元中存储的数据。 [0108] The memory signal processor (MSP), which is coupled to the memory and arranged to: a first voltage corresponding to the data as stored in a set level of the analog memory unit; a first in the memory the analog memory unit performs a memory access operation; in response to a memory access operation executed, reads the second voltage level from said second analog memory storage unit; processing the second voltage level, to estimate the the disturbance level of a second voltage level, the level of the disturbance is caused by the memory access operations performed on the first analog memory unit; using the estimated disturbance level, the second correction the voltage level; and a second voltage level based on the corrected reconstructed data stored in the second analog memory cells.

[0109] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0109] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0110] 存储器,其包含多个模拟存储单元;以及 [0110] a memory, comprising a plurality of analog memory means; and

[0111] 存储器信号处理器(MSP),其被耦合到所述存储器并且被布置为:将数据作为相应的第一电压电平存储在一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,所述第二电压电平中的至少一些不同于所述相应的第一电压电平;识别潜在地导致针对读取自目标模拟存储单元的第二电压电平的失真的模拟存储单元的子集;基于数据被存储在所述模拟存储单元中的相对时间和数据被存储在所述目标模拟存储单元中的时间之间的关系,将所述子集中的模拟存储单元分成多个类;为所述类的每一个估计由该类中的模拟存储单元针对所述目标模拟存储单元中的第二电压电平所导致的相应失真;使用为所述类中的一个或多个类中的每一个所估计的相应失真,校正读取自所述目标模拟存储单元的第二电压电平;以及基于所 [0111] The signal processor memory (the MSP), which is coupled to the memory and arranged to: a first voltage corresponding to the data as stored in a set level of the analog memory unit; after storing the data, from the analog memory unit reads a second voltage level corresponding to the second voltage level different from at least some of said corresponding first voltage level; identifying potentially cause a target for a read from the analog memory unit a subset of the analog memory unit distortion second voltage level; and the relative time-based data is data stored in the analog memory unit is stored a relationship between the target time of the analog memory unit, the the analog memory means into a plurality of classes in the subset; estimating distortion caused by the corresponding class in the analog memory cells for a second target voltage level of the analog memory unit resulting for each of said classes; using estimating distortion for the corresponding class in the class in one or more of each of a second correction read voltage level from the target analog memory unit; and based on the 正的第二电压电平,重构在所述目标模拟存储单元中存储的数据。 A second positive voltage level, reconstituted in the target data stored in the analog memory cells.

[0112] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0112] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0113] 存储器,其包含多个模拟存储单元;以及 [0113] a memory, comprising a plurality of analog memory means; and

[0114] 存储器信号处理器(MSP),其被耦合到所述存储器并且被布置为:接受用于存储在所述存储器中的数据;确定相应的第一电压电平,用于对一组模拟存储单元编程,从而使得所述模拟存储单元存储表示所述数据的物理量的相应值;使用所述第一电压电平对所述组中的模拟存储单元编程;在对所述模拟存储单元编程之后,从相应的模拟存储单元读取第二电压电平;并且从所述第二电压电平重构数据。 [0114] The signal processor memory (the MSP), which is coupled to the memory and arranged to: for receiving data stored in the memory; determining a respective first voltage level, a set of simulation value corresponding memory cell programming, so that the analog memory unit stores the data representing a physical quantity; using the first voltage level of the analog memory cell of the group; after the analog memory cell programming reading from a second voltage level corresponding analog memory cells; and reconstruct data from the second voltage level.

[0115] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0115] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0116] 存储器,其包含多个模拟存储单元;以及 [0116] a memory, comprising a plurality of analog memory means; and

[0117] 存储器信号处理器(MSP),其被耦合到所述存储器并且被布置为:将数据作为相应的第一电压电平存储在一组模拟存储单元中;在存储所述数据之后,从所述组中的模拟存储单元读取第二电压电平,所述第二电压电平中的至少一些不同于所述相应的第一电压电平;估计读取自所述模拟存储单元中的第二电压电平中的失真度;以及当所估计的失真度违反了预定的失真判据时,将所述数据重新编程到所述组的模拟存储单元中。 [0117] The signal processor memory (the MSP), which is coupled to the memory and arranged to: a first voltage corresponding to the data as stored in a set level of the analog memory unit; after storing the data, from in the group of analog memory unit reads a second voltage level, the second voltage level different from at least some of said corresponding first voltage level; estimates read from the analog memory unit distortion of the second voltage level; and when the estimated distortion violates a predetermined distortion criterion, the reprogramming data into the analog memory cell group.

[0118] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0118] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0119] 存储器,其包含多个模拟存储单元;以及 [0119] a memory, comprising a plurality of analog memory means; and

[0120] 存储器信号处理器(MSP),其被耦合到所述存储器并且被布置为:将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,所述第二电压电平中的至少一些不同于所述相应的第一电压电平;识别潜在地导致针对读取自目标模拟存储单元的第二电压电平的失真的模拟存储单元的子集;估计在所述目标模拟存储单元被编程的第一瞬时由在所述子集中的模拟存储单元导致的针对所述目标模拟存储单元的第一失真度与所述目标模拟存储单元被读取的第二瞬时由在所述子集中的模拟存储单元导致的针对所述目标模拟存储单元的第二失真度之间的差;以及使用所估计的差,校正读取自所述目标模拟存储单元的第二电压电平。 [0120] The memory signal processor (MSP), which is coupled to the memory and arranged to: a first voltage corresponding to a data level stored in a set of analog memory cells of the memory; stored in the after the data, reads the corresponding second voltage level from said analog memory means, a second voltage level different from at least some of said corresponding first voltage level; for identifying potentially result read from target analog memory cell subset distortion analog memory cells a second voltage level; estimating said transient target in a first analog memory cell is programmed by results in the subset of analog memory means for the between the second distortion for the target instantaneous analog memory cells of the second target first distortion analog memory unit and the target analog memory cell is read by the analog memory cell subset resulting difference; and using the estimated difference correction reads the second target voltage level from the analog memory cells.

[0121] 根据本发明的一个实施方案,还提供了一种数据存储装置,包括: [0121] According to one embodiment of the present invention, there is provided a data storage apparatus, comprising:

[0122] 存储器,其包含多个模拟存储单元;以及 [0122] a memory, comprising a plurality of analog memory means; and

[0123] 存储器信号处理器(MSP),其被耦合到所述存储器并且被布置为:将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平;估计交叉耦合系数,其通过处理所述第二电压电平而将所述模拟存储单元之间的交叉耦合干扰量化;以及使用所估计的交叉耦合系数,从所读取的第二电压电平重构存储在该组模拟存储单元中的数据。 [0123] The memory signal processor (MSP), which is coupled to the memory and arranged to: a first voltage corresponding to a data level stored in a set of analog memory cells of the memory; stored in the after the data read from the analog memory cells corresponding to a second voltage level, the second voltage level is affected by cross coupling of interference, which causes the cross-coupled interference is different from the second voltage level corresponding a first voltage level; cross coupling coefficient estimation, by processing the second voltage level to cross coupling interference between the quantized analog memory means; and using the estimated cross-coupling coefficients from the read a second voltage level data stored in the set of reconstructed analog memory cells.

[0124] 从下文对本发明的实施方案的详述,结合如下附图,将可更完整地理解本发明。 [0124] From the detailed description of embodiments of the invention below, in conjunction with the following drawings, the present invention may be more fully understood.

附图说明 BRIEF DESCRIPTION

[0125] 图I是示意性地示出了根据本发明的一个实施方案的用于存储器信号处理的系统的框图; [0125] FIG I schematically illustrates a block diagram of a memory of the signal processing system in accordance with one embodiment of the present invention;

[0126] 图2是示意性地示出了根据本发明的一个实施方案的存储单元阵列的示意图; [0126] FIG. 2 schematically shows a diagram illustrating the memory cell array according to an embodiment of the present invention;

[0127] 图3至图8是示意性地示出了根据本发明的实施方案的用于估计和消除存储单元阵列中的失真的方法的流程图,以及 [0127] Figures 3 to 8 schematically illustrates a flowchart of a method embodiment of the present invention for estimating the memory cell array and eliminating distortion, and

[0128] 图9是示意性地示出了根据本发明的实施方案的用于在存储单元阵列中刷新数据的方法的流程图。 [0128] FIG. 9 is a diagram schematically illustrates a flowchart of a method of refreshing data in the memory cell array according to an embodiment of the present invention.

具体实施方式 Detailed ways

[0129] 概述 [0129] Overview

[0130] 本发明的实施方案提供了用于估计和补偿在模拟存储单元中的失真的方法和系统。 [0130] Embodiments of the invention provide methods and systems for estimating and compensating distortion in the analog memory unit. 在下文描述的实施方案中,数据被存储为电荷电平,其被写入模拟存储单元阵列。 In the embodiments described below, data is stored as a charge level, which is written in the analog memory cell array. 电荷电平确定存储单元的相应的门限电压。 Determining charge level corresponding gate threshold voltage of the memory cell. 存储器信号处理器(MSP)从存储单元读取电压电平,并且自适应地估计包含在其中的失真度。 Memory signal processor (MSP) a read voltage level from the storage unit, and adaptively estimates the distortion contained therein. MSP通常产生所校正的电压,以此校正、消除抑或补偿失真。 MSP is usually a voltage corrected, thereby correcting, or whether to eliminate the distortion compensation. 使用所校正的电压重构存储在存储单元中的数据。 In the data storage unit using the voltage corrected reconstructed memory.

[0131 ] 本文描述了几种示例性的失真估计和消除方法。 [0131] Described herein are several exemplary distortion estimation and elimination. 一些方法是判决导向的,也即,使用硬判决分割过程的输出。 Some methods are decision-directed, i.e., using the hard decision output of the segmentation process. 在一些情况下,失真估计过程考虑的是,相对于被干扰存储单元被编程的时刻,潜在干扰存储单元被编程的时刻。 In some cases, the distortion estimation process is considered, with respect to disturbance of memory cells are programmed time, potentially interfering memory cell is programmed timing. 其他方法是基于位于存储单元阵列中的同一列(位线)中的其他存储单元的失真,来预测在某个存储单元中的失真。 Other methods are based on the distortion of other memory cells in the same column (bit line) in the memory cell array is located in, to predict distortion in a storage unit. 一些公开的方法校正了在失真形成时由阵列中的其他存储单元的操作所导致的扰动噪声。 Some of the disclosed method of correcting distortion when noise disturbance is formed by the operation of the other memory cell array caused.

[0132] 在一些实施方案中,使用编程和验证(P&V)过程对存储单元进行编程,且MSP对在编程时的失真做补偿,或者既对在编程时也对在读存储单元时的失真做补偿。 [0132] In some embodiments, a program and verify (P & V) the process of programming the memory cell, and MSP distortion when programmed to make compensation, or both of the programming also distortion when reading the memory cell to make compensation .

[0133] 作为对失真进行补偿的补充或替代,MSP可以响应于所估计的失真而执行其他种类的动作。 [0133] Additionally or alternatively to the distortion compensation, MSP action in response to the estimated perform other types of distortion. 例如,当所估计的失真超过最大的可容忍的失真度时,MSP可以刷新(即,重新编程)数据。 For example, when the estimated distortion exceeds the maximum degree of distortion can be tolerated, the MSP can be refreshed (i.e., reprogramming) data.

[0134] 本文所描述的失真估计和补偿方法可被用于以几种途径改进存储设备的数据存储性能。 [0134] described herein distortion estimation and compensation methods can be used in several ways to improve the performance of storage data storage device. 例如,可以降低当重构数据时达到的误差概率,可以增大可达到的存储容量,和/或可以延长可达到的数据保持期。 For example, the error probability can be reduced to achieve data when reconstructed, it can increase the storage capacity can be achieved, and / or may extend the achievable data retention period. 改进的性能可以接着用于降低存储设备的成本和复杂度和/或增大它们的编程速度。 Improved performance may then be used to reduce the cost and complexity of storage devices, and / or increase their speed of programming. 这些改进在对失真特别敏感的MLC设备中尤其重要。 These improvements are particularly important in the particularly sensitive to distortion MLC device. [0135] 系统描述 [0135] System Description

[0136] 图I是示意性地示出了根据本发明的一个实施方案的用于存储器信号处理的系统20的框图。 [0136] FIG. I is a schematic block diagram illustrating a memory 20 of the signal processing system according to an embodiment of the present invention. 系统20可用于不同的主机系统和设备中,例如用于计算设备、蜂窝电话或其他通信终端、可移除存储器模块(“U盘”设备)、数码相机、音乐和其他媒体播放器、和/或任何其他存储和取出数据的系统或设备。 The system 20 may be used for different host systems and devices, for example, computing devices, cellular phones or other communication terminals, removable memory module ( "U disk" apparatus), digital cameras, music and other media players, and / or any other system or device to store and retrieve data.

[0137] 系统20包括存储设备24,其将数据存储在存储单元阵列28中。 [0137] system 20 comprises, in the storage device 24 which stores data in the memory cell array 28. 存储阵列28包括多个模拟存储单元32。 An analog memory array 28 includes a plurality of memory cells 32. 在本专利申请的上下文中以及在权利要求书中,术语“模拟存储单元”用于描述保持诸如电压或电荷之类的物理参数的连续模拟值的任意的存储单元。 In the context of the present patent application and in the specification, the term "analog memory means" any claim for holding a memory cell is described as a continuous analog voltage value or a physical parameter of the charge or the like. 阵列28可以包括任何种类的模拟存储单元,举例而言,例如,NAND、N0R和CTF闪存单元、PCM、NR0M、FRAM、MRAM和DRAM单元。 Array 28 may include any type of analog memory cells, as, for example, NAND, N0R and CTF flash memory cells, PCM, NR0M, FRAM, MRAM and DRAM unit. 存储在存储单元中的电荷电平和/或写入与读出存储单元的模拟电压在本文中统称为模拟值。 Electric charge stored in the storage unit analog voltage levels and / or written into the memory cell is read collectively referred to herein as an analog value.

[0138] 用于存储在存储设备24中的数据被提供给所述设备并且缓存在数据缓冲器36中。 [0138] for data stored in the storage device 24 is provided to the device and the data buffer 36 in the buffer. 然后所述数据被转换成模拟电压并且使用读/写(R/W)单元40写入存储单元32中,该读/写单元40的功能将在下文中进一步详述。 The data is then converted into an analog voltage and a read / write (R / W) unit 40 writes the storage unit 32, the read / write unit 40 will be described in further detail below. 当从阵列28读出数据时,读/写单元40将电荷以及由此的存储单元32的模拟电压转换成数字样本。 When the data is read from the array 28, the read / write unit 40 converts the analog voltage of the charge and a storage unit 32, thereby converted into digital samples. 每个数字样本具有一个或多个比特的分辨率。 Each digital sample having one or more bits of resolution. 这些样本被缓存在缓冲器36中。 These samples are buffered in the buffer 36. 存储设备24的操作和时序均由控制逻辑48所管理。 And timing the operation of the storage device 24 by control logic 48 managed.

[0139] 数据进出存储设备24的存储和取出,由存储器信号处理器(MSP) 52执行。 [0139] Data storage device and taken out of the storage 24, executed by the signal processor memory (MSP) 52. 如下文将详示,MSP 52使用新颖的方法,以用于估计和降低在存储单元阵列28中的各种不同的失 As will be shown in detail, MSP 52 using a novel method for estimating and reducing the variety in the memory cell array 28 is different from the loss

真效应。 Real effect.

[0140] 在一些实施方案中,MSP 52包括编码器/解码器64,该编码器/解码器64使用ECC对将要写到设备24的数据进行编码,而当把数据从设备24读出时对所述ECC进行解码。 [0140] In some embodiments, MSP 52 includes an encoder / decoder 64, the encoder / decoder 64 using an ECC for data to be written device 24 is encoded, while when the read data from the device 24 the ECC decoding. 信号处理单元60处理被写入设备24和从设备24取出的数据。 The signal processing unit 60 and processing device 24 is written to the data extracted from the device 24. 具体地,信号处理单元60估计对从存储单元32读出的电压有影响的失真。 Specifically, the signal processing unit 60 estimates a voltage of 32 read out from the memory cell affecting distortion. 信号处理单元60可以补偿抑或减少所估计的失真的效应。 The signal processing unit 60 may compensate for distortion effects and is decreasing estimated. 替代地,信号处理单元60可以基于所估计的失真而采取其他种类的行动,在下文将详述。 Alternatively, the signal processing unit 60 may take other actions based on the estimated kind of distortion will hereinafter be described in detail.

[0141] MSP 52包括数据缓冲器72,该数据缓冲器72由信号处理单元60用于存储数据以及用于与存储设备24交互。 [0141] MSP 52 includes a data buffer 72, the data buffer 72 by the signal processing unit 60 for storing data and for interacting with a storage device 24. MSP 52还包括输入/输出(I/O)缓冲器56,该输入/输出(I/O)缓冲器56在所述MSP和所述主机之间形成接口。 MSP 52 is further includes an input / output (I / O) buffer 56, the input / output (I / O) buffer 56 form an interface between the host and the MSP. 控制器76管理MSP 52的操作和定时。 A timing controller 76 and the operation management of MSP 52. 信号处理单元60和控制器76可以用硬件实现。 The signal processing unit 60 and the controller 76 may be implemented in hardware. 替代地,信号处理单元60和/或控制器76可以包括运行合适的软件的微处理器,或者硬件和软件元素的组合。 Alternatively, the signal processing unit 60 and / or controller 76 may comprise a microprocessor running suitable software, or a combination of hardware and software elements.

[0142] 图I中的配置是示例性的系统配置,其纯粹是为概念清楚而示出的。 [0142] Figure I is an exemplary configuration of the system configuration, which is purely conceptual clarity shown. 也可以使用任意其他合适的配置。 You may also be used any other suitable configuration. 为清楚起见,对于理解本发明的原理并非必要的元件,例如各种接口、寻址电路、定时和定序电路、数据置乱电路和调试电路,均从附图中省略。 For clarity, for an understanding of the principles of the present invention is not necessary elements, such as various interfaces, addressing circuits, timing and sequencing circuit, a data scrambling circuit and the debugging circuit are omitted from the drawings. [0143] 在图I中所示的示例性系统配置中,存储设备24和MSP 52被实现为两个单独的集成电路(1C)。 An exemplary system configuration shown in FIG. I, [0143], the MSP 52 and the storage device 24 is realized as two separate integrated circuits (1C). 然而,在替代的实施方案中,所述存储设备和MSP可被集成在单一IC中或片上系统(SoC)中。 However, in an alternative embodiment, the storage device and the MSP may be integrated in a single IC or the system-on-chip (SoC). 在一些实施方式中,单个MSP 52可被连接到多个存储设备24。 In some embodiments, the single MSP 52 may be connected to a plurality of storage device 24. 进一步作为替代,MSP 52的某些或全部功能可以用软件实现,并且由主机系统的处理器或其他元件来执行。 As a further alternative, some or all of the functions of the MSP 52 can be implemented in software and executed by a processor, or other components of the host system. 实现系统20的某些实施方案的另外的架构性的方面,在上文所引用的美国临时专利申请60/867,399中,并且在以援引方式全部纳入本文中的提交于2007年5月10日的题为uCombinedDistortion Estimation and Error Correction Coding for MemoryDevices,,的PCT专利申请中,得以更详细地描述。 Further aspects of the architectural implementation of certain embodiments of the system 20, and in U.S. Provisional Patent Application cited above 60 / 867,399, and filed on May 10, 2007 incorporated in its entirety herein by invoking the PCT Patent application entitled uCombinedDistortion Estimation and Error Correction Coding for MemoryDevices ,, the day, is described in more detail.

[0144] 在典型的写操作中,从主机接收待要写入存储设备24的数据,并将所述数据缓存在I/o缓冲器56中。 [0144] In a typical write operation, the data to be received from the host computer 24 to be written to the storage device and the data buffer in I / o buffer 56. 编码器/解码器64编码所述数据,且所编码的数据通过数据缓冲器72传送到存储设备24。 64 encoding the encoder / decoder data, and the encoded data transmitted by the data buffer 72 to the storage device 24. 在将数据传送到存储设备用于编程之前,MSP 52可以预处理该数据。 Before transferring data to storage devices for programming, MSP 52 may be preprocessed data. 在设备24中,数据临时存储在缓冲器36中。 In the device 24, 36 is temporarily stored in the data buffer. 读/写单元40将数据转换成模拟电压值,并且将数据写入阵列28的适当的存储单元32中。 Read / write unit 40 converts the data into an analog voltage value, and the data is written to the appropriate memory cell 32 in array 28. [0145] 在典型的读操作中,读/写单元40从适当的存储单元32读出模拟电压值并且将所述电压转换为软数字样本。 [0145] In a typical read operation, read / write 40 means 32 reads the analog voltage value from a suitable storage unit and converting the voltage to a digital soft samples. 所述样本被缓存在缓冲器36中,并且传送到MSP 52的缓冲器72。 The samples are buffered in the buffer 36, MSP 52 and transferred to the buffer 72. 在一些实施方案中,MSP 52的信号处理单元60将电压样本转换为数据位。 In some embodiments, the signal processing unit 60 MSP 52 converts the voltage sample of data bits. 如上所述,可能的门限电压的范围被分为两个或更多个区域,其中每个区域表示一个或多个数据位的某一组合。 As described above, the range of possible threshold voltages is divided into two or more regions, where each region represents a combination of one or more data bits. 当读取存储单元时,信号处理单元60典型地将读取的电压样本的幅度与一组判决门限相比较,以便确定读取的电压所落入的区域,且从而确定存储在存储单元中的数据位。 When reading the memory cell, the signal processing unit 60 is typically an amplitude of the read sample voltage with a set of decision threshold is compared to determine the area of ​​the read voltage falls, and in the storage unit to determine the data bits. 数据块从缓冲器72传送到信号处理单元60,而编码器/解码器64对这些块的ECC进行解码。 Block transfer of data from buffer 72 to the signal processing unit 60, the encoder / decoder 64 pairs of ECC blocks is decoded. 已解码的数据通过1/0缓冲器56传送到主机。 It decoded data to the host through the buffer 56 1/0. 在一些实施方案中,ECC解码器包括软解码器,而信号处理单元60将电压样本转换成用于解码ECC的软解码度量。 In some embodiments, ECC decoder comprises a soft decoder, the signal processing unit 60 converts the voltage sample to a soft decoder for decoding the ECC metric.

[0146] 另外,信号处理单元60使用下文描述的方法估计在所读取的样本中存在的失真。 [0146] Further, the signal processing unit 60 uses the estimating method described below is present in the sample the read distortion. 在一些实施方案中,MSP 52在数据被写入存储单元之前将其置乱,并且将从存储单元读取的数据反置乱,以便改进失真估计的性能。 In some embodiments, MSP 52 before the data is written to the memory cell scrambling, and data read from the memory cell anti-scrambling, in order to improve distortion estimation performance.

[0147] 存储阵列结构和失真机制 [0147] memory array structures and distortion mechanisms

[0148] 图2是示意性地示出了根据本发明的一个实施方案的存储单元阵列28的示意图。 [0148] FIG. 2 is a schematic showing a schematic memory cell array 28 in accordance with an embodiment of the present invention. 虽然图2涉及连接在特定阵列配置中的闪存单元,但本发明的原理也可应用于其他类型的存储单元和其他阵列配置。 Although FIG. 2 relates to flash memory cells connected to a particular array configuration, but the principles of the present invention can also be applied to other types of memory cell arrays and other configurations. 在上文背景技术部分中所引用的参考文献中,描述了一些示例性的存储单元类型和阵列配置。 References in the Background section above are cited, we describe some exemplary storage array unit type and configuration.

[0149] 阵列28的存储单元32被布置在具有多个行和多个列的栅格中。 The storage unit [0149] 32 of array 28 are arranged in a grid having a plurality of rows and columns. 每个存储单元32包括浮置栅极金属氧化物半导体(MOS)晶体管。 Each memory cell 32 includes a floating gate metal-oxide-semiconductor (MOS) transistors. 通过向晶体管的栅极、源极和漏极施加适当的电压电平,可以将一定数量的电荷(电子或空穴)存储在一特定的存储单元中。 Through the gate of the transistor, the source and drain application of an appropriate voltage level, a certain amount of charge (electrons or holes) may be stored in a particular storage unit. 存储在所述存储单元中的值可通过测量所述存储单元的门限电压来读取,所述门限电压被定义为使所述晶体管导通而需要向所述晶体管的栅极施加的最小电压。 Values ​​stored in the storage unit can be read by measuring the threshold voltage of the memory cell, the threshold voltage is defined as the minimum voltage that the transistor needs to be applied to the gate of the transistor. 所读取的门限电压与存储在所述存储单元中的电荷成比例。 Threshold voltage proportional to the charge stored in the read storage unit.

[0150] 在图2的示例性配置中,每一行中的晶体管的栅极由字线80连接。 [0150] In the exemplary configuration of FIG. 2, the gates of the transistors in each row are connected by the word line 80. 每一列中的晶体管的源极由位线84连接。 The source of the transistor in each column is connected by a bit line 84. 在一些实施方案中,例如在一些NOR单元设备中,源极直接连接到位线。 In some embodiments, for example, in some NOR cell devices, a source directly connected to the bit line. 在替代的实施方案中,例如在一些NAND单元设备中,位线被连接到多串浮置栅极单元。 In an alternative embodiment, for example in some equipment NAND cell, the bit line is connected to strings of floating gate cells.

[0151] 通常,读/写单元40,通过将变化的电压电平施加到特定的存储单元32的栅极(也即,施加到所述存储单元所连接到的字线),并且检查所述存储单元的漏极电流是否超过了某一门限(也即,所述晶体管是否导通),来读取该特定的存储单元32的门限电压。 [0151] Generally, the read / write unit 40, applied to the gate (i.e., is applied to the memory cells connected to the word line) of a particular storage unit 32 by voltage level change, and examining the the drain current of the memory cell exceeds a certain threshold (i.e., whether the transistor is turned on), the particular read gate threshold voltage of memory cell 32. 读/写单元40通常向所述存储单元所连接到的字线施加一系列的不同的电压值,并且确定为使漏极电流超过所述门限的最低栅极电压值。 Read / write unit 40 commonly connected to the word line to the memory cell applies a series of different voltage values, and determines the minimum value of the gate voltage is the drain current exceeds the threshold. 通常,读/写单元40同时读取一整行的存储单元,这一整行的存储单元也被称为页。 Typically, the read / write unit 40 reads the storage unit while a full row, the entire row of memory cells is also called a page.

[0152] 在一些实施方案中,读/写单元40通过将所述存储单元的位线预充电到某一电压电平来测量漏极电流。 [0152] In some embodiments, the read / write unit 40 via the bit line of the memory cell is precharged to a voltage level of the drain current is measured. 一旦栅极电压被设定到期望值,漏极电流就使得位线电压经存储单元放电。 Once the gate voltage is set to a desired value, the drain current is such that the memory cell via the bit line voltage discharge. 在施加栅极电压之后的几毫秒,读/写单元40测量位线电压,并且将位线电压与门限进行比较。 In a few milliseconds after the gate voltage is applied, the read / write bit line voltage measuring unit 40, and the bit line voltage is compared with a threshold. 在一些实施方案中,每个位线84被连接到相应的读出放大器,该读出放大器将位线电流放大并且将该电流转换为电压。 In some embodiments, each bit line 84 is connected to the corresponding sense amplifier, the sense amplifier amplifies the bit line current and the current into a voltage. 使用比较器将被放大的电压与门限进行比较。 Using a comparator to be amplified voltage is compared with a threshold.

[0153] 上文所描述的电压读取方法是一种示例性方法。 [0153] voltage reading method described above is an exemplary method. 作为替代,读/写单元40可以使用任何其他适合的方法来用于读取存储单元32的门限电压。 Alternatively, the read / write unit 40 may use any other suitable method for reading gate threshold voltage of the memory cell 32. 例如,读/写单元40可以包括一个或多个模数转换器(ADC),该模数转换器将位线电压转换成数字样本。 For example, read / write unit 40 may include one or more analog to digital converters (the ADC), the analog to digital converter converts the digital samples into a bit line voltage.

[0154] 存储单元阵列通常被分为多个页,也即,多组同时编程和读取的存储单元。 [0154] The memory cell array is generally divided into a plurality of pages, i.e., groups of memory cells simultaneously programmed and read. 在一些实施方案中,每个页包括阵列的一整行。 In some embodiments, each page comprising an array of the whole line. 在替代性的实施方案中,每个行可被分为两个或更多个页。 In alternative embodiments, each row may be divided into two or more pages. 对存储单元的擦除通常在包含多个页的块中执行。 Erased memory cell generally comprising a plurality of pages is performed in the block. 典型的存储设备可以包括数千个擦除块。 Typical storage devices may include thousands of erase blocks. 尽管也可以使用其它块尺寸,典型的擦除块是128页的数量级,每个擦除块包括数千个存储单元。 Although other block sizes may be used, typically of the order of erase blocks 128, each erase block includes thousands of memory cells.

[0155] 存储在存储单元中的电荷电平和读取自存储单元的电压可能包含多种类型的失真,这些失真是由阵列28中的不同的失真机制所导致的。 [0155] of charge in the storage unit is read from the voltage level and the memory cell may comprise a plurality of types of distortion, such distortions by the array of 28 different distortion caused mechanisms. 一些失真机制影响了存储在存储单元中的实际电荷,而其他机制使得所读出的电压失真。 Some distortion mechanisms affect the actual charge stored in the storage unit, while other mechanisms such that the readout voltage distortion. 例如,阵列中的相邻存储单元之间的电交叉耦合会修改特定存储单元中的门限电压。 For example, the electrical cross-coupling will be between adjacent memory cells in the array to modify certain memory cell threshold voltage. 此效应被称为交叉耦合失真。 This effect is called cross-coupled distortion. 又例如,电荷会随着时间的推移而从存储单元中泄漏。 As another example, the charge may leak from the storage unit over time. 这种老化效应的结果是,所述存储单元的门限电压将随着时间的推移而从最初写入的值漂移。 The result of this aging effect, the threshold voltage of the memory cell will drift over time from the value originally written to.

[0156] 另一种类的失真,通常被称为扰动噪声,是由阵列中的某些存储单元上的存储器存取操作(例如,读、写或擦除操作)而导致的,这引起了对其他存储单元中的非预期的电荷改变。 [0156] Another type of distortion, commonly referred to disturbing noise, is access operation (e.g., read, write or erase operation) on some memory by the memory cell array caused, which causes the pair of unintended change in charge of the other storage units. 作为又一实例,可以由相邻存储单元(例如在同一NAND存储单元串中的其他存储单元)中的电荷,通过一种称为背景图案相关性(BH))的效应,来影响特定存储单元的源极_漏极电流。 As yet another example, adjacent memory cells may be formed (e.g., other memory cells in the same memory cell NAND string) in the charge, by means of a correlation called a background pattern (BH)) effects, to affect a specific memory cell _ a source drain current.

[0157] 失真估计和消除方法 [0157] and eliminate distortion estimation method

[0158] 存储单元32中的失真降低了存储设备的性能,例如重构数据时的误差概率、可达到的存储容量以及可达到的数据保持期。 The [0158] storage unit 32 to reduce the distortion performance of the storage device, for example, the reconstruction error probability data storage capacity can be achieved and the data retention period can be achieved. 性能降低在MLC设备中尤其严重,因为在MLC设备中表示数据的不同电压电平之间的差相对较小。 Performance degradation is particularly serious in the MLC devices, as represented by a difference between the different voltage levels of the data is relatively small in the MLC device. 在许多情况下,失真度随着时间的推移而变化,且在一个存储单元和另一个存储单元之间也有所不同。 In many cases, the distortion varies over time, and may also vary between a storage unit and other storage units. 从而,以自适应的方式估计失真并且基于所估计的失真采取行动是很有好处的。 Thus, in an adaptive manner is estimated based on the estimated distortion and distortion action is very good.

[0159] MSP 52可以采用各种不同的方法来估计存储单元32中的失真,并且使用所估计的失真度来消除或补偿失真。 [0159] MSP 52 Various methods may be employed to estimate the distortion in the storage unit 32, and using the estimated distortion to eliminate or compensate for the distortion. 作为对失真进行补偿的补充或替代,MSP可以基于所估计的失真执行其他种类的动作。 As a complement to compensate for distortion or alternative, MSP can perform other types of action based on the estimated distortion.

[0160] 例如,MSP可以使用所估计的失真来执行数据刷新判决。 [0160] For example, MSP can be performed using the data refresh judgment the estimated distortion. 在一种典型的实现中,MSP估计各个不同的存储单元组(例如存储页)的失真度。 In a typical implementation, MSP various estimates of memory cell groups (e.g., memory pages) distortion. 当在一特定页中的失真超过某一可容忍的门限时,MSP对数据进行刷新(也即,重新编程)。 When the distortion in a particular page more than a tolerable threshold, MSP data is refreshed (ie, reprogrammed).

[0161] 又例如,MSP可以使用所估计的失真来评估在某一存储单元或某组存储单元中的可达到的存储容量。 [0161] As another example, MSP can be used to evaluate the distortion of the estimated storage capacity of a storage unit or a group of memory cells that can be achieved. 基于可达到的容量,MSP可以修改用于在相应的存储单元中存储数据的电压电平的数量和/或ECC。 Based on the achievable capacity, MSP can be used to modify the voltage level in the storage unit corresponding to the amount of data and / or ECC. 从而,MSP可以自适应地修改存储单元中存储数据的密度,以匹配它们的存储容量,因为它们的存储容量随着时间的推移而改变。 Thus, the MSP can be adaptively modify the density of data storage unit, to match their storage capacity because of their storage capacity varies over time. 使用失真估计用于适配存储设备的存储密度的一些方面在提交于2007年5月10日的题为“Memory Devicewith Adaptive Capacity”的PCT专利申请中得以描述,该文献以援引方式全部纳入本文。 Use distortion estimation for some aspects of the storage density of the storage device to the adapter described in PCT patent application filed on May 10, 2007, entitled "Memory Devicewith Adaptive Capacity" in the literature cited to totally incorporated herein by reference.

[0162] 再例如,MSP可以基于所估计的失真而修改判决门限,也即将存储单元的可能的电压的范围分成判决区域的门限。 [0162] As another example, the MSP decision threshold may be modified based on the estimated distortion, is about the range of possible voltage of the memory cell area is divided into a threshold decision. MSP可以调整判决门限值以最小化失真度,以最小化解码误差概率或满足任何其他适合的性能条件。 MSP can adjust the decision threshold to minimize distortion, to minimize decoding error probability or to meet any other suitable performance condition. MSP也可以修改ECC解码度量,例如对数似然比(LLR),该解码度量由ECC解码器使用以解码ECC。 MSP ECC decoding metric may be modified, for example, the likelihood ratio (the LLR), the decoding metric used to decode the number of ECC by the ECC decoder. 这样的方法例如在上文所引用的PCT申请“Combined Distortion Estimation and ErrorCorrection Coding for Memory Devices,,中得以描述。 Such a method, for example, in the above-cited PCT application of "Combined Distortion Estimation and ErrorCorrection Coding for Memory Devices ,, been described in.

[0163] 图3至8是示意性地示出了根据本发明的实施方案的用于估计和消除存储单元阵列28中的失真的方法的流程图。 Flowchart of a method [0163] Figures 3 to 8 is a schematic for illustrating a memory cell array to estimate and cancel the distortion 28 according to an embodiment of the present invention. 在下文的说明中,假设MSP逐页地读取存储单元并估计失真度。 In the following description, it is assumed MSP memory cell is read page by page and estimate distortion. 然而,在替代性的实施方案中,MSP可以读取并处理任意其他存储单元组。 However, in an alternative embodiment of, the MSP can read and process any other memory cell groups. 例如,MSP可以处理整个擦除块或甚至单独的存储单元。 For example, MSP can handle the entire erase block, or even a single memory cell.

[0164] 图3是示意性地示出了根据本发明的一个实施方案的一种用于估计和消除交叉耦合失真的方法的流程图。 [0164] FIG. 3 is a schematic flow chart illustrating a method for estimating and canceling the cross-coupled distortion according to one embodiment of the present invention. 在一些情况下,例如在闪存中,交叉耦合失真是由存储在邻近存储单元的电荷产生的电场的电磁耦合所导致的。 In some cases, for example in the flash memory, the cross-coupled distortion by electromagnetic field coupling is generated in the charge stored in adjacent memory cells caused. 在其他情况下,例如在NROM存储单元中,交叉耦合失真可由其他原因导致,例如由于共享地线导致的存储单元的源电压的上升。 In other cases, for example NROM memory cell, the cross-coupled distortion by other causes, for example, increased source voltage of the memory cell because the shared ground lead.

[0165] 读取自受交叉耦合影响的某一存储单元i的电压一般可写为: [0165] Since the read voltage of a memory cell i is generally affected by the cross-coupling can be written as:

[0166] Vi = g(CiKf (Ci, Ci) [0166] Vi = g (CiKf (Ci, Ci)

[0167] 其中g(Ci)表示当所有潜在干扰存储单元均被擦除时从所述存储单元读取的电压,Ci表示在存储单元i中的电荷电平,f (C17C1)表示当存储单元电荷是Ci时的稱合效应,而Ci表示相邻存储单元的电荷电平的集合,j ^ io [0167] where g (Ci) represents the potential interference when all memory cells are erased from the memory cell read voltage, Ci represents the charge level of the memory cell i, f (C17C1) indicates when the memory cell said charge is combined effect during Ci, Ci represents the set charge levels of adjacent memory cells, j ^ io

[0168] 在一些实际情况下,交叉耦合可以用线性函数来建模,以使得 [0168] In some practical cases, cross-coupling may be modeled by a linear function, such that

[0169] + [0169] +

[0170] 其中I^i表示交叉耦合系数,也即,从存储单元j到存储单元i的交叉耦合幅度。 [0170] where I ^ i represents cross coupling coefficient, i.e., j from the storage unit to the amplitude of the cross-coupled memory cell i. 系数值有时可以取决于存储单元的电荷电平。 Coefficient values ​​may sometimes depend on the charge level of the memory cell.

[0171] 在其他情况下,由某一干扰存储单元导致的交叉耦合既取决于干扰存储单元的电荷电平,也取决于被干扰存储单元的电荷电平。 [0171] In other cases, the cross-coupled memory cells by some interference caused by the interference depends both on the level of charge storage units, also depend on the charge level of the memory cell is disturbed. 在这些情况下,公式[2]可被写为 In these cases, the formula [2] can be written as

[0172] Vi = k0 · Ci+f ({ci; CjI, j 幸i) [0172] Vi = k0 · Ci + f ({ci; CjI, j Fortunately i)

[0173] 交叉耦合系数值通常可以从一个单元到另一个单元而变化,也可以随着温度、电源电压和其他条件的变化而变化。 [0173] Cross-coupling coefficient value may generally vary from one cell to another, may vary with temperature, supply voltage, and other conditions. [0174] 在读取步骤90,图3的方法始于MSP 52从一存储单元页读取电压。 [0174] In the read step 90, the method of Figure 3 begins with MSP 52 from a memory cell read voltage page. 每个读取电压由软样本所表示,也即具有两个或更多个位的分辨率的数字化值。 Each read voltage is represented by a soft sample, i.e. digitized values ​​having two or more bits of resolution. 所述MSP从读取的电压值生成硬判决。 The voltage generated by the MSP value from the hard decision read. 换句话说,所述MSP逐个存储单元确定最有可能已被写到存储单元中的标称电压电平。 In other words, the storage unit one by MSP to determine the most likely to have been written to the nominal voltage level of the memory cell. MSP可以将每个读取电压和表示不同比特组合的不同标称电压值作比较,并且确定最接近于读取电压的标称电压电平。 MSP can be read compare voltages each representing a different nominal voltage values ​​different bit combinations, and determine the closest to the nominal voltage level of the read voltage. 这种操作通常称为硬分割。 This operation is commonly referred to as hard segmentation.

[0175] 在系数估计步骤94, MSP基于读取的电压样本并基于对应的硬判决,估计交叉耦合系数。 [0175] In step 94 the estimated coefficient, the MSP cross coupling coefficient based on the read sample voltage corresponding to a hard decision based on estimated. 在大多数实际情况下,大多数硬判决反映了写入存储单元的正确比特组合,只有很少的硬判决是错误的。 In most practical cases, most of the hard decision reflects the correct combination of bits written in the memory cell, only a few hard decisions is wrong. 虽然硬判决的错误概率不足以用于可靠地重构数据,但其通常足以用于可靠地估计系数。 Although the hard decision error probability is insufficient for reliably reconstruct the data, but it is usually sufficient to reliably estimate coefficients.

[0176] MSP可以使用任何适当的估计方法用于估计交叉耦合系数的值。 [0176] MSP may use any suitable estimation method for estimating the value of the cross coupling coefficients. 在许多实际情况下,耦合系数值在整个已处理的存储单元组中基本恒定。 In many practical cases, the coupling coefficient value substantially constant in the entire memory cell groups have been processed. 在这些情况下,MSP可以使用本领域公知的各种不同的块估计技术,这些块估计技术使用软电压样本的整个集合和对应的硬判决来估计交叉耦合系数。 In these cases, the MSP known in the art may be used in a variety of estimation techniques blocks, these blocks using the hard decision estimation techniques entire set of soft voltage samples and corresponding cross coupling coefficient estimates.

[0177] 替代地,所述MSP可以使用本领域公知的各种不同的循序估计方法,其循序地(例如逐个样本地)处理电压样本和硬判决,并且收敛成交叉耦合系数的期望值。 [0177] Alternatively, the MSP known in the art may be used in various sequential estimation method, which sequentially (e.g., sample by sample, ground) voltage samples and hard decision processing, and converges in a cross coupling coefficient expectations. 循序估计方法可以包括,例如最小均方(LMS)过程、递归最小二乘(RLS)过程、Kalman过滤过程或者任何其他适合的过程。 Sequential estimation method may comprise, for example, a least mean square (LMS) process, Recursive Least Squares (RLS) process, Kalman filter process, or any other suitable process.

[0178] 在一些实施方案下,估计过程试图减少在读取电压和对应的硬判决之间的距离度量(例如欧几里得距离)。 [0178] In some embodiments, the process attempts to reduce the estimated distance metric (e.g., Euclidean distance) between the read voltage and a corresponding hard decision.

[0179] 例如,当使用LMS过程时,MSP可以迭代地估算下述表达式 [0179] For example, when the LMS process, the MSP can be estimated iteratively by the following expression

[0180] - k(^ + μ. v(/) · e(0 [0180] - k (^ + μ v (/) · e (0.

J1 J1 J 1 J1 J1 J 1

[0181] 其中t表示根据已处理的样本和硬判决而递增的增量指数(例如,样本指数)。 [0181] where t represents a hard decision based on a sample processed and incremented index increment (e.g., sample index). 表示在第t次迭代的交叉耦合系数I^i的估计值。 It represents the estimated value of the cross coupling coefficient t-th iteration of the I ^ i. μ表示预定义的迭代步长,Vj(t)表 μ represents a predefined iterative step, Vj (t) table

示在第t次迭代读取自存储单元j的电压样本。 Illustrates iterative read voltage samples from the storage element j at the time t. ei(t)被定义为ef) = - ,也即,第t次迭代的读取电压和对应的硬判决(标称电压)的差。 EI (t) is defined as ef) = -, i.e., the t-th iteration of the read voltage and a corresponding hard decision (nominal voltage) difference. 注意,不同于上述公式[2]中交 Note that, unlike the above-described formula [2] in cross

叉耦合系数与存储单元的电荷电平相乘,公式[4]中交叉耦合系数与存储单元电压相乘。 Charge level of the memory cell cross coupling coefficient multiplied by the formula [4] in the cross-coupling coefficient is multiplied by the memory cell voltage.

[0182] 在一些实施方案中,在对存储单元编程期间,可以通过测量由对存储单元j编程而在存储单元电压Vi中导致的变化,来估计h的值。 [0182] In some embodiments, the memory cell during programming, the memory cell changes caused j programmed in the memory cell voltage Vi, the estimated by measuring the value of h.

[0183] 在交叉耦合补偿步骤98,MSP基于所估计的交叉耦合系数补偿读取电压中的交叉耦合失真。 [0183] In the cross-coupling compensation step 98, MSP cross-coupled read voltage based on the estimated distortion compensation coefficient cross coupling. MSP通常产生校正的电压,其中交叉耦合失真度被降低。 MSP typically produce a corrected voltage, wherein the cross-coupling distortion is reduced. 例如,MSP可以将所估计的交叉耦合失真分量求和,并且从存储单元电压中减去该和,所述交叉耦合失真分量源自不同的干扰存储单元并且影响某一读取电压。 For example, the MSP can be estimated cross-coupled distortion component summed and subtracted from the storage unit and the voltage, the cross-coupled distortion component derived from a different storage unit and the interference impact of a read voltage. 这种操作有时称为线性均衡。 Such operations are sometimes referred to as a linear equalizer.

[0184] 如本领域所公知,MSP可以替代地通过施加判决反馈均衡(DFE)来消除交叉耦合失真。 [0184] As is known in the art, MSP can alternatively be eliminated by application of the cross-coupled distortion decision feedback equalization (DFE). 在替代性的实施方案中,所述MSP可以使用减少状态最大似然序列估计(MLSE)过程,例如使用众所周知的Viterbi算法,来消除交叉稱合失真。 In an alternative embodiment, the MSP can be used to reduce the state of the maximum likelihood sequence estimation (the MLSE) process, for example using the well-known Viterbi algorithm to eliminate crossover distortion, said engagement. 此外作为替代,所述MSP可以使用最大后验(MAP)估计过程或任何其他适合的方法以基于所估计的交叉耦合系数来补偿交叉耦合失真。 Further alternatively, the MSP can use the maximum a posteriori (MAP) process, or any other suitable method for estimating cross coupling coefficient based on the estimated cross-coupling distortion compensation.

[0185] 所述MSP使用校正的电压来重构存储单元中存储的数据。 [0185] The MSP using the corrected voltage to reconstruct the data storage unit. 在一些实施方案中,所述MSP分两步处理读取的电压(也即,两次扫描读取的电压值)。 In some embodiments, the two-step process MSP voltage (i.e., voltage value of the scanning reading of two) read. 在第一步,MSP估计交叉耦合系数。 In the first step, MSP estimated cross-coupling coefficients. 在第二步,MSP使用所估计的系数来校正读取电压并且重构数据。 In a second step coefficient, MSP using the estimated read voltage and correcting the reconstructed data. 两步处理可以是有利的,举例而言,例如由于在不同温度、电源电压或其他条件下写存储单元,而存储单元的不同的块或页具有不同的交叉耦合系数值时。 Two-step process may be advantageous, for example, for example, since the write memory cell at a different temperature, supply voltage, or other conditions, the different blocks or pages of memory cells having different cross-coupling coefficient values ​​of time. 在替代性的实施方案中,MSP可以在一步之内执行系数估计、失真补偿和数据重构。 In an alternative embodiment of, the MSP can be performed in one step the coefficient estimation, data reconstruction and distortion compensation.

[0186] 在一个替代性的实施方案中,MSP起初在一步之内执行系数估计和数据重构。 [0186] In an alternative embodiment of the embodiment, MSP initial estimation and data reconstruction in the step of performing coefficient. 然后MSP估计重构的数据的质量(例如通过检测未被ECC校正的错误),并且若数据重构质量过低则执行第二步。 Mass (e.g., by detecting a non-ECC correction error) is then estimated MSP reconstructed data and the reconstructed data if the quality is too low, the second step. 这种技术不会显著地改变平均的处理时延或处理功率,在系数随着时间的推移而改变的情况下是有利的。 This technique does not significantly alter the average processing delay of processing power or, in the case where the coefficient changes with time is advantageous.

[0187] 如上所述,在一些实施方案中,MSP在将数据写到存储单元之前将数据置乱,以便防止非随机数据使估计精确度降低。 [0187] As described above, in some embodiments, the MSP before writing data to the data storage unit scrambling, in order to prevent non-random data that the estimating accuracy. · ·

[0188] 在一些失真机制中,特定存储单元中的失真度和沿同一位线而处的其他存储单元的失真度是相关的。 [0188] In some mechanism distortion, the distortion of the particular memory cell and another memory cell along the same bit line and at the degree of distortion is related. 例如,在一些NAND闪存中,沿着每条位线的存储单元彼此相连构成十六个或三十二个存储单元组成的组,称为串。 For example, in some NAND flash memory, the memory cells along each bit line is connected to each other constitute a group of sixteen or thirty-two memory units, referred to as a string. 读取自特定存储单元的电压通常取决于串中的其他存储单元的电压。 Read from a particular memory cell typically depends on the voltage of the voltages of the other memory cell string. 此效应通常称为背景图案相关性(BPD)。 This effect is usually referred to as the background pattern correlation (BPD). 又例如,由读出放大器导致的参数变化和其他失真也可以在沿着一条位线的不同存储单元中相关联。 As another example, the parameter change, and other distortions caused by the sense amplifier may be associated along one bit line different storage units.

[0189] 在其他情况下,具体存储单元中的失真度可以和沿同一字线而处的其他存储单元的失真度相关联。 Distortion associated with the other memory cells [0189] In other cases, the distortion of the particular storage unit may be along the same word line and at. 例如,考虑和同一页中的其他存储单元相比需要明显更长的编程时间的某一存储单元。 For example, consider other storage units and the same page of memory cells require a significantly longer time compared to programming. 当所涉及的页正在被编程时,在一定次数的P&v迭代之后,大多数存储单元达到它们的预期电荷电平,但是在“慢”存储单元中的电荷电平仍然远不达期望电平。 When the page concerned is being programmed, after a certain number of P & v iterations, most of the memory cells reach their intended level of charge, but the charge level in the "slow" in the memory cell is still far from reach the desired level. 因此,在慢存储单元中的源极-漏极电流就因此而较低。 Thus, the source electrode slow storage unit - drain current is therefore lower. 使用另外的P&V迭代过程继续对该慢存储单元进行编程,而其电流增大。 Additional P & V using an iterative process to continue programming the slow memory cell, while the current increases. 增大的电流增大了落在地线上的电压以及页中其他存储单元的源极-漏极电压。 The increased current increases the source voltage falls to the ground line and a page of memory cells in the other electrode - drain voltage. 作为结果,页中的其他存储单元的门限电压下降。 As a result, the other page gate threshold voltage of the memory cell drops.

[0190] 虽然下文对图4的说明涉及沿着位线的相关失真,然而图4的方法也可以用于预测和补偿沿着字线的相关失真。 [0190] Although the following text relates to the distortion along the associated bit line description of FIG. 4, however, the method of FIG. 4 may be used to predict and compensate for distortions associated along a word line. 此外作为替代,所述方法可被用于预测和校正任何其他在某一组中的存储单元的失真度彼此相关的失真机制,这样的存储单元例如为在阵列中彼此极为接近的存储单元,以及具有相同电源电压(Vcc)线、地线或功率供应电路的存储单元。 Further alternatively, the method may be used to predict and correct any distortion in the other memory cells in a group associated with each other distortion mechanisms, such as, for example, a memory cell array in close proximity to each other in a storage unit, and having the same supply voltage (Vcc) line of the memory cell, the ground or the power supply circuit.

[0191]当沿着某一位线的存储单元的失真度相关时,有时可将失真度建模为 [0191] When the correlation distortion along a bit line of memory cells, and sometimes distortion may be modeled as

[0192] 咖,m) = m))+[g; (c(i, m)) [0192] coffee, m) = m)) + [g; (c (i, m))

i>n i<n i> n i <n

[0193] 其中e (n,m)表示在列(位线)m和行(页)η处的存储单元的失真度。 [0193] where e (n, m) represents the distortion in the column (bit line) memory cells and row m (p) at the [eta]. c(i,m)表示从第i页的第m位线处的存储单元读取的电压。 c (i, m) denotes the voltage read from the memory cell at the m-th bit line on page i. &和gi分别表示定义在第i页的一个存储单元的电压与沿着同一位线在先前页中和后继页中的存储单元的依赖关系的函数。 And & gi represent the function defined in one memory cell and the voltage of the previous page i along the dependencies on the previous page and subsequent pages of memory cells of the same bit line. 公式[5]假设页被循序处理。 Equation [5] is assumed to be sequentially processed pages.

[0194] 图4是示意性地示出了根据本发明的一个实施方案的用于预测和消除位线相关失真的一种迭代方法的流程图。 [0194] FIG. 4 is a schematic flow chart illustrating an iterative method for prediction and elimination of distortion associated bit line according to an embodiment of the present invention. 在失真记录步骤102,所述方法始于MSP记录先前读取的存储单元的失真度。 Distortion in the recording step 102, the method begins distortion storage unit previously read recording MSP. 可能在ECC解码之后,MSP可以用任何适当的方法计算失真度,例如通过将读取电压与期望的标称电压相比较。 Possibly after ECC decoding, the MSP can be by any suitable method of calculating the degree of distortion, e.g., by a read voltage with a desired nominal voltage is compared.

[0195] 在目标读取步骤106,MSP读取特定存储单元的电压,这个存储单元被称为目标存储单元。 [0195] In certain reading step 106, MSP specific read voltage of the memory cell, the memory cell is referred to as a target storage unit. 然后在预测步骤110,MSP基于记录的沿同一位线的其他存储单元的失真度值,并基于从这些存储单元读取的电压,预测在目标存储单元之中的失真度。 Then 110, MSP-based storage unit along with the other bit line of the prediction distortion value recording step, based on the voltage read from the storage unit, the predicted degree of distortion in the target memory cell. 例如,MSP可以使用上述公式[5]预测失真度。 For example, MSP can be used the above formula [5] predicted degree of distortion.

[0196] 在校正步骤114,MSP使用所估计的失真度来校正从目标存储单元读取的电压.然后在解码步骤118,MSP基于校正的电压,对存储在目标存储单元中的数据进行解码。 [0196] In 114, MSP using the estimated distortion correction step of correcting the voltage read from the target memory cell. Then 118, MSP-based voltage correction data stored in the target storage unit is decoded in the decoding step. 当ECC解码器包括软解码器时,MSP可以替代地基于所估计的失真度,校正存储在存储单元中的比特的软ECC度量(例如,LLR)。 When the ECC decoder comprises a soft decoder, the MSP can alternatively be based on the estimated distortion, the correction bits in the storage unit is ECC soft metrics (e.g., LLR). 此类校正办法,例如在上述PCT申请“CombinedDistortionEstimation and Error Correction Coding for MemoryDevices” 中得以描述。 Such correction methods, for example, been described in the above PCT application "CombinedDistortionEstimation and Error Correction Coding for MemoryDevices".

[0197] 虽然图4的描述为清楚起见注重于单个目标存储单元,但是随着从存储器读取页,预测和校正过程通常并行地在多个存储单元中执行。 [0197] Although the description of FIG. 4 for clarity focus on a single target storage unit, but with the page is read from memory, and the corrected prediction process is typically performed in parallel in the plurality of storage units.

[0198] 为了改进存储效率,MSP可以仅为每个位线存储单个失真值,而不是记录并存储每个先前读取的存储单元的失真度。 [0198] In order to improve storage efficiency, the MSP may be only each bit line stores a single distortion value, and stores the record instead of distortion of each memory cell previously read. 存储的值,标注为,表示在读取第η页之后的e (n,m) 的估计值。 Stored value, labeled, after the first reading e represents η page (n, m) is an estimated value. 对于读取的第一页,通常被初始化为O。 Read the first page, typically initialized to O.

[0199] 当对第η页解码时,MSP更新我冲的值,例如使用表达式 [0199] When the first page η decoding, MSP I rushed updated value of, for example, use the expression

[0200] e{m) = (\-δη)· e(m) + Sn ■ [c{n, m) — c(n, m)\ [0200] e {m) = (\ -δη) · e (m) + Sn ■ [c {n, m) - c (n, m) \

[0201] 其中δ n表示用于第n页的预定步长。 [0201] where [delta] n represents a predetermined step length for the n-th page. c(n,m)表示从第η页的第m位线的存储单元读取的电压,而表示该存储单元的基于解码器输出的标称电压。 c (n, m) denotes the voltage read from the memory cell of the m-th bit line η page, and indicates that the storage unit based on the nominal output voltage of the decoder. 当读取第n+1页时,MSP可以通过估算^(m) = ^(m)—尤+1 ■c{n+\,m)^gn 来基于预测失真。 When this page is read first n + 1, MSP can estimate ^ (m) = ^ (m) - in particular +1 ■ c {n + \, m) ^ gn be based on the predicted distortion. 校正电压(例如,c(« +1, m)- e(m))被用来解码数据。 Correction voltage (e.g., c ( «+1, m) - e (m)) is used to decode the data.

[0202] 上述方法在预测和校正读出放大器的变化的增益、偏差或其他变化的参数时会尤其有效。 [0202] The method will be particularly effective when the prediction gain parameter and the correction readout, or other changes in the deviation amplifier changes. 此类参数还可以包括对特定电压电平的分布或所有电压电平的联合分布的可变的偏差或展宽。 Such parameters may also include a variable offset joint distribution of development or distribution of a specific voltage level or all of the width of the voltage level.

[0203] 当此方法用于校正NAND闪存存储单元阵列中的BH)失真时,可能存在一个贡献了大部分失真的特定单元,例如因为它被过编程。 [0203] When this method for correcting the NAND flash memory cell array BH) distortion, there may be a distortion contributes most to the particular cell, for example because it is over-programming. 在这种情况下,迭代方法可以在NAND存储单元上重复,直到这个存储单元被识别,在这时刻的值被重置。 In this case, an iterative process can be repeated on the NAND memory cell until the memory cell is identified, the value is reset at this time. 不同于通常在每个NAND存储单元串执行的对BH)失真的校正,通常是在每条完整位线上追踪和执行读出放大器的变化。 Unlike the normal correction of BH) distortion of each string of NAND memory cell is performed, is usually performed on each track and the read bit lines change complete amplifier.

[0204] 在一些实施方案中,MSP 52维持保持每条位线、字线或其他相关存储单元组的所追踪的参数的表格或其他数据结构。 [0204] In some embodiments, MSP 52 holding each bit line is maintained, the table parameters of the tracked word line or other memory cell group or other data structures.

[0205] 如上所述,一些存储单元可能受扰动噪声影响,扰动噪声也就是由阵列中的其他存储单元上执行的操作所导致的失真。 [0205] As described above, the memory elements may be subject to noise disturbance, the disturbance noise is performed by the operation on another memory cell array caused by distortion. 在一些实施方案中,MSP 52校正扰动噪声是在形成扰动噪声之时,而不是在读取被干扰存储单元时。 In some embodiments, MSP 52 at the time of correcting the disturbance noise disturbance noise forming, rather than reading memory cell interference.

[0206] 图5是示意性地示出了根据本发明的一个实施方案的一种用于校正扰动噪声的方法的流程图。 [0206] FIG. 5 is a diagram schematically illustrates a flowchart of a method of correcting the disturbance noise according to one embodiment of the present invention. 在扰动创建操作步骤122,所述方法始于MSP 52执行存储器存取操作,该存储器存取操作可对一些存储单元贡献扰动噪声。 The procedure for creating the disturbance 122, the method begins with MSP 52 performs memory access operation, the memory access operation may contribute to a number of memory cells to disturbing noise. 存储器存取操作可以包括,例如,编程、读或擦除操作。 Memory access operations may include, for example, program, read or erase operation. 在读取潜在被扰动存储单元的步骤126,MSP从可能被存储器存取操作所扰动的存储单元读取电压。 In the read step of the memory cell is perturbed potential 126, MSP read voltage from the memory cell may be perturbed memory access operation. [0207] 在扰动估计步骤130,MSP评估在潜在被扰动存储单元中的扰动噪声的电平。 [0207] In the disturbance estimation step 130, MSP assess the potential level of disturbance in the memory cell is disturbed noise. 为此目的,MSP可以使用任何适合的失真估计方法。 For this purpose, MSP may use any suitable method to estimate distortion. 例如,所述MSP可以使用判决导向方法,其中将读取自存储单元的电压和由硬分割所确定的相应标称电压电平相比较,或者与通过将ECC解码运用于读取自存储单元的电压而确定的标称电压电平作比较。 For example, the MSP decision-directed methods can be used, which is read from the memory cell voltage and a corresponding nominal voltage level determined by the hard-sliced ​​phase comparison, and by the ECC decoding or reading from a memory cell used comparing the nominal voltage level of the voltage determined.

[0208] 在一些情况下,扰动噪声可以增加在相邻页中的一些已擦除存储单元中的电荷电平。 [0208] In some cases, the disturbance noise can increase the level of charge in some of the erased memory cells in an adjacent page. 在这样的情况下,MSP可以通过对潜在被扰动页中的已擦除存储单元(也即,其电压低于某一门限电平的存储单元,该门限电平可以不同于通常用于检测已擦除存储单元的门限电平)的数量进行计数,来评估扰动电平。 In such a case, the MSP can be perturbed by potential page has been erased cells (i.e., the memory cell voltage lower than a certain threshold level, the threshold level may be different from commonly used detecting the number of NAND memory cell erased threshold level) was counted to assess the level of disturbance. MSP可以将潜在扰动存储器存取操作之前和之后的已擦除存储单元的数量进行比较,并且从这两个结果之间的差来评估扰动电平。 Potential perturbations MSP access memory may be compared to the number before the operation and after the erased memory cells, and this difference between the two results to evaluate the level of disturbance.

[0209] 在高扰动检查步骤134,MSP检查所估计的失真度是否超过一预定义的门限。 [0209] In the high disturbance checking step 134, MSP check the estimated distortion exceeds a predefined threshold. 在扰动校正步骤138,如果扰动电平被视为高,则MSP校正在潜在被扰动存储单元中的扰动噪声。 High disturbance correction step 138, if the disturbance level is considered, the MSP is potentially corrected disturbance noise disturbance in the memory cell. 例如,MSP可以刷新在同一存储单元中的数据,重新编程在其他存储单元中(也即,在另一页中)的数据,或对现有的已编程的存储单元增加电荷。 For example, the MSP can refresh the data in the same storage unit, in other reprogramming the memory cell (i.e., another page) of data, or increase the charge of the conventional memory cells have been programmed. MSP也可以使用更强的ECC来编码数据,并且将新编码的数据存储在另一页中。 MSP stronger ECC may be used to encode data, and the new encoded data is stored in another page. 否则,也即,如果扰动电平被认为可容忍, 则在终止步骤142终止该方法。 Otherwise, i.e., if the disturbance level is considered tolerable, then terminates at step 142 the method is terminated.

[0210] 在一些情况下,在每次读、写和擦除操作之后执行图5的方法,会显著地增加处理时间。 [0210] In some cases, the method of FIG. 5 is executed after each read, write and erase operations, can significantly increase processing time. 因此,在一些实施方案中,MSP仅仅在系统空闲的时间段期间执行图5的方法。 Thus, in some embodiments, the MSP method of Figure 5 is performed only during a time period the system is idle.

[0211] 图6是根据本发明的一个替代性的实施方案,示意性地示出了用于校正扰动噪声的另一种方法的流程图。 [0211] FIG. 6 is an alternative embodiment of the present invention, schematically illustrates a flowchart of another method for correcting the disturbance noise. 所述方法基于扰动噪声是由比目标存储单元更新近地编程的存储单元贡献到该目标存储单元的事实。 The method is based on the disturbance noise contributed by the more recent than the programmed target memory cell storage unit to the fact that the target memory cell. 为简洁起见,比目标存储单元更为新近地编程的存储单元被称为与目标单元相比“较年轻”。 For brevity, more recent than the target memory cells programmed memory cell is compared with the target unit called "younger." 比目标存储单元更早编程的存储单元被称为“较老”存储单元。 Earlier than the target memory cells programmed memory cells are called "older" storage unit.

[0212] 在潜在干扰存储单元识别步骤146,上述方法始于MSP 52识别潜在地对目标存储单元引发扰动噪声的存储单元。 [0212] In the step of identifying potentially interfering storage unit 146, the above-described method begins MSP 52 to identify a potential target storage unit of the storage unit perturbation induced noise. 在较年轻存储单元识别步骤150,MSP识别并标记哪些潜在干扰存储单元比目标存储单元较年轻。 In younger storage unit identification step 150, MSP identified and marked memory cells which potentially interfere with younger than the target memory cell. 在一些实施方案中,MSP存储每个页被编程的时间标记,其通常作为页的一部分和数据一起存储。 In some embodiments, the MSP is stored for each page has been programmed time stamp, which is generally stored together as part of the page and data. 所述MSP查询所存储的标记,以便确定哪些存储单元比目标存储单元较年轻。 The query token stored MSP to determine which memory cells younger than the target memory cell.

[0213] 当循序写存储器页时,MSP可以把在较大编号的页中的存储单元视为相比目标单元较年轻。 [0213] When the sequential write memory page, MSP can store a large number of cells in the page are treated as compared to the target cells younger. 替代地,当未循序写存储器页时,MSP可以在每个页中存储一个变量,该变量指示该页与相邻页相比的相对年龄。 Alternatively, when the memory page is not written sequentially, the MSP can store a variable that indicates relative age compared to adjacent pages each page in the page. 当此页被编程时,上述变量被设置并存储。 When the page is programmed, the above variables are set and stored. 例如,所述变量可以包括如下计数值,其对迄今为止在擦除块中被编程的页的数量进行计数。 For example, the following variables can include a count value that counts the number of the erase blocks so far in the page to be programmed. 替代地,上述变量可以为每个相邻页包含一个布尔标志,其指示在当前页被编程时,相邻页是已编程还是已擦除。 Alternatively, the above variables may comprise a boolean flag for each of the adjacent pages, which indicates when this page is programmed, the adjacent pages are programmed or erased. 此外作为替代,MSP可以使用任何其他适合的方法以确定与目标存储单元相比较年轻的潜在干扰存储单元。 Further Alternatively, MSP can use any other suitable method to determine the target memory cell potential interference with younger storage unit.

[0214] 在干扰存储单元读取步骤154,MSP 52读取被标记的存储单元(也即,比目标存储单元较年轻的潜在干扰存储单元)的电压。 [0214] Step 154 ​​reads in the memory cell interference, MSP 52 reads the storage unit (i.e., younger than the target memory cell of the memory cell potential interference) voltage is marked. 所述MSP可以重新读取干扰存储单元和/或使用ECC解码器对存储在潜在干扰存储单元中的数据进行可靠地解码。 The MSP can be re-read disturb memory cell and / or using an ECC decoder for data stored in the storage unit potentially interfering reliably decoded. 在目标存储单元读取步骤158,所述MSP也读取目标存储单元的电压。 Step 158 reads in the target storage unit, but also the MSP target memory cell read voltage. 在一些实施方案中,目标存储单元的电压以高分辨率读取,例如使用具有位数高于存储在每个存储单元中的数据位数的ADC。 In some embodiments, the target voltage of the memory cell is read at high resolution, for example, having a number of bits than data bits stored in each memory cell of the ADC. 被标记的存储单元的电压有时可以用降低的分辨率读取。 Voltage of the memory cell is read using labeled sometimes reduced resolution.

[0215] 在扰动贡献估计步骤162,所述MSP估计由较年轻潜在干扰存储单元贡献到目标存储单元的扰动噪声的电平。 [0215] Step 162 estimates the contribution of the disturbance, the estimation of the contribution by the MSP younger potentially interfering storage unit to the level of noise disturbance target memory cell. 所估计的扰动电平可以取决于:潜在被干扰存储单元的相对年龄、存储在潜在干扰存储单元中的电压值和/或数据、潜在干扰存储单元相对于目标存储单元的位置(例如,它们是否位于一相邻页、第二相邻页,等等)、被干扰存储单元的最近的编程-擦除循环的次数和/或其他信息或判据。 The estimated disturbance level may depend on: the relative age of potentially interfered memory cells, the voltage value stored in the storage unit of the potential interference and / or data relative to the target memory cell of the memory cell potential interference (e.g., whether they located adjacent pages a, a second adjacent pages, etc.), the memory cell interference latest program - the number of erase cycles and / or other information or criteria. 对扰动电平的一种有效估计,是该扰动电平以上述参数为条件的平均值。 Kind of effective estimate the disturbance level is the average level of the disturbance parameters in the above-described conditions.

[0216] 在扰动消除步骤166,所述MSP对所估计的扰动电平进行补偿。 [0216] In the noise canceling step 166, the MSP estimated disturbance level to compensate. 例如,所述MSP可以从读取自目标存储单元的电压中减去所估计的扰动电平,以产生校正的电压。 For example, the MSP reads from the level of the voltage disturbance target memory cell is subtracted from the estimated to produce a corrected voltage. 校正的电压被用于对存储在目标存储单元中的数据解码,或者用于修改ECC解码器度量。 The correction voltage is used for decoding data stored in the target storage unit, or for modifying the ECC decoder metric.

[0217] 虽然上述说明为清楚起见注重于单个目标存储单元,但是图6的过程也可以随着从存储器读取页,而并行地针对多个目标存储单元执行。 [0217] While the above description for clarity focus on a single target storage unit, but the process of FIG. 6 may be read as the page from the memory, and executed in parallel for the plurality of target storage unit.

[0218] 在一些实施方案中,使用编程与验证(P&V)过程对存储单元编程,而当对存储单元编程时,MSP 52采用失真补偿。 [0218] In some embodiments, a programming and verification (P & V) during programming of the memory cell, the memory cell when programming, MSP 52 using the distortion compensation. 在一些实施方案中,MSP在对存储单元的编程和读取期间均采用失真补偿。 In some embodiments, MSP during the memory cell programming and reading are used in distortion compensation.

[0219] P&V过程通常用于对存储单元编程。 [0219] P & V process typically used for memory cell programming. 在一典型的P&V过程,通过施加一系列电压脉冲而对一存储单元编程,该一系列电压脉冲的电压电平逐个脉冲增加。 In a typical procedure P & V by applying a series of voltage pulses of a memory cell is programmed, the voltage level of a pulse by pulse series of voltage pulses is increased. 在每个脉冲之后,读取(“验证”)已编程的电压电平,且迭代继续进行直到达到期望的电平。 After each pulse, reading ( "authentication") programmed voltage level, and the iterations continue until the desired level is reached. P&V过程,例如,由Jung 等人于1996 年11 月在IEEE Journal of Solid State Circuits (11 :31)的1575 页-1583 页上发表的“A 117mm2 3.3V Only 128Mb MultilevelNAND FlashMemory for Mass Storage Applications”中描述,以及由Lee 等人于2002 年5 月在IEEEElectron Device Letters (23 :5)的264 页-266 页发表的“Effects of Floating GateInterference onNAND Flash Memory Cell Operation” 中描述,上述文献均在此处以援引方式纳入本文。 P & V process, e.g., by a Jung et al. Of Solid State Circuits in November 1996 in IEEE Journal: (11 31) 1575 -1583 Page published "A 117mm2 3.3V Only 128Mb MultilevelNAND FlashMemory for Mass Storage Applications" in description, and by Lee et al., in May 2002 in IEEEElectron Device Letters: published (235) of 264 -266 pages "Effects of Floating GateInterference onNAND Flash Memory Cell Operation" described in the literature are cited here to incorporated herein by reference.

[0220] 图7是示意性地示出了根据本发明的另一实施方案的用于在存储单元阵列28之中估计和消除失真的方法的流程图。 [0220] FIG. 7 is a diagram schematically illustrating a flowchart according to another embodiment of the present invention, in a method of estimating and canceling the distortion 28 in the memory cell array. 与一些已知的验证读取自存储单元的电压达到期望值的P&V过程不同,图7的方法使得存储在存储单元中的电荷达到期望的电荷,这个电荷表示所存储的数据。 Unlike some known voltage verify read from the storage cell reaches a desired value P & V process, the method of FIG. 7 such that charge stored in the storage unit reaches a desired charge, the charge represents the stored data.

[0221] 验证存储在存储单元中的电荷电平而不是读取电压,是有好处的,因为在写时和读时的失真度可能是不同的。 Of charge [0221] authentication stored in the storage unit read voltage level instead, is advantageous because, when writing and when reading distortion may be different. 此方法可以用于补偿任何失真类型或者机制。 This method can be used to compensate for any distortion in the type or mechanism.

[0222] 所述方法始于MSP 52意欲对某页编程之时。 When MSP 52 is intended for programming a page of the [0222] The method begins. 在潜在干扰存储单元读取步骤170,对于页中一将要编程的给定目标存储单元,MSP读取潜在地导致该目标存储单元失真的存储单元。 Step 170 reads in the memory means the potential interference for a page to be programmed to a given target memory cell, the MSP reads potentially leading to memory cells in the target memory cell distortion. (在一些情况下,MSP已经处理了这些值,因为它们刚被编程,在这种情况下没有必要读取这些存储单元。)在失真计算步骤174,所述MSP估计由潜在干扰存储单元导致的对目标存储单元的失真。 (In some cases, these MSP values ​​have been processed, because they had just been programmed, reading the memory cells is not necessary in this case.) In step 174 the distortion calculation, the MSP estimated potential interference caused by the memory cell distortion of the target storage unit. 所述MSP可以使用任何适当的方法,例如上述的各种不同的估计过程,用于估计失真度。 The MSP may use any suitable method, for example, the above-described various estimation process for estimating distortion.

[0223] 基于所估计的失真,MSP计算一预先校正的电压值以便编程目标存储单元。 [0223] Based on the estimated distortion, MSP calculates a predetermined voltage value in order to program the corrected target memory cell. 通常,MSP通过从意图在所述存储单元中存储的标称电压电平中减去所估计的失真度,来产生校正的电压。 Typically, the MSP by subtracting the estimated intent from the nominal voltage level stored in said storage means in the distortion to generate corrected voltage. [0224] 在预校正编程步骤178,所述MSP使用P&V过程,以预校正的电压对目标存储单元编程。 [0224] In the pre-programmed calibration step 178, the MSP process using P & V, the memory cell pre-programmed target voltage correction. 作为结果,存储在目标存储单元中的电荷电平真实地反映了写到存储单元中的数据,因为它被预先校正以移除在写的时候存在的失真。 As a result, the electric charge stored in the target level storage unit true reflection data is written in the memory cell, since it is previously corrected to remove distortion occurring when writing.

[0225] 在存储单元读取步骤182,对存储单元的读取可能在对该存储单元编程之后很久才发生,当读取存储单元时,MSP读取目标存储单元以及潜在干扰存储单元。 [0225] Step 182 reads in the memory unit, reading of the memory cells may not occur for a long time after the memory cell programming, memory cell when reading, reading the target memory cell and the MSP potential interference storage unit. 在失真重新估计步骤186,MSP重新估计在读取时由潜在干扰存储单元对目标存储单元导致的失真。 Re-estimating the distortion in step 186, MSP again estimated distortion when read by the storage unit of potential interference caused by the target memory cell. MSP可以使用任何适合的方法,例如上述的各种不同的估计过程,用于重新估计所述失真度。 MSP using any suitable method, such as the above-described various estimation procedure for re-estimating the distortion.

[0226] 如上所述,目标存储单元可能在很久以前已被编程,而诸如温度和电源电压之类的操作条件可能已经改变。 [0226] As described above, the target storage unit may have been programmed long time ago, and operating conditions such as temperature and supply voltage or the like may have changed. 此外,在目标存储单元被编程之后,另外的潜在干扰存储单元可能已经被读、编程或擦除。 Further, after the target memory cell is programmed, the memory cell further potential interference may have been read, programmed or erased. 从而,在步骤186计算的失真度可能与在上述步骤174计算的失真度大相径庭。 Thus, in step 186 the calculated distortion could differ distortion calculated in step 174.

[0227] 在校正步骤190,MSP基于重新估计的失真,校正读取自目标存储单元的电压。 [0227] In the correction step 190, MSP again based on the estimated distortion, the correction voltage read from the target memory cell. 校正的电压被用于解码自目标存储单元的数据。 The correction voltage is used for decoding data from the target memory cell. 为了在读取干扰存储单元的电压时减少失真,以判决导向方式迭代地执行对存储单元数据的解码。 In order to reduce the voltage distortion interference when reading the memory cell, in an iterative decision-directed manner to perform the decoding of the memory cell data.

[0228] 在图7的方法中,在写存储单元的时候和读存储单元的时候都校正失真,且每次校正均使用当前存在的实际失真度。 [0228] In the method of FIG. 7, the memory cell when writing and reading the memory cells when they are correct the distortion, and each actual distortion correction are currently exist. 从而,相对于已知的P&V过程,本方法更具鲁棒性,并且更容忍对操作条件和随后的编程操作进行的改变。 Thus, with respect to the known P & V process, the present method more robust, and more tolerant of changing operating conditions and a subsequent programming operation.

[0229] 在一些实施方案中,仅仅在编程期间采用失真校正,且不经过二次失真校正即对存储单元进行读取。 [0229] In some embodiments, the distortion correction using only during the program, i.e., without passing through the second distortion correction memory cells are read. 在这些实施方案中,图7的方法的步骤182至190被略去,而MSP应该将来自未经编程的存储单元的干扰纳入考虑。 In these embodiments, the method steps 182-190 in FIG. 7 is omitted, and the interference from the MSP should unprogrammed memory cells into consideration.

[0230] 图8是示意性地示出了根据本发明的一个实施方案用于估计目标存储单元中的失真的又一种方法的流程图。 [0230] FIG. 8 is a schematic flow chart illustrating yet another method for estimating a target storage unit in accordance with one embodiment of the distortion in the present invention. 图8的方法利用如下事实,即由在目标存储单元之前编程的存储单元导致的失真可不同于在目标存储单元之后编程的存储单元导致的失真。 The method of FIG. 8 using the fact that the memory cell before programming the target memory cell may be different than the distortion caused by distortion after the target memory cell programming a memory cell caused.

[0231] 另一种假设是,所述阵列使用P&V过程编程,如上所述。 [0231] Another is that, using the array P & V programming process, as described above. 在一些已知的P&V过程中,例如在上文引用的由Jung等人所著的文献中,在某一页中的每个存储单元都被编程为标注以O至MI的M个电压电平中的一个,其中电平O是已擦除电平。 In some known process P & V, for example, by Jung et al., Written in the literature cited above, each of the memory cells in a page are programmed to the MI for the label to a O M voltage levels one in which the level is erased O level. 所述P&V过程分M个阶段对所述页编程。 P & V The process is divided into M phase of the page programming. 在阶段i,一系列电压脉冲被施加到编程电平应该为i或更高的存储单元。 At stage i, a series of voltage pulses is applied to the program level i must be higher or the storage unit. 在每个脉冲之后,所述过程读取不同存储单元的电压,并且停止向已经达到其期望电平的存储单元施加脉冲。 After each pulse, the process of reading the voltages of different memory cells, and ceases to have reached its desired level pulse is applied to the memory cell.

[0232] 在一些实施方案中,对于一给定的目标存储单元,MSP根据编程时间对潜在干扰存储单元分类。 [0232] In some embodiments, for a given target memory cell, the MSP according to the programming time of the memory cell classification potential interference. (如上所述,MSP可以存储每个页的被编程的时间标记,并且将存储的标记用于分类过程。)存储单元的一子集,标注为D1,包括潜在干扰存储单元,其在目标存储单元被编程时并未被所述P&V过程完全编程。 (As described above, the MSP can be programmed for each page stored time stamp, and stores the flag for the classification process.) A subset of memory cells, denoted D1, potential interference comprising a storage unit that stores target the unit has not been fully programmed P & V during programming. 当目标存储单元被编程时,类Dl中的存储单元处于已擦除电平或是被部分编程,但是可能从那时起已被编程。 When the target memory cell is programmed, the class Dl memory cell is erased or partially programmed level, since then it may have been programmed.

[0233] 在一些编程方案中,分数个阶段对存储单元编程。 [0233] In some programming scheme, a fraction of the memory cell programming phase. 例如,在一些4电平存储单元编程方法中,最低有效位(LSB)和最高有效位(MSB)被在两个单独的步骤中写入。 For example, in some power 4-level memory cell programming method, the least significant bit (LSB) and a most significant bit (MSB) is written in two separate steps. 一种示例性的方法由Takeuchi 等人于1998 年8 月在IEEE Journal of Solid-State Circuits (33 :8)的1228页-1238页发表的“A Multipage Cell Architecture for High-SpeedProgrammingMultilevel NAND Flash Memories”中描述,该文献在此处以援引方式纳入本文。 An exemplary method of Takeuchi et al., In August 1998 in of Solid-State Circuits IEEE Journal (33: 8) of the page 1228 -1238 published "A Multipage Cell Architecture for High-SpeedProgrammingMultilevel NAND Flash Memories" in described in the literature cited herein is incorporated herein by reference. 在此类方法中,在某一时间点可将存储单元编程到中间电平,而未来编程步骤将所述存储单元编程到其最终编程值。 In such a method, at the point in time the storage unit may be programmed to an intermediate level, and the next step of programming the memory cell is programmed to its final programmed value. 当使用此类编程方法时,类Dl被扩展而包括如下存储单元,该存储单元在目标存储单元被编程时处于已擦除电平或处于中间编程电平,但可以自那时起编程到其最终值。 When using such a programming method is extended and the class Dl comprises a storage unit, the memory cell is erased or at an intermediate level program level when the target memory cell is programmed, it can be programmed to it since then The final value.

[0234] 存储单元32的另一子集,标注为D2,包括潜在干扰存储单元,其在目标存储单元被编程时已被编程。 [0234] Another subset of the storage unit 32, denoted D2, a storage unit including potential interference, which has been programmed in the target memory cell is programmed. 因为当目标存储单元被编程时,从这些存储单元到该目标存储单元的干扰已经存在,故所述P&V过程已经至少部分地对此干扰进行补偿。 Because when the target memory cell is programmed from the storage unit to the target memory cell interference exists, so that the P & V process has at least partially compensate for this disturbance. 第三类存储单元,标注为D3,包括与所述目标存储单元并发编程的潜在干扰存储单元,例如,与所述目标存储单元处于同一页上的存储单元。 The third storage unit denoted as D3, a storage unit comprising a potential interference with the concurrent programming of the target memory cell, e.g., the target storage unit in the storage unit on the same page.

[0235] MSP 52可以根据不同类的潜在干扰存储单元,估计针对目标存储单元的失真。 [0235] MSP 52 can potentially interfere with different types of memory cells, for the estimated distortion target memory cell. 设η和m各自表示阵列28中目标存储单元的行号和列号。 Provided η and m each represent an array in a target row number of memory cells 28 and column number. 则xn,m表示在使用所述P&V过程写目标存储单元之后此目标存储单元的电压。 Is xn, m indicates a voltage after using the P & V during a write target memory cell of this target memory cell. Xi, j表示在上次编程迭代之后的目标存储单元电压被验证时的位于i行和j列的存储单元的电压。 Xi, j represents a voltage of the memory cell located at row i and column j of the memory cell when the target voltage after the last iteration of the programming is verified. yn,m表示读取自目标存储单元的存储单元电压值,由于失真,它不同于xn,m。 yn, m represents the voltage value read from the memory cell's target memory cell, due to the distortion, it is different from xn, m.

[0236] 在yn,m中存在的总失真可被写为 [0236] present in total distortion yn, m can be written as

「02371 e^m ~ [ hn、mj,j《yi、j 一xiJ) + "02371 e ^ m ~ [hn, mj, j" yi, j a xiJ) +

LJ (i Ac η. LJ (i Ac η.

[0238] . ί - XjJ )^- [0238] ί -. XjJ) ^ -

{um {Um

[0239] Σ ·mwc 齡 + ^ [0239] Σ · mwc age + ^

(0)6¾ (0) 6¾

[0240] 其中hn,m,M表示从位于i行j列的干扰存储单元到位于η行m列的目标存储单元的交叉耦合干扰系数。 [0240] where hn, m, M represents the interference from the memory cell located at the i-th row j-th column located η rows and m columns cross coupling coefficient of the target memory cell interference. b表示常数偏项。 b represents a constant bias term. 虽然上述公式[7]涉及线性失真模型,但也可以使用非线性模型。 Although the above-mentioned formula [7] relates to linear distortion model, it is also possible to use a nonlinear model.

[0241] 类Dl中的存储单元包括在目标存储单元被编程之后而被编程的存储单元。 [0241] Dl-based memory cell comprises a storage unit after the target memory cell is programmed to be programmed. 因此,由于该编程操作而添加到这些存储单元的电荷所导致的干扰在那时并不存在,并且所述P&V过程也不可能已经对此失真做补偿。 Therefore, since the programming operation and the charge added to the interference caused by these memory cells does not exist at that time, and the P & V has been impossible for this process to make the distortion compensation.

[0242] 当目标存储单元被编程时,类D2中的存储单元已经被编程,并且当所述P&V过程对所述目标存储单元编程时,这些存储单元所导致的失真已经存在。 [0242] When the target memory cell is programmed, the D2 class memory cells have been programmed, and when the P & V process when the target memory cell programming, memory cells caused distortion exists. 因此,当目标存储单元被编程时,所述P&V过程已经(至少部分地)补偿所述失真。 Thus, when the target memory cell is programmed, the P & V process has been (at least partly) compensate for the distortion. 然而,在目标存储单元被编程时这种补偿是正确的,并且不考虑在那一时刻和所述目标存储单元被读取时之间所发生的老化、电荷泄漏和其他效应。 However, when the target memory cell is programmed such compensation is correct, and without regard to aging and other effects of charge leakage between the target and the moment when the memory cell is read it occurred. 在以上公式[7]的第二项中的矣,7是对电压的估计,其在目标存储单元被编程时存在于干扰存储单元之中。 Carry in the second term in the above formula [7], and is an estimate of the voltage 7, in which the target memory cell is programmed interference exists in the storage unit.

[0243] 在一些实施方案中,可通过将所述ECC解码运用到这些存储单元的输出来估计。 [0243] In some embodiments, it may be estimated by use of the ECC decoder output to the memory cells. 通过恢复写到存储单元中的比特集,所述ECC可以帮助校正严重的错误,例如由严重泄漏导致的错误。 By restoring a set of bits written in the memory cell, the ECC can help correct severe errors, such as error caused by a serious leak. 替代地,公式[7]的第二项中的八厂七可以用yi,j的无记忆函数或U勺无记忆函数来估计,例如α (或aJu),其为电压电平为的存储单元估计泄漏错误。 Alternatively, the formula [7] in the second term of seven eight plants can yi, j of the memory-function or U spoon memoryless function to estimate, for example [alpha] (or Aju), which memory cell is the voltage level estimated leak errors.

[0244] 上述公式[7]中的第三项,涉及类D3中的存储单元,假定使用P&V过程,其固有地对由被编程到小于或等于目标存储单元的电平的D3存储单元所导致的失真进行补偿。 [0244] the above formula third item [7], to class D3 of the memory cell, it is assumed that P & V process, which is inherently of the to be programmed to a level less than or equal to the target storage unit D3 of the memory cell caused by the distortion compensation. 在目标存储单元已经被完全编程之后,当在与该目标存储单元相同的页上的潜在干扰存储单元被编程到较高电平时,此编程通常在P&V过程的较晚步骤中执行。 , When the potential interference on the same page of target memory cell memory cell is programmed to a higher level, this programming is typically performed at a later step in the process of P & V storage unit after the target has been completely programmed. 从而,由具有比目标存储单元更高电平的D3存储单元所导致的失真的有效部分在目标存储单元被编程时将不存在,并且P&V过程将不能补偿此部分失真。 Thus, there will be no distortion of the active portion having a higher level than the target storage unit D3 of the memory cell caused when the target memory cell is programmed, and P & V will not be able to compensate for this part of the process of distortion. 当使用在一次操作中对给定存储单元的所有位编程的P&V过程(例如由Jung等人所著的文献中描述的过程)时,上述公式[7]的第三项尤其有效。 When all the bits are programmed to a given memory cell is P & V process (e.g. process written by Jung et al., Described in the literature) in one operation, the third above-mentioned formula [7] is particularly effective. 当使用在多个阶段中对存储单元编程不同的数据位的P&V过程(例如由Takeuchi等人所著的文献中描述的过程)时,上述公式[7]的第三项可被略去。 When used in multiple stages of programming the memory cells of different data bits P & V process (e.g. process written by Takeuchi et al., Described in the literature), the third above-mentioned formula [7] can be omitted.

[0245] 在电压读取步骤194,图8的方法始于MSP 52从阵列28的存储单元32读取电压。 [0245] In the voltage reading step 194, the method of Figure 8 begins with MSP 52 32 read voltage from the memory cell array 28. 所述电压既包括目标存储单元的电压,也包括潜在地导致对目标存储单元干扰的存储单元的电压。 Both said voltage includes a voltage target memory cell, the memory cell also includes a voltage potentially cause interference for the target memory cell. 在当前实例中,阵列28的页被循序读取,也即,逐行读取,虽然也可以使用其他读取配置。 In the present example, the page is sequentially read array 28, i.e., reading row by row, although other read configuration may be used.

[0246] 在编程时间估计步骤196,在目标存储单元被编程时,MSP估计目标存储单元和潜在干扰存储单元的值(例如,电荷电平)。 [0246] In step 196 the estimated time of programming, when the target memory cell is programmed, the MSP estimate (e.g., charge level) of the target memory cell and the potential interference of the memory cell. 所述估计可以将一些因素纳入考虑,例如读取自目标存储单元和潜在干扰存储单元的电压、目标存储单元和潜在干扰存储单元的编程顺序、自先前的编程和擦除循环以来经过的时间、存储单元已经经历的擦除循环的数量、诸如电源电压和温度之类的环境参数,等等。 The estimated number of factors may be taken into consideration, for example, read from the program sequence, and the voltage potential interference target memory cell of the memory cell, the target memory cell and the potential interference of the memory cell, since the prior program and erase cycles elapsed time, the number of erase cycles experienced by the memory cell has, supply voltage and environmental parameters such as temperature and the like, and the like.

[0247] 在写-读差估计步骤198,MSP然后估计在目标存储单元被编程时和目标存储单元被读取时产生的所估计的失真度之间的差。 [0247] In the writing - the difference between the estimated difference between the generated read step 198, MSP estimates are then read when the target memory cell is programmed and the memory unit when the estimated target degree of distortion. MSP可以使用上述公式[7]来估计这个差。 MSP can use the above formula [7] to estimate the difference. 在校正步骤200,MSP使用所估计的差来补偿失真(例如,从读取自目标存储单元的电压减去所述差或调整ECC度量)。 In the aberration correction step 200, MSP be compensated using the estimated distortion (e.g., from a target memory cell is read from the voltage difference by subtracting the adjusted ECC or metric).

[0248] 在一些P&V过程中,从较小编号的页到较大编号的页循序地将页写到存储器中。 [0248] In some P & V process, the page from the smaller number to the larger number of pages the page sequentially written to the memory. 从而,当存储单元xn, m被编程时,在i ( η的页中的存储单元已被编程,且可以假设P&V过程补偿了由这些存储单元贡献的失真。 Thus, when the memory cell xn, m is programmed in the memory cell i (η a page has been programmed, and may assume P & V distortion compensation process by the contribution of these memory cells.

[0249] 在一些实施方案中,MSP 52以与写这些页的顺序相反的顺序(也即,从较高编号的页到较低编号的页)读取这些页。 [0249] In some embodiments, MSP 52 with the order (i.e., higher numbered pages from the page to the lower numbered) page in the reverse order to write these read those pages. 当读取第η页时,MSP为每个存储单元列m计算失真度量Mm (η): When reading the first page [eta], MSP m for each memory cell column calculates distortion metric Mm (η):

Figure CN101496110BD00261

[0251] 其中N表示擦除块中的行(字线)的数量,而Xi, j表示从在i行和j列处的存储单元读取的电压。 [0251] wherein N represents the number of erase blocks in a row (word line), and Xi, j represents a voltage in the memory cell at the i-th row and j-th column is read from. 假设失真仅影响所涉及的擦除块中的存储单元。 Suppose only the distortion effects related to the erase block of the memory cell. 所述MSP通过计算 The MSP by calculating

m -MJri),从读取自当前页的电压去除失真度量。 m -MJri), this page is removed from the voltage distortion metric from read. 可被用作函数f的示例性函 It may be used as an example of the function f Functional

Figure CN101496110BD00262

[0252] 在替代性的实施方案中,MSP并发处理一整块的存储单元。 [0252] In an alternative embodiment of, MSP concurrent processing block of a memory cell. 使用待要被编程的数据和交叉耦合系数MSP计算编程值和读取值之间的误差,并且补偿此误差。 It is programmed to be calculated using the cross-coupling coefficient data and an error between the MSP and the read value programmed values ​​and compensates for this error.

[0253] 虽然图8的示例性方法涉及某些P&V处理实现,但所述方法经必要的修改后,可以和任意其他适合的P&V过程一起使用。 [0253] While the exemplary method of Figure 8 relates to certain processing implementation P & V, but the method was necessary modifications, can be used with any other suitable P & V process. 本领域技术人员将理解,可以基于所公开的实施方案对本方法进行适应性修改,以与其他种类的P&V过程一起使用。 Those skilled in the art will appreciate that modifications may be made to the present method is based on the adaptability of the disclosed embodiment, the process to P & V used together with other types.

[0254] 基于失真估计的数据刷新 [0254] Based on data distortion estimates refresh

[0255] 在一些实施方案中,MSP 52基于所估计的失真度,刷新(也即,重新编程)存储在存储单元阵列28中的数据。 [0255] In some embodiments, MSP 52 based on the estimated distortion, refresh (i.e., reprogramming) data is stored in the memory cell array 28.

[0256] 图9是根据本发明的实施方案示意性地示出了刷新存储单元阵列中的数据的方法的流程图。 [0256] FIG. 9 is an embodiment of the present invention is schematically illustrates a flowchart of a method of refreshing a memory cell of the data array. 在页读取步骤210,该方法始于MSP 52从阵列28读取存储器页。 On page reading step 210, the method begins with MSP 52 read from the memory array 28 pages. 在页失真估计步骤214,MSP估计所读取的页中的失真度。 On page distortion estimation step 214, MSP estimated distortion of the read page. 为此目的,MSP可以使用任何适当的失真估计方法,例如上文所描述的方法。 To this end, the MSP may use any suitable distortion estimation methods, such as described above.

[0257] 在失真度检查步骤218,MSP检查失真度是否可容忍。 [0257] 218, MSP checks whether the distortion in the distortion tolerable checking step. 例如,MSP可以将所估计的失真度与指示最大可容忍的失真度的预定的门限作比较。 For example, MSP can be a predetermined threshold and the estimated distortion level indicates the maximum tolerable limit distortion compared. 最大可容忍的失真度通常被选择为使得当达到门限时解码数据仍然有很大可能是无错误的。 The maximum tolerable distortion is usually chosen so that when the threshold is reached decoded data is still very likely be error-free. 这种情况保证了刷新的数据有可能是无错误的。 Refresh this case to ensure that the data might be error-free.

[0258] 如果失真度是可容忍的,所述方法循环回到上述页读取步骤210,且MSP继续读取并检查存储器页。 [0258] If the distortion is tolerable, the method loops back to step 210 to read said page, and MSP continue to read and check the memory page.

[0259] 另一方面,如果MSP确定在所读取的存储页中的失真度高于可容忍的失真度,则在重新编程步骤222,所述MSP对页的数据重新编程。 [0259] On the other hand, if the stored MSP determined distortion in the read page is higher than the degree of distortion can be tolerated, the reprogramming step 222, the MSP reprogramming data pages. 然后该方法循环回到上述的页读取步骤210。 The method then loops back to step 210 to read the above-described page.

[0260] 不同于一些周期性地执行重新编程的公知的存储器刷新方法,不论失真度如何,图9的方法仅在必要时才重新编程数据。 [0260] Unlike some reprogramming is performed periodically known memory refresh process, process regardless of how the distortion, FIG. 9 only when necessary reprogramming data. 从而,与这些公知的方法相比,再编程操作的频率降低。 Thus, as compared with these known methods, the frequency of reprogramming operation is reduced. 通常,图9的方法结合了系统20的常规操作。 Typically, the method of FIG. 9 in conjunction with a conventional operating system 20. 也即,MSP使用常规的页读和/或失真估计操作,来评估是否需要刷新,而不执行专门的读操作。 That is, MSP using conventional page read and / or distortion estimation operations, to assess the need to refresh, without performing a special read operation.

[0261] 虽然此处描述的实施方案主要着重于从多层单元(MLC)取出数据,但是本发明的原理也可用于单层单元(SLC)。 [0261] Although the embodiments described herein focus primarily on data extracted from the multi-level cell (MLC), but the principles of the invention may also be used single-level cell (SLC). 虽然此处描述的实施方案主要着重于从固态存储设备取出数据,但是本发明的原理也可以用于在硬盘驱动器(HDD)和其他数据存储介质和设备中存储和取出数据。 Although the embodiments described herein focus primarily on data extracted from the solid state storage device, but the principles of the invention may also be used in a hard disk drive (HDD), and other data storage media and devices store and retrieve data.

[0262] 因此应该理解,此处所描述的实施方案仅以举例方式引用,且本发明不限于上文中已经具体示出和描述的内容。 [0262] It should be therefore understood that the embodiments described herein are merely cited by way of example, and the present invention is not limited to the foregoing has been particularly shown and described hereinabove. 与此相反,本发明的范围涵盖上述各个特征的组合和子组合,以及其中本领域技术人员在阅读前述说明之后即可作出的未在现有技术中公开的变化和修改。 In contrast to this, the scope of the invention encompasses the above-described various combinations and subcombinations of features, as well as variations and modifications not disclosed in the prior art wherein skilled in the art upon reading the foregoing description can be made.

Claims (24)

1. 一种用于操作存储器的方法,包括: 将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中,所述第一电压电平选自可能的值的集合; 在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平; 处理所述第二电压电平以获得相应的硬判决,每个硬判决均对应于所述第一电压电平的可能的值中的相应值; 基于所述第二电压电平和所述相应的硬判决估计交叉耦合系数,该交叉耦合系数量化所述模拟存储单元之间的交叉耦合干扰;以及使用所估计的交叉耦合系数,从所读取的第二电压电平重构存储在该组模拟存储单元中的数据。 1. A method for operating a memory, comprising: a first voltage corresponding to a data level stored in a set of analog memory cells of the memory, the first voltage level is selected from a set of possible values ; after storing the data, reads the corresponding second voltage level from said analog memory unit, the second voltage level is affected by cross coupling of interference, which interference results in a different cross-coupling the second voltage level corresponding to the first voltage level; processing the second voltage level to obtain the corresponding hard decision, each hard decision values ​​corresponding to respective all possible values ​​of the first voltage level in; based level and the corresponding hard decision estimating the second voltage cross coupling coefficient, the quantization coefficient of cross coupling cross coupling interference between said analog memory means; and using the estimated cross-coupling coefficient, the read from the first in this set of simulation data storage unit stores a second voltage level remodeling.
2.根据权利要求I所述的方法,其中估计交叉耦合系数包括使用块估计过程处理所述第二电压电平和所述相应的硬判决。 2. The method according to claim I, wherein the estimating comprises using a cross coupling coefficient estimating block during the processing of the second voltage level and the corresponding hard decision.
3.根据权利要求I所述的方法,其中估计交叉耦合系数包括使用收敛到所述交叉耦合系数的序列估计过程以循序扫描所述第二电压电平以及所述相应的硬判决。 3. The method according to claim I, wherein the estimating comprises using a cross coupling coefficient converge to the cross coupling coefficient sequence estimation procedure to sequentially scan the second voltage level and the corresponding hard decision.
4.根据权利要求I所述的方法,其中估计交叉耦合系数包括采用一个减少在所述所读取的第二电压电平和所述相应的硬判决之间的距离度量的估计过程。 4. The method according to claim I, wherein the estimating comprises using a cross coupling coefficient reduces the voltage level of the second level and the read process of the estimated distance metric between the respective hard decisions.
5.根据权利要求I所述的方法,还包括既基于读取自第一模拟存储单元的第二电压电平又基于读取自第二模拟存储单元的第二电压电平,估算在所述存储器中由所述第一模拟存储单元导致的针对所述第二模拟存储单元的交叉耦合干扰。 The method according to claim I, further comprising a second voltage level on both read from the storage unit and the first analog voltage level based on the second reading from the second analog memory cell, the estimate cross-coupled interference for the second analog memory means by the first analog memory cells results in a memory.
6.根据权利要求I所述的方法,其中重构数据包括使用如下过程之一将所述交叉耦合干扰从所述第二电压电平中除去,所述过程为:线性均衡过程、判决反馈均衡(DFE)过程、最大后验(MAP)估计过程以及最大似然序列估计(MLSE)过程。 6. The method according to claim I, wherein the reconstruction data comprises using one of the following procedures to the cross-coupled interference removing from the second voltage level, the process is: linear equalization, decision feedback equalization (DFE) process, maximum a posteriori (MAP) estimation process and a maximum likelihood sequence estimation (the MLSE) process.
7.根据权利要求I所述的方法,其中估计交叉耦合系数与重构数据包括在第一处理阶段中估计所述交叉耦合系数,并且在后继于所述第一处理阶段的第二处理阶段中消除所估计的交叉耦合干扰。 7. The method according to claim I, wherein the cross coupling coefficient estimating comprises estimating said reconstructed data in a first cross coupling coefficient process stage, and in the subsequent stage of the first process to the second process stage eliminate cross coupling interference estimation.
8.根据权利要求7所述的方法,其中估计交叉耦合系数与重构数据包括将所估计的交叉耦合系数用于所述第二处理阶段的后继情况,并且仅当未能重构所述数据时才重复所述第一处理阶段。 8. The method according to claim 7, wherein the cross coupling coefficient estimation and reconstruction data comprises the estimated cross coupling coefficient for the second case the subsequent processing stage, and only when the data fails to reconstruct when repeating the first process stage.
9.根据权利要求I所述的方法,其中存储数据包括使用纠错码(ECC)编码所述数据,其中重构数据包括基于所估计的交叉耦合系数计算纠错度量并且使用所述纠错度量解码所述ECC。 9. The method according to claim I, wherein the stored data comprises error correction code (ECC) encoding the data, wherein the reconstruction data comprises an error correction metric is calculated based on the estimated cross-coupling coefficient and using the error correction metric decoding the ECC.
10. 一种用于操作存储器的方法,包括: 将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中; 在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平; 估计交叉耦合系数,其通过处理所述第二电压电平而将所述模拟存储单元之间的交叉耦合干扰量化;以及使用所估计的交叉耦合系数,从所读取的第二电压电平重构存储在该组模拟存储单元中的数据。 10. A method for operating a memory, comprising: a first voltage corresponding to a data level stored in a set of analog memory cells of the memory; after storing the data read from the analog memory unit obtains the corresponding second voltage level, the influence of the second voltage level is subject to cross coupling interference, which causes the cross-coupled interference is different from the second voltage level corresponding to a first voltage level; cross coupling coefficient estimate that while the cross-coupling interference between the quantized analog memory unit by processing the second voltage level; and using the estimated cross-coupling coefficient, a second voltage level read from a reconfigurable memory in the group of analog data storing unit.
11.根据权利要求10所述的方法,还包括既基于读取自第一模拟存储单元的第二电压电平又基于读取自第二模拟存储单元的第二电压电平,估算在所述存储器中由所述第一模拟存储单元导致的针对所述第二模拟存储单元的交叉耦合干扰。 11. The method of claim 10, further comprising a second voltage level on both read from the storage unit and the first analog voltage level based on the second reading from the second analog memory cell, the estimate cross-coupled interference for the second analog memory means by the first analog memory cells results in a memory.
12. —种数据存储装置,包括: 接口,其操作性地与包含多个模拟存储单元的存储器通信;以及存储器信号处理器(MSP),其被耦合到所述接口并且被布置为:将数据作为选自可能的值的集合的相应的第一电压电平存储在一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平;处理所述第二电压电平以获得相应的硬判决,每个硬判决均对应于所述第一电压电平的可能的值中的相应值;基于所述第二电压电平和所述相应的硬判决估计交叉耦合系数,该交叉耦合系数量化所述模拟存储单元之间的交叉耦合干扰;以及使用所估计的交叉耦合系数,从所述第二电压电平重构存储在该组模拟存储单元中的数据。 12. - seed data storage means, comprising: an interface operative communication with a memory comprising a plurality of analog memory cells; a signal processor and a memory (the MSP), which is coupled to the interface and arranged to: Data may be selected as a value corresponding to a first voltage level in a set of stored set of analog memory cells; after storing the data, reads the corresponding second voltage level from said analog memory means of the Effects of two cross-coupled by the voltage level of interference, which causes the cross-coupled interference is different from the second voltage level corresponding to a first voltage level; processing the second voltage level to obtain the corresponding hard decision, each hard decision corresponds to the first voltage level corresponding values ​​of possible values; hard decision corresponding to the second voltage level based on the estimated cross-coupling coefficients, the coupling coefficient quantizing said analog cross cross-coupling interference between memory cells; and using the estimated cross-coupling coefficient data from the second voltage level is stored in the set of reconstructed analog memory cells.
13.根据权利要求12所述的装置,其中所述MSP被布置为:估计交叉耦合系数,包括使用块估计过程处理所述第二电压电平和所述相应的硬判决。 13. The apparatus according to claim 12, wherein the MSP is arranged to: estimate the cross-coupling coefficient estimation procedure using a block comprising processing the second voltage level and the corresponding hard decision.
14.根据权利要求12所述的装置,其中所述MSP被布置为:估计交叉耦合系数,包括使用收敛到所述交叉耦合系数的序列估计过程以循序扫描所述第二电压电平以及所述相应的硬判决。 14. The apparatus according to claim 12, wherein the MSP is arranged to: estimate the cross-coupling coefficients, including the use of sequence estimation converges to the cross-coupled coefficients during a sequential scan of the second voltage level and the the corresponding hard decision.
15.根据权利要求12所述的装置,其中所述MSP被布置为:采用减少在所读取的第二电压电平和所述相应的硬判决之间的距离度量的估计过程。 15. The apparatus according to claim 12, wherein the MSP is arranged to: reduce the second voltage level using the read level and the distance metric between the respective hard decision estimation process.
16.根据权利要求12所述的装置,其中所述MSP被布置为:既基于读取自第一模拟存储单元的第二电压电平,又基于读取自第二模拟存储单元的第二电压电平,估算在所述存储器中由所述第一模拟存储单元导致的针对所述第二模拟存储单元的交叉耦合干扰。 16. The apparatus according to claim 12, wherein the MSP is arranged to: either based on a second voltage level read from the first analog memory cell, and a second analog voltage based on the reading from the second storage unit level, cross-coupled interference estimate for the second analog memory cells in the memory caused by the first analog memory cells.
17.根据权利要求12所述的装置,其中所述MSP被布置为:使用如下过程之一将所述交叉耦合干扰从所述第二电压电平中除去,所述过程为:线性均衡过程、判决反馈均衡(DFE)过程、最大后验(MAP)估计过程以及最大似然序列估计(MLSE)过程。 17. The apparatus according to claim 12, wherein the MSP is arranged: to use one of the following processes the cross-coupled interference removing from the second voltage level, the process is: linear equalization process, decision feedback equalization (DFE) process, maximum a posteriori (MAP) estimation process and a maximum likelihood sequence estimation (MLSE) process.
18.根据权利要求12所述的装置,其中所述MSP被布置为:在第一处理阶段中估计所述交叉耦合系数,并且在后继于所述第一处理阶段的第二处理阶段中消除所估计的交叉耦合干扰。 The elimination of the cross-coupled coefficients estimated in a first process stage, and in the subsequent stage of the first process to the second process stage: 18. The apparatus of claim 12, wherein the MSP is arranged to cross-coupled estimated interference.
19.根据权利要求18所述的装置,其中所述MSP被布置为:将所估计的交叉耦合系数用于所述第二处理阶段的后继情况,并且仅当未能重构所述数据时才重复所述第一处理阶段。 When the estimated cross coupling coefficient for the second case the subsequent processing stage, and only when the data fails to reconstruct: 19. The apparatus according to claim 18, wherein the MSP is arranged to repeating the first process stage.
20.根据权利要求12所述的装置,其中所述MSP被布置为:在存储所述数据之前使用纠错码(ECC)编码所述数据,基于所估计的交叉耦合系数计算纠错度量,以及通过使用所述纠错度量解码所述ECC以重构所述数据。 20. The apparatus according to claim 12, wherein the MSP is arranged to: encode the data using an error correction code (ECC) prior to storing the data, an error correction metric is calculated based on the estimated cross-coupling coefficient, and by using the error correction decoding metric to reconstruct the data of the ECC.
21. 一种数据存储装置,包括:接口,其操作性地与包含多个模拟存储单元的存储器通信;以及存储器信号处理器(MSP),其被耦合到所述接口并且被布置为:将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平;估计交叉耦合系数,其通过处理所述第二电压电平而将所述模拟存储单元之间的交叉耦合干扰量化;以及使用所估计的交叉耦合系数,从所读取的第二电压电平重构存储在该组模拟存储单元中的数据。 21. A data storage apparatus, comprising: an interface operative communication with a memory comprising a plurality of analog memory cells; a signal processor and a memory (the MSP), which is coupled to the interface and arranged to: Data as a first voltage level corresponding to a set stored in the analog memory cells of the memory; after storing the data, reads the corresponding second analog voltage level from the storage unit, the second voltage level affected by cross coupling of interference, which causes the cross-coupled interference is different from the second voltage level corresponding to a first voltage level; cross coupling coefficient estimation, by processing the second voltage level and the cross-coupling interference between the quantized analog memory means; and using the estimated cross-coupling coefficient data reconstructed from the second voltage level stored in the set of the read analog memory cells.
22.根据权利要求21所述的装置,其中所述MSP被布置为:既基于读取自第一模拟存储单元的第二电压电平又基于读取自第二模拟存储单元的第二电压电平,估算在所述存储器中由所述第一模拟存储单元导致的针对所述第二模拟存储单元的交叉耦合干扰。 22. The apparatus according to claim 21, wherein the MSP is arranged to: either based on a read voltage level from the second storage unit and the first analog voltage based on the second reading from the second analog memory unit electrically flat, cross-coupled interference estimate for the second analog memory cells in the memory caused by the first analog memory cells.
23. 一种数据存储装置,包括: 存储器,其包含多个模拟存储单元;以及存储器信号处理器(MSP),其被耦合到所述存储器并且被布置为:将数据作为选自可能的值的集合的相应的第一电压电平存储在一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平;处理所述第二电压电平以获得相应的硬判决,每个硬判决都对应于所述第一电压电平的可能的值中的相应值;估计交叉耦合系数,其基于所述第二电压电平和所述相应的硬判决,对所述模拟存储单元之间的交叉耦合干扰进行量化;以及使用所述交叉耦合系数,从所述第二电压电平重构存储在该组模拟存储单元中的数据。 23. A data storage apparatus comprising: a memory comprising a plurality of analog memory cells; a signal processor and a memory (the MSP), which is coupled to the memory and arranged to: the selected data as possible values corresponding to a first voltage level in a set of stored set of analog memory cells; after storing the data, reads the corresponding second analog voltage level from the storage unit, the second voltage level being cross-coupled the effect of interference, which causes the cross-coupled interference is different from the second voltage level corresponding to a first voltage level; processing the second voltage level to obtain the corresponding hard decision, hard decision corresponds to each the possible values ​​of the respective values ​​of a first voltage level; estimating a cross coupling coefficient based on said second voltage level and the respective hard decisions, interference of cross-coupled between the analog memory unit quantization; and using the cross-coupling coefficient data from the second voltage level is stored in the set of reconstructed analog memory cells.
24. 一种数据存储装置,包括: 存储器,其包含多个模拟存储单元;以及存储器信号处理器(MSP),其被耦合到所述存储器并且被布置为:将数据作为相应的第一电压电平存储在所述存储器的一组模拟存储单元中;在存储所述数据之后,从所述模拟存储单元读取相应的第二电压电平,该第二电压电平受到交叉耦合干扰的影响,该交叉耦合干扰导致所述第二电压电平不同于所述相应的第一电压电平;估计交叉耦合系数,其通过处理所述第二电压电平而将所述模拟存储单元之间的交叉耦合干扰量化;以及使用所估计的交叉耦合系数,从所读取的第二电压电平重构存储在该组模拟存储单元中的数据。 24. A data storage apparatus comprising: a memory comprising a plurality of analog memory cells; a signal processor and a memory (the MSP), which is coupled to the memory and arranged to: a first data voltage corresponding to a a set of analog levels stored in the memory cells of the memory; after storing the data, reads the corresponding second voltage level from said analog memory unit, the second voltage level is affected by cross coupling of interference, this causes the cross-coupled interference is different from the second voltage level corresponding to a first voltage level; cross coupling coefficient estimation, by processing the second voltage level to the intersection between the analog memory unit coupling interference quantization; and using the estimated cross-coupling coefficient data reconstructed from the second voltage level stored in the set of the read analog memory cells.
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