CN112947664A - Temperature self-adaptive voltage source - Google Patents
Temperature self-adaptive voltage source Download PDFInfo
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- CN112947664A CN112947664A CN202110390784.3A CN202110390784A CN112947664A CN 112947664 A CN112947664 A CN 112947664A CN 202110390784 A CN202110390784 A CN 202110390784A CN 112947664 A CN112947664 A CN 112947664A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention relates to the technical field of semiconductor integrated circuits, and provides a self-adaptive voltage source for providing different voltage input temperatures under different working conditions, which comprises a first-stage voltage reduction circuit and a second-stage voltage reduction circuit which are cascaded, wherein the first-stage voltage reduction circuit comprises a low-voltage reference circuit and is used for reducing the voltage of a high-voltage input to obtain a low-voltage reference voltage output; the step-down voltage source power tube is used for obtaining output current; the second-stage voltage reduction circuit comprises a low-voltage reference circuit and is used for reducing the low-voltage reference voltage output by the first-stage voltage reduction circuit to obtain ultra-low-voltage reference voltage output; the step-down voltage source power tube is used for obtaining output current; the first-stage voltage reduction circuit and the second-stage voltage reduction circuit comprise MOS tubes.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a temperature self-adaptive voltage source.
Background
With the popularization of internet of things devices in a large number, wireless terminal nodes widely collect various physical information and transmit data through smart phones or other network nodes, and meanwhile, the energy obtained by the devices from batteries or external environments (such as solar energy) is very limited, and the requirements of people on the power consumption of chips and systems are becoming stricter and stricter.
Currently, in most application scenarios, the system generally includes functions of detecting, processing, storing, sending and receiving information, and the like, and will be in a sleep mode when the system is not in operation. Furthermore, as system performance increases, the time required for the system to perform detection and processing operations decreases, in contrast to the longest part of the system sleep mode time, as shown in fig. 1, and therefore the power consumption of the sleep mode will directly determine the device lifecycle. In the sleep mode, power is still required to be supplied to the memory in order to ensure that data in the memory is not lost; some bus controllers also need to poll devices and the like on the bus periodically, so that even in the sleep mode, current still exists in the chip, and the current of the chip is mainly divided into two parts, namely leakage current and dynamic current, so that the current of the chip needs to be reduced in order to reduce the power consumption of the chip in the sleep mode. The leakage current and the working voltage form an exponential relationship, and the dynamic current and the working voltage form a linear relationship, so how to provide a lower voltage source which ensures the normal operation of the circuit on the premise of low power consumption is the core for realizing the low power consumption of the system.
Disclosure of Invention
The invention aims to provide a temperature adaptive voltage source which can provide different voltage inputs under different working conditions.
The basic scheme provided by the invention is as follows: a temperature self-adaptive voltage source comprises a first-stage voltage reduction circuit and a second-stage voltage reduction circuit which are cascaded, wherein the first-stage voltage reduction circuit comprises a low-voltage reference circuit and is used for reducing the voltage of a high-voltage input to obtain a low-voltage reference voltage output; the first voltage reduction voltage source power tube is used for obtaining output current;
the second-stage voltage reduction circuit comprises an ultra-low voltage reference circuit and is used for reducing the low-voltage reference voltage output by the first-stage voltage reduction circuit to obtain ultra-low voltage reference voltage output; the second voltage reduction voltage source power tube is used for obtaining output current;
the first-stage voltage reduction circuit and the second-stage voltage reduction circuit comprise MOS tubes and are used for reducing output voltage along with temperature rise and increasing output voltage along with temperature fall.
Description of the drawings: when the circuit works, the temperature comprises the ambient temperature and the junction temperature, the junction temperature is the actual working temperature of a semiconductor in the electronic equipment, and the temperature in the scheme refers to the junction temperature.
The basic scheme has the working principle and the beneficial effects that: for a chip, when the chip is in normal operation, the high-speed operation capability is reduced at a higher temperature, and in order to ensure the high-speed operation capability at a high temperature, the voltage needs to be increased for the chip at the high temperature, so in the prior art, a high-voltage source is adopted to provide the chip with the operating voltage so as to ensure the normal operation of the chip. However, when the chip is in the sleep mode, even if the chip is also in a high temperature condition, only part of the low-power-consumption circuits in the chip are in an operating state because the low-power-consumption circuits do not need to perform data processing, operation and the like, and only one low voltage is needed for normal operation because the low-power-consumption circuits do not perform processing, operation and the like.
After a first-stage voltage reduction circuit and a second-stage voltage reduction circuit are cascaded, a high-voltage input by a high-voltage source is subjected to first voltage reduction by the first-stage voltage reduction circuit to obtain a low-voltage output, the low-voltage output of the first-stage voltage reduction circuit is used as the input of the second-stage voltage reduction circuit, and the low-voltage output is obtained after the voltage reduction is carried out again by the second-stage voltage reduction circuit, so that under the condition that the high-voltage source (namely, a voltage source meeting the normal working requirement of a chip) is not replaced, the power consumption of the chip in a dormant mode is reduced by reducing the input voltage at the moment, and the use efficiency of energy is also improved;
2. considering that most devices in a chip are transistors, and for the transistors, when the temperature rises, the forward junction voltage is reduced, that is, when the temperature rises, the power supply voltage required by the chip is reduced, the temperature is reduced, and the power supply voltage required by the chip is increased, therefore, in the scheme, the output voltage reduced by the first-stage voltage reduction circuit and the second-stage voltage reduction circuit is taken as the input voltage of the chip, and in the designed first-stage voltage reduction circuit and the second-stage voltage reduction circuit, the MOS tube has the characteristic that the threshold voltage is reduced along with the rise of the temperature, therefore, after the temperature rises, the output voltage reduced by the first-stage voltage reduction circuit and the second-stage voltage reduction circuit is reduced, that is, the voltage is provided at high temperature, and after the temperature falls, the obtained output voltage, that is, higher power supply is provided at low temperature, so that the temperature of the chip can be high, the required voltage is small, the temperature of the chip is low, and the required voltage is large, so that the output voltage in the scheme can follow the requirement of the chip on the voltage along with the temperature, and the purpose of temperature self-adaption is achieved.
Furthermore, the first-stage voltage reduction circuit adopts a high-voltage MOS tube, and the second-stage voltage reduction circuit adopts a low-voltage MOS tube. Because the input of the first step-down circuit is high-voltage input, a high-voltage MOS tube is adopted in the first step-down circuit to ensure the normal work of the first step-down circuit, and for the second step-down circuit, on one hand, because the input of the second-stage voltage reduction circuit is low-voltage input obtained by the voltage reduction of the first-stage voltage reduction circuit, on the other hand, because the power supply after the voltage reduction of the second-stage voltage reduction circuit is used as a low-voltage power supply voltage of a subsequent chip device, therefore, in the scheme, the second-stage voltage reduction circuit selects a low-voltage MOS tube which can be used at low voltage so as to ensure the normal work of the second-stage voltage reduction circuit, after the low-voltage MOS tube is selected, when a subsequent chip device selects an MOS device consistent with the low-voltage MOS tube used in the second-stage voltage reduction circuit, the voltage obtained through voltage reduction can follow the deviation introduced in the process.
Further, the low-voltage reference circuit comprises a first NMOS tube and a first PMOS tube, wherein the source electrode of the first NMOS tube is connected with the input end, the grid electrode of the first NMOS tube is connected with the output end of the first step-down voltage source power tube, the drain electrode of the first NMOS end is connected with the source electrode of the first PMOS tube, the grid electrode of the first PMOS tube is in short circuit with the drain electrode, and the drain electrode of the first PMOS tube is connected with the grounding end.
Furthermore, the first step-down voltage source power tube is a second NMOS tube, the grid electrode of the second NMOS tube is connected with the input end, the source electrode of the second NMOS tube is in short circuit with the grid electrode, and the drain electrode of the second NMOS tube is connected with the grid electrode of the first NOMS tube.
Further, the MOS tube adopts a 40nm process.
In the invention, the NMOS tube and the PMOS tube are adopted to form the Voltage reduction circuit, and the MOS tube has the characteristics of Temperature rise, threshold Voltage reduction, Temperature reduction and threshold Voltage rise, so that the power supply Voltage provided for the chip is increased at low Temperature, the power supply Voltage provided for the chip is lower at high Temperature, the margin required for ensuring the normal work of the PVT (Process, Voltage and Temperature) of the chip is reduced, the typic case and the power supply Voltage at room Temperature are reduced, the power consumption of a low-power module is further reduced, the distribution range of different core power consumption sizes of the chip is reduced, and the yield of the chip is improved.
And because in the existing technology, even if the same batch of chips produced, therefore the technology is different in the production process, just can lead to the chip to be different, therefore to different operating conditions, the required operating voltage of chip is just also different, on the contrary, to same operating voltage, to current chip, can be under this operating voltage chip that can normally work be the yields, and in this scheme, because output voltage follows the technology change, when the voltage of typical technology angle of design is less than the required voltage of slow technology angle, actual slow technology angle chip voltage can obtain certain compensation, thereby can improve the yield of chip.
Description of the drawings: the chip needs to adapt to the varying temperature and voltage within its application range, and needs to withstand the manufacturing process variations, which needs to be taken into account in the design implementation, i.e. PVT.
Corner: the process corner, the variation range of the MOSFETs parameters between different wafers and different batches is relatively large. To alleviate the design difficulties, it is necessary to limit the device performance to a certain range and reject chips beyond this range to tightly control the expected parameter variations. The process corner is this performance range.
typic case: typic, typical; case, case specific; example (2); examples; actual conditions; (ii) a fact; special cases.
Drawings
FIG. 1 is a schematic diagram of a first step-down circuit in an embodiment of a temperature adaptive voltage source according to the present invention;
FIG. 2 is a schematic diagram of a second stage buck circuit in an embodiment;
fig. 3 is a schematic diagram of a cascade of a first stage voltage reduction circuit and a second stage voltage reduction circuit.
Detailed Description
The following is further detailed by way of specific embodiments:
reference numerals in the drawings of the specification include: a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first PMOS transistor PM1, and a second PMOS transistor PM 2.
The embodiment is substantially as shown in figure 3: a temperature self-adaptive voltage source comprises a first-stage voltage reduction circuit and a second-stage voltage reduction circuit which are cascaded, in the figure 3, the left part of a dotted line is the first voltage reduction circuit, the right part of the dotted line is the second voltage reduction circuit, the first-stage voltage reduction circuit comprises a low-voltage reference circuit and is used for reducing the voltage of high-voltage input to obtain low-voltage reference voltage output; the first voltage reduction voltage source power tube is used for obtaining output current;
the second-stage voltage reduction circuit comprises an ultra-low voltage reference circuit and is used for reducing the low-voltage reference voltage output by the first-stage voltage reduction circuit to obtain ultra-low voltage reference voltage output; and the second voltage reduction voltage source power tube is used for obtaining output current.
The first-stage voltage reduction circuit and the second-stage voltage reduction circuit comprise MOS tubes and are used for reducing output voltage along with temperature rise and increasing output voltage along with temperature fall.
Specifically, as shown in fig. 1, the low-voltage reference circuit in the first-stage buck circuit includes a first NMOS transistor and a first PMOS transistor, a source of the first NMOS transistor is connected to the input terminal, a gate of the first NMOS transistor is connected to an output terminal of the first buck voltage source power transistor, a drain of the first NMOS transistor is connected to a source of the first PMOS transistor, a gate of the first PMOS transistor is shorted to the drain, and a drain of the first PMOS transistor is connected to the ground terminal, where the first buck voltage source power transistor is a second NMOS transistor, a gate of the second NMOS transistor is connected to the input terminal, a source of the second NMOS transistor is shorted to the gate, and a drain of the second NMOS transistor is connected to a gate of the first NMOS transistor.
As shown in fig. 2, the ultra-low voltage reference circuits in the second-stage voltage-reducing circuit each include a third NMOS transistor and a second PMOS transistor, a source of the third NMOS transistor is connected to the input terminal, a gate of the third NMOS transistor is connected to the output terminal of the first voltage-reducing voltage source power transistor, a drain of the third NMOS transistor is connected to a source of the second PMOS transistor, a gate of the second PMOS transistor is shorted to the drain, and a drain of the second PMOS transistor is connected to the ground terminal, wherein the second voltage-reducing voltage source power transistor is a fourth NMOS transistor, a gate of the fourth NMOS transistor is connected to the input terminal, a source of the fourth NMOS transistor is shorted to the gate, and a drain of the fourth NMOS transistor is connected to a gate of the third NMOS transistor.
After the first-stage voltage reduction circuit and the second-stage voltage reduction circuit are cascaded, the output of the first-stage voltage reduction circuit is used as the input of the second-stage voltage reduction circuit. And the first NMOS tube, the second NMOS tube and the first PMOS tube in the first-stage voltage reduction circuit are high-voltage MOS tubes, and the third NMOS tube, the fourth NMOS tube and the second PMOS tube in the second-stage voltage reduction circuit are low-voltage MOS tubes.
The specific implementation process is as follows: when the chip is in a dormant state, the chip triggers the high-voltage power supply VDDH to be switched into the temperature self-adaptive voltage source in the embodiment, and the high-voltage power supply VDDH is input as the first-stage voltage reduction circuit.
The high-voltage power supply VDDH is subjected to voltage reduction by the first-stage voltage reduction circuit to obtain a low-voltage output VDDL, and the VDDL is VGS_PM1+VGS_NM1(ii) a Then the low-voltage output VDDL obtained by the first-stage voltage-reducing circuit is used as the input of the second-stage voltage-reducing circuit, the voltage is reduced by the second-stage voltage-reducing circuit to obtain the ultra-low-voltage output VREG, and the ultra-low-voltage output VREG provides ultra-low-voltage for the chip at the momentGS_PM2+VGS_NM3. Specifically, in the embodiment, the high-voltage power supply VDDH is 2.1-3.6V, and the ultra-low-voltage transmission obtained after the high-voltage power supply VDDH passes through the first-stage voltage reduction circuit and the second-stage voltage reduction circuitThe VREG is 0.4-0.8V.
Due to the temperature characteristic of the MOS tube, V can be known when the temperature risesGS_PM1、VGS_NM1、VGS_PM2、VGS_NM3All decrease, i.e. VREG decreases, as the temperature decreases, VGS_PM1、VGS_NM1、VGS_PM2、VGS_NM3Become larger, i.e., VREG becomes larger, thereby enabling the voltage source in this embodiment to provide different voltage outputs with temperature changes, thereby accommodating different temperature conditions.
The foregoing is merely an example of the present invention, and common general knowledge in the field of known specific structures and characteristics is not described herein in any greater extent than that known in the art at the filing date or prior to the priority date of the application, so that those skilled in the art can now appreciate that all of the above-described techniques in this field and have the ability to apply routine experimentation before this date can be combined with one or more of the present teachings to complete and implement the present invention, and that certain typical known structures or known methods do not pose any impediments to the implementation of the present invention by those skilled in the art. It should be noted that, for those skilled in the art, without departing from the structure of the present invention, several changes and modifications can be made, which should also be regarded as the protection scope of the present invention, and these will not affect the effect of the implementation of the present invention and the practicability of the patent. The scope of the claims of the present application shall be determined by the contents of the claims, and the description of the embodiments and the like in the specification shall be used to explain the contents of the claims.
Claims (6)
1. A temperature adaptive voltage source, comprising: the voltage-reducing circuit comprises a first-stage voltage-reducing circuit and a second-stage voltage-reducing circuit which are cascaded, wherein the first-stage voltage-reducing circuit comprises a low-voltage reference circuit and is used for reducing the voltage of high-voltage input to obtain low-voltage reference voltage output; the first voltage reduction voltage source power tube is used for obtaining output current;
the second-stage voltage reduction circuit comprises an ultra-low voltage reference circuit and is used for reducing the low-voltage reference voltage output by the first-stage voltage reduction circuit to obtain ultra-low voltage reference voltage output; the second voltage reduction voltage source power tube is used for obtaining output current;
the first-stage voltage reduction circuit and the second-stage voltage reduction circuit comprise MOS tubes and are used for reducing output voltage along with temperature rise and increasing output voltage along with temperature fall.
2. The temperature adaptive voltage source of claim 1, wherein: the first-stage voltage reduction circuit adopts a high-voltage MOS tube, and the second-stage voltage reduction circuit adopts a low-voltage MOS tube.
3. The temperature adaptive voltage source of claim 1, wherein: the MOS tube adopts an MOS device which is the same as a chip device in an application system.
4. The temperature adaptive voltage source of claim 1, wherein: the low-voltage reference circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube and a first PMOS (P-channel metal oxide semiconductor) tube, wherein the source electrode of the first NMOS tube is connected with the input end, the grid electrode of the first NMOS tube is connected with the output end of the first step-down voltage source power tube, the drain electrode of the first NMOS end is connected with the source electrode of the first PMOS tube, the grid electrode of the first PMOS tube is in short circuit with the drain electrode, and the drain electrode of the first PMOS tube is connected with the grounding end.
5. The temperature adaptive voltage source of claim 4, wherein: the first step-down voltage source power tube is a second NMOS tube, the grid electrode of the second NMOS tube is connected with the input end, the source electrode of the second NMOS tube is in short circuit with the grid electrode, and the drain electrode of the second NMOS tube is connected with the grid electrode of the first NOMS tube.
6. The temperature adaptive voltage source of claim 1, wherein: the MOS tube adopts a 40nm process.
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| CN202110390784.3A CN112947664A (en) | 2021-04-12 | 2021-04-12 | Temperature self-adaptive voltage source |
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| CN202110390784.3A CN112947664A (en) | 2021-04-12 | 2021-04-12 | Temperature self-adaptive voltage source |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113364287A (en) * | 2021-06-23 | 2021-09-07 | 深圳市矽塔科技有限公司 | Integrated power supply control circuit applied to high-voltage grid driving chip |
| CN114253342A (en) * | 2022-01-26 | 2022-03-29 | 北京信息科技大学 | Voltage stabilizing circuit and amplifying circuit |
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| CN109308089A (en) * | 2017-07-28 | 2019-02-05 | 原相科技股份有限公司 | With the reference voltage generator and IC chip for adapting to voltage |
| CN110858082A (en) * | 2018-08-24 | 2020-03-03 | 新唐科技股份有限公司 | Single transistor controlled voltage stabilizer and integrated circuit using same |
| CN112327990A (en) * | 2020-11-06 | 2021-02-05 | 电子科技大学 | Output voltage adjustable low-power consumption sub-threshold reference voltage generating circuit |
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2021
- 2021-04-12 CN CN202110390784.3A patent/CN112947664A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20110031955A1 (en) * | 2009-08-05 | 2011-02-10 | Advanced-Connectek, Inc. | Constant current device |
| CN101860202A (en) * | 2010-05-12 | 2010-10-13 | 海洋王照明科技股份有限公司 | Buck chopper circuit, LED drive circuit and LED lamp |
| CN109308089A (en) * | 2017-07-28 | 2019-02-05 | 原相科技股份有限公司 | With the reference voltage generator and IC chip for adapting to voltage |
| CN107526386A (en) * | 2017-08-28 | 2017-12-29 | 天津大学 | Reference voltage source with high PSRR |
| CN110858082A (en) * | 2018-08-24 | 2020-03-03 | 新唐科技股份有限公司 | Single transistor controlled voltage stabilizer and integrated circuit using same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113364287A (en) * | 2021-06-23 | 2021-09-07 | 深圳市矽塔科技有限公司 | Integrated power supply control circuit applied to high-voltage grid driving chip |
| CN114253342A (en) * | 2022-01-26 | 2022-03-29 | 北京信息科技大学 | Voltage stabilizing circuit and amplifying circuit |
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Application publication date: 20210611 |