CN217034617U

CN217034617U - Self-adaptive ultralow static power consumption leakage bleeder circuit

Info

Publication number: CN217034617U
Application number: CN202122574451.4U
Authority: CN
Inventors: 赵冬; 何洋; 赵文广; 其他发明人请求不公开姓名
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd; Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd; Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2021-10-25
Filing date: 2021-10-25
Publication date: 2022-07-22
Anticipated expiration: 2031-10-25

Abstract

The utility model provides a self-adaptive ultralow static power consumption leakage bleeder circuit, which comprises an error amplifier EA, a PMOS power tube MP1, a PMOS tube MP2, a PMOS tube MP3 and a PMOS tube MP4, wherein the positive phase input end of the error amplifier EA is connected with a feedback voltage VFB, the negative phase input end of the error amplifier EA is connected with a reference voltage VREF, the source electrode of the PMOS power tube MP1 is connected with an input voltage VDD, the drain electrode of the PMOS power tube MP1 is connected with a divider resistor string RF1 and a divider resistor string RF2, and the grid electrode of the PMOS power tube MP1 is connected with the output end of the error amplifier; according to the self-adaptive ultralow-power-consumption leakage bleeder circuit, the PMOS tube MP2, the PMOS tube MP3 and the PMOS tube MP4 form the self-adaptive ultralow-power-consumption leakage bleeder circuit, the problem that the circuit cannot form normal negative feedback due to overlarge leakage of the PMOS power tube MP1 when the LDO under the whole process angle, temperature and voltage is in a no-load state is solved, and in a normal state, the circuit formed by the PMOS tube MP2, the PMOS tube MP3 and the PMOS tube MP4 is in a cut-off state and has ultralow static power consumption.

Description

Self-adaptive ultralow static power consumption leakage bleeder circuit

Technical Field

The utility model relates to the field of semiconductor integrated circuit design, in particular to an ultra-low power consumption self-adaptive leakage bleeder circuit.

Background

With the continuous development of the semiconductor integrated circuit industry, various power management chips have been developed, among which, low dropout linear regulators (LDO) have the obvious characteristics of simple structure, high stability, small voltage ripple, small size, etc., and are therefore integrated in various chips, some of which are applied under high temperature conditions, such as aerospace field, automobile field, military industry field, energy field, etc., which usually require that the chips operate under different environmental temperatures, some of which can even reach 180 ℃, under such high temperature environment, the power tube of the LDO will generate a large leakage current, if the leakage current of the LDO is greater than the load current, the function of the feedback loop of the LDO will be destroyed, causing malfunction of the LDO, the conventional leakage solution is to connect a reverse biased diode between the output of the LDO and the ground to achieve the purpose of absorbing the leakage current tube, however, due to process variations, the matching between the diode and the power transistor is not good, and the ability of the diode to absorb leakage current may be poor.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide an ultra-low power consumption self-adaptive leakage bleeder circuit, which solves the problem that the feedback loop of the LDO is damaged when the LDO is in no load due to overlarge leakage in the high-temperature environment.

The technical solution of the present invention to achieve the above object is that, a self-adaptive ultra-low static power leakage bleeder circuit, which is characterized in that the circuit includes an error amplifier EA, a PMOS power transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, and a PMOS transistor MP4, wherein a positive phase input terminal of the error amplifier EA is connected to a feedback voltage VFB, a negative phase input terminal thereof is connected to a reference voltage VREF, a source of the PMOS power transistor MP1 is connected to an input voltage VDD, a drain thereof is connected to a divider resistor string RF1 and a divider resistor string RF2, and a gate thereof is connected to an output terminal of the error amplifier.

Furthermore, the drain of the PMOS power transistor MP1 is connected to the source of the PMOS transistor MP2, the gate of the PMOS transistor MP2 is connected to the drain, the source of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP2, the gate of the PMOS transistor MP3 is connected to the drain, the source of the PMOS transistor MP4 is connected to the drain of the PMOS transistor MP3, the gate of the PMOS transistor MP4 is connected to the drain, and the drain of the PMOS transistor MP4 is connected to ground.

Furthermore, the substrates of the PMOS tube MP2, the PMOS tube MP3 and the PMOS tube MP4 are all connected with the drain electrode of the PMOS power tube MP 1.

Different from the traditional electric leakage solution, the scheme has the distinct technical advantages that: the scheme is simple in structure, the three PMOS tubes which are the same as the PMOS power tube MP1 in type are used for DIODE connection, the problem of electric leakage of a no-load LDO under the conditions of a full process angle, temperature and voltage is solved, and the three PMOS tubes are in a cut-off state under a normal state and have the characteristic of ultra-low power consumption.

Drawings

Fig. 1 is a schematic diagram of a circuit structure for adaptive ultra-low static power leakage discharging according to the present invention.

Detailed Description

The following detailed description of the embodiments of the present invention is provided in connection with the accompanying drawings for the purpose of understanding and controlling the technical solutions of the present invention, so as to define the protection scope of the present invention more clearly.

The utility model discloses a leakage discharge circuit, which is invented by a designer aiming at the problems that a PMOS (P-channel metal oxide semiconductor) power tube of an LDO (low dropout regulator) can generate large leakage at high temperature, and the large leakage does not leave a place to cause current to be accumulated on a load capacitor all the time when the LDO is in idle load, so that the output voltage of the LDO is increased to a power supply voltage all the time, the loop stability of the LDO is damaged, and the LDO loses the function of loop feedback.

Referring to fig. 1, in the adaptive leakage current relief circuit with ultra-low static power consumption in this embodiment, the leakage current relief circuit includes an error amplifier EA, a PMOS power transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, and a PMOS transistor MP4, a positive phase input end of the error amplifier EA is connected to a feedback voltage VFB, a negative phase input end of the error amplifier EA is connected to a reference voltage VREF, a source of the PMOS power transistor MP1 is connected to an input voltage VDD, a drain of the PMOS power transistor MP1 is connected to a divider resistor string RF1 and a divider resistor string RF2, and a gate of the PMOS power transistor MP is connected to an output end of the error amplifier.

In one embodiment, the drain of the PMOS power transistor MP1 is connected to the source of the PMOS transistor MP2, the gate of the PMOS transistor MP2 is connected to the drain, the source of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP2, the gate of the PMOS transistor MP3 is connected to the drain, the source of the PMOS transistor MP4 is connected to the drain of the PMOS transistor MP3, the gate of the PMOS transistor MP4 is connected to the drain, the drain of the PMOS transistor MP4 is connected to ground, and the substrates of the PMOS transistor MP2, the PMOS transistor MP3, and the PMOS transistor MP4 are connected to the drain of the PMOS power transistor MP 1.

The working principle of the leakage current relief circuit is explained as follows:

the PMOS power transistor MP1, the PMOS transistor MP2, the PMOS transistor MP3, and the PMOS transistor MP4 are all of the same type, so that it is ensured that the threshold voltages of the four PMOS transistors are changed synchronously at different process angles, temperatures, and voltages, in a normal state, the drain output VOUT of the PMOS power transistor MP1 is 1.5V, the threshold voltages of the PMOS transistors MP2, MP3, and MP4 are between 0.58V and 0.63V, the PMOS transistors MP2, MP3, and the corresponding VGS2, VGS3, and VGS4 of the PMOS transistors MP4 are all smaller than their threshold voltages Vth, so that the leakage current discharging circuit is in a cut-off state, and when in a high temperature environment, according to the PMOS transistor drain current formula:

it can be known that V_thWhen the temperature is increased and decreased, the leakage current of the PMOS power transistor MP1 increases, and the PMOS power transistor MP2,The leakage bleeder circuit composed of PMOS tube MP3 and PMOS tube MP4 is characterized in that V is arranged between the PMOS tube MP3 and the PMOS tube MP4_thIn addition, the substrates of the PMOS tube MP2, the PMOS tube MP3 and the PMOS tube MP4 are all connected to the drain of the PMOS power tube, and the larger the substrate voltage of the PMOS tube is, the larger the threshold voltage is, so that the leakage circuit under the whole process angle is ensured to be in a cut-off state under the normal state.

It will be apparent to those skilled in the art that the examples herein are capable of carrying out the utility model in other specific forms without departing from the spirit or essential characteristics thereof. The present examples are to be considered as illustrative and not restrictive, the scope of the utility model being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein, and any reference signs in the claims should not be construed as limiting the claim concerned.

Claims

1. The self-adaptive ultralow static power consumption leakage bleeder circuit is characterized by comprising an error amplifier EA, a PMOS power tube MP1, a PMOS tube MP2, a PMOS tube MP3 and a PMOS tube MP4, wherein the positive phase input end of the error amplifier EA is connected with a feedback voltage VFB, the negative phase input end of the error amplifier EA is connected with a reference voltage VREF, the source electrode of the PMOS power tube MP1 is connected with an input voltage VDD, the drain electrode of the PMOS power tube MP1 is connected with a divider resistor string RF1 and a divider resistor string RF2, the grid electrode of the PMOS power tube MP1 is connected with the output end of the error amplifier EA, the drain electrode of the PMOS tube MP2 is connected with the grid electrode of the PMOS tube MP2, the source electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP3 is connected with the drain electrode, the source electrode of the PMOS tube MP4 is connected with the drain electrode of the PMOS tube MP3, the grid electrode of the PMOS tube MP4 is connected with the drain electrode of the PMOS tube MP4 is connected with the ground.

2. The adaptive ultra-low static power leakage bleeder circuit of claim 1, wherein: the substrates of the PMOS tube MP2, the PMOS tube MP3 and the PMOS tube MP4 are all connected with the drain electrode of the PMOS power tube MP 1.