CN112928165A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112928165A CN112928165A CN201911236816.3A CN201911236816A CN112928165A CN 112928165 A CN112928165 A CN 112928165A CN 201911236816 A CN201911236816 A CN 201911236816A CN 112928165 A CN112928165 A CN 112928165A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- H01L21/205—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: forming a substrate and an initial pattern layer positioned on the substrate, wherein the initial pattern layer is formed by utilizing an etching process; and forming a covering layer on the side wall of the initial pattern layer by using a plasma deposition process, wherein the initial pattern layer and the covering layer are used as pattern layers. In the process of forming the covering layer on the side wall of the initial pattern layer by utilizing the plasma deposition process, the plasma generated by the deposition process can remove the dangling bond on the side wall of the initial pattern layer, so that the side wall of the initial pattern layer has smaller surface roughness, and the covering layer is formed on the side wall of the initial pattern layer, therefore, the side wall surface roughness of the pattern layer is smaller, and the covering layer is formed by the plasma deposition process, so that the surface of the covering layer does not have the dangling bond, and the side wall of the covering layer is not easy to contact with water, O and H in the environment to form the dangling bond, therefore, the surface roughness of the side wall of the pattern layer is smaller, and the improvement of the electrical.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that a sub-threshold leakage (SCE) phenomenon, which is a so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; the gate structure is also shifted from the original polysilicon gate structure to a metal gate structure, and the work function layer in the metal gate structure can adjust the threshold voltage of the semiconductor structure.
In the working process of the semiconductor structure, the source-drain doped layers on the two sides of the grid structure provide stress for the channel, and the migration rate of current carriers in the channel is improved.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, and electrical properties of a device are improved.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a substrate and an initial pattern layer positioned on the substrate, wherein the initial pattern layer is formed by utilizing an etching process; and forming a covering layer on the side wall of the initial pattern layer by using a plasma deposition process, wherein the initial pattern layer and the covering layer are used as pattern layers.
Optionally, the initial pattern layer is made of monocrystalline silicon, polycrystalline silicon or amorphous silicon, and the covering layer is made of monocrystalline silicon, polycrystalline silicon or amorphous silicon.
Optionally, the etching process is a dry etching process.
Optionally, the plasma deposition process includes a direct current superimposed plasma process or a plasma enhanced atomic layer deposition process.
Optionally, the plasma deposition process is a direct current superimposed plasma process, and process parameters of the direct current superimposed plasma process include: the pressure of the chamber is 4mTorr to 50mTorr, the source power is 100W to 1000W, the bias power is 0W to 500W, the DC voltage is 0V to 1200V, and the adopted reaction gases comprise fluorocarbon gas and N2Ar and H2One or more of (a).
Optionally, in the step of forming the covering layer, the thickness of the covering layer is 0.5 nm to 3 nm.
Optionally, in the step of forming a substrate and an initial pattern layer on the substrate, the initial pattern layer is an initial fin portion; in the step of forming a covering layer on the side wall of the initial pattern layer, the initial pattern layer and the covering layer on the side wall of the initial pattern layer are used as the pattern layer, and the pattern layer is used as a fin portion.
Optionally, after the initial pattern layers are formed and before the covering layer is formed, forming an isolation layer on the substrate between the initial pattern layers, where the isolation layer covers part of the sidewalls of the initial pattern layers; in the step of forming the covering layer on the side wall of the initial pattern layer, the covering layer conformally covers the initial fin part exposed by the isolation layer and the top of the isolation layer; after the covering layer is formed, the method further comprises the following steps: removing the capping layer on top of the isolation layer.
Optionally, the step of removing the cover layer on top of the isolation layer includes: and oxidizing the covering layer on the top of the isolation layer by adopting an anisotropic oxidation process to form an oxide layer.
Optionally, the parameters of the anisotropic oxidation process include: the reaction gas comprises oxygen, and the source power is 300W to 1000W; the pressure is 4mTorr to 100mTorr, the bias power is 0 to 500W, and the flow rate of the reaction gas is 50sccm to 500 sccm.
Optionally, in the step of forming a substrate and an initial pattern layer on the substrate, the initial pattern layer is an initial core layer; in the step of forming a covering layer on the side wall of the initial pattern layer, the covering layer conformally covers the initial pattern layer and the substrate between the initial pattern layer, the initial pattern layer and the covering layer positioned on the side wall of the initial pattern layer are used as pattern layers, and the pattern layers are core layers.
Optionally, the method for forming the semiconductor structure further includes: after the graphic layer is formed, forming a side wall material layer which conformally covers the graphic layer; removing the side wall material layer on the substrate between the top of the graphic layer and the graphic layer, wherein the rest side wall material layer on the side wall of the graphic layer is used as a side wall layer; after the side wall layer is formed, removing the graphic layer; and after removing the pattern layer, etching the substrate by taking the side wall layer as a mask to form a residual substrate and a target pattern on the residual substrate.
Optionally, the target pattern is a fin portion or a gate structure.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the initial pattern layer is positioned on the substrate and is formed by utilizing an etching process; and the covering layer is positioned on the side wall of the initial pattern layer, the covering layer is formed by a plasma deposition process, and the initial pattern layer and the covering layer are used as pattern layers.
Optionally, the plasma deposition process includes: a direct current superimposed plasma process or a plasma enhanced atomic layer deposition process.
Optionally, the initial pattern layer is made of monocrystalline silicon, polycrystalline silicon or amorphous silicon, and the covering layer is made of monocrystalline silicon, polycrystalline silicon or amorphous silicon.
Optionally, the thickness of the cover layer is 0.5 nm to 3 nm.
Optionally, the initial graphics layer is an initial core layer, and the graphics layer is a core layer; or the initial graphic layer is an initial fin part, and the graphic layer is a fin part; or, the initial graphic layer is an initial gate structure, and the graphic layer is a gate structure.
Optionally, the initial pattern layer is an initial fin portion; the semiconductor structure further includes: the isolation layer is positioned on the substrate between the initial graphic layers and covers partial side walls of the initial graphic layers; the covering layer covers the side wall of the initial pattern layer exposed out of the isolation layer, and the pattern layer is a fin portion.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the initial pattern layer is formed by an etching process, usually, in the etching process, a dangling bond formed by the etching process exists on the side wall of the initial pattern layer, and the macroscopic representation is that the surface roughness of the side wall of the initial pattern layer is larger; in the process of forming the covering layer on the side wall of the initial pattern layer by using the plasma deposition process, the plasma generated by the deposition process can remove dangling bonds on the side wall of the initial pattern layer, so that the side wall of the initial pattern layer has smaller surface roughness, the covering layer is formed on the side wall of the initial pattern layer, therefore, the side wall surface roughness of the pattern layer is smaller, and the covering layer is formed by the plasma deposition process, therefore, the surface of the covering layer does not have dangling bonds, so that the side wall of the covering layer is not easy to contact with water, O and H in the environment to form dangling bonds, and the surface roughness of the side wall of the pattern layer is smaller, thereby being beneficial to improving the electrical property of the semiconductor structure.
Drawings
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 6 to 11 are schematic structural views corresponding to steps in a first embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 12 to 14 are schematic structural diagrams corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Fig. 1 to 5 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure.
As shown in fig. 1, a base is provided, which comprises an initial substrate 1 and a layer of core material 2 on the initial substrate 1.
As shown in fig. 2, the core material layer 2 is etched to form a core layer 3.
As shown in fig. 3 and 4, conformally covering the core layer 3 and the initial substrate 1 with the exposed core layer 3 with a side wall material layer 4; removing the side wall material layer 4 on the core layer 3 and on the surface of the initial substrate 1, and taking the remaining side wall material layer 4 on the side wall of the core layer 3 as a side wall layer 5; after the side wall layers 5 are formed, the core layer 3 is removed.
As shown in fig. 5, the initial substrate 1 is etched by using the sidewall layer 5 as a mask, so as to form a substrate 6 and a fin portion 7 located on the substrate 6.
The core layer 3 is formed by etching the core material layer 2 by using a dry etching process, in order to improve the integration level of an integrated circuit, improve the working speed of a device and reduce the power consumption of the device, the characteristic size of a semiconductor process is continuously reduced, the influence of the surface roughness of the side wall of the core layer 3 on the surface roughness of the side wall of the fin portion 6 cannot be ignored, the surface roughness of the side wall of the core layer 3 is large, the surface roughness of the side wall layer 5 formed on the side wall of the core layer 3 is large, and further the surface roughness of the side wall of the fin portion 7 formed subsequently is large, so that the electrical performance of a semiconductor structure is improved.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a substrate and an initial pattern layer positioned on the substrate, wherein the initial pattern layer is formed by utilizing an etching process; and forming a covering layer on the side wall of the initial pattern layer by using a plasma deposition process, wherein the initial pattern layer and the covering layer are used as pattern layers.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the initial pattern layer is formed by an etching process, usually, in the etching process, a dangling bond formed by the etching process exists on the side wall of the initial pattern layer, and the macroscopic representation is that the surface roughness of the side wall of the initial pattern layer is larger; in the process of forming the covering layer on the side wall of the initial pattern layer by using the plasma deposition process, the plasma generated by the deposition process can remove dangling bonds on the side wall of the initial pattern layer, so that the side wall of the initial pattern layer has smaller surface roughness, the covering layer is formed on the side wall of the initial pattern layer, therefore, the side wall surface roughness of the pattern layer is smaller, and the covering layer is formed by the plasma deposition process, therefore, the surface of the covering layer does not have dangling bonds, so that the side wall of the covering layer is not easy to contact with water, O and H in the environment to form dangling bonds, and the surface roughness of the side wall of the pattern layer is smaller, thereby being beneficial to improving the electrical property of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 6 to 11 are schematic structural diagrams corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the present invention.
Referring to fig. 6 and 7, a substrate 100 and an initial pattern layer 101 (shown in fig. 7) on the substrate 100 are formed, and the initial pattern layer 101 is formed using an etching process.
The substrate 100 provides a process foundation for the subsequent formation of a target pattern. In this embodiment, the formed semiconductor structure is a fin field effect transistor (FinFET), and the corresponding target pattern is a fin portion. In other embodiments, the target pattern to be formed subsequently may also be a gate structure.
In this embodiment, the substrate 100 is made of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. Components, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, inductors, or the like, can also be formed within the substrate.
The initial pattern layer 101 provides a process foundation for the subsequent formation of the capping layer.
Specifically, the initial graphics layer 101 is an initial core layer.
The material of the initial pattern layer 101 is monocrystalline silicon, polycrystalline silicon or amorphous silicon. In other embodiments, the initial pattern layer can also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like.
Specifically, the steps of forming the substrate 100 and the initial pattern layer 101 on the substrate 100 include:
as shown in fig. 6, a base is provided, and the base includes a substrate 100, a core material layer 102 on the substrate 100, and a core mask layer on the core material layer 102.
The layer of core material 102 provides for the subsequent formation of an initial core layer.
Specifically, the material of the core material layer 102 includes one or both of silicon and amorphous silicon.
In the subsequent process, the core mask layer is used as an etching mask for etching the core material layer 102.
In this embodiment, the core mask layer adopts a tri-layer mask (tri-layer mask) technology, that is, the core mask layer includes an organic dielectric layer 103, an anti-reflective coating 104 on the organic dielectric layer 103, and a photoresist layer 105 on the anti-reflective coating 104. Compared with a single-layer photoresist mask, the core mask layer is not easy to fall off, so that rework is not needed, and the pattern transfer precision is improved. The process of forming the core mask layer is a process commonly used in the semiconductor field, and the description of this embodiment is omitted here.
In this embodiment, the photoresist layer 105 is formed by a patterning process.
In this embodiment, the organic dielectric layer 103 is made of a SOC (spin on carbon) material. The SOC material has the advantages of low cost, simple forming process and high process compatibility. In other embodiments, the material of the organic dielectric layer may also be an Organic Dielectric Layer (ODL) material, or a Deep ultraviolet Absorbing Oxide (DUO) material.
In this embodiment, the material of the anti-reflective coating 104 includes: BARC (bottom-reflective coating) material, DARC (dielectric anti-reflective coating) material.
The substrate further comprises: a layer of substrate masking material (not shown) is located between the substrate 100 and the initial pattern layer 101.
In the subsequent step of etching the core material layer 102 to form the initial pattern layer 101, the substrate mask material layer is used as an etching stop layer, thereby protecting the substrate 100.
In addition, the hardness of the substrate mask material layer is greater than that of the substrate 100, so that the surface roughness of the side wall of the substrate mask layer formed by subsequently etching the substrate mask material layer is smaller, and the surface roughness of a target pattern formed by subsequently etching the substrate by taking the pattern layer and the substrate mask layer as masks is smaller.
In this embodiment, the material of the substrate mask material layer includes one or more of SiN, SiON, SiOC, and metal oxide. In this embodiment, the material of the substrate mask material layer includes SiN, which is a dielectric material with a common process and low cost, and has high process compatibility, thereby being beneficial to reducing the process difficulty and process cost for forming the substrate mask material layer.
As shown in fig. 7, the core material layer 102 is etched using the core mask layer as a mask to form an initial pattern layer 101.
In this embodiment, the initial graphics layer 101 is an initial core layer. The initial graphics layer 101 is ready for subsequent formation of the graphics layer.
In this embodiment, the core mask layer is used as a mask, and the core material layer 102 is dry-etched to form the initial pattern layer 101. The dry etching process is an anisotropic etching process, has good etching profile controllability, and is beneficial to making the surface roughness of the side wall of the initial pattern layer 101 smaller.
It should be noted that, in the step of forming the initial pattern layer 101 by using the dry etching process, the etching rate of the substrate mask material layer is less than the etching rate of the core material layer 102, and the top surface of the substrate mask material layer is used to define an etching stop position, so that the forming rates of the initial pattern layers 101 in the respective regions are easily consistent. In addition, the substrate masking material layer can also function to protect the substrate 100.
It should be noted that, after the core material layer 102 is etched by using a dry etching process to form the initial pattern layer 101, a large number of unstable Si — Si bonds exist on the sidewall of the initial pattern layer 101, and the macro representation indicates that the surface roughness of the sidewall of the initial pattern layer 101 is high.
Referring to fig. 8, a capping layer 106 is formed on sidewalls of the preliminary pattern layer 101 using a plasma deposition process, and the preliminary pattern layer 101 and the capping layer 106 serve as a pattern layer 107.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the initial pattern layer 101 is formed by an etching process, usually, in the etching process, a dangling bond formed by the etching process exists on the side wall of the initial pattern layer 101, and the macroscopic representation is that the surface roughness of the side wall of the initial pattern layer 101 is larger; in the process of forming the covering layer 106 on the side wall of the initial pattern layer 101 by using a plasma deposition process, the plasma generated by the deposition process can remove dangling bonds on the side wall of the initial pattern layer 101, so that the side wall of the initial pattern layer 101 has smaller surface roughness, the covering layer 106 is formed on the side wall of the initial pattern layer 101, therefore, the surface roughness of the side wall of the pattern layer 107 is smaller, and the covering layer is formed by using the plasma deposition process, therefore, the surface of the covering layer does not have dangling bonds, so that the side wall of the covering layer is not easy to react with water, O and H in the air to form dangling bonds, and the surface roughness of the side wall of the pattern layer 107 is smaller, thereby being beneficial to improving the electrical property of the semiconductor structure.
In the step of forming the overlay layer 106 on the sidewall of the preliminary pattern layer 101, the overlay layer 106 conformally covers the preliminary pattern layer 101 and the substrate 100 between the preliminary pattern layers 101, the preliminary pattern layer 101 and the overlay layer 106 on the sidewall of the preliminary pattern layer 101 are used as pattern layers, and the pattern layer 107 is a core layer.
In this embodiment, the material of the cover layer 106 is the same as that of the initial pattern layer 101. The material of the capping layer 106 is the same as that of the preliminary pattern layer 101, and thus the electrical characteristics of the entire material of the pattern layer 107 can be formed to be the same as those of the entire material of the preliminary pattern layer 101 while reducing the surface roughness of the sidewall of the preliminary pattern layer 101.
Specifically, the material of the covering layer 106 is monocrystalline silicon, polycrystalline silicon or amorphous silicon.
Specifically, the Plasma deposition process includes a direct current additive deposition technology (DCST) or a Plasma Enhanced Atomic Layer Deposition (PEALD).
In this embodiment, the plasma deposition process is a direct current superimposed plasma process. In the process of forming the covering layer 106 by adopting the direct current superimposed plasma process, the generated plasma can remove the dangling bond on the side wall of the initial pattern layer 101, and the macroscopic representation is that the surface roughness of the side wall of the initial pattern layer 101 is relatively reduced.
Specifically, the step of forming the capping layer 106 by using the dc additive plasma process includes: arranging a silicon-containing target at the positive pole of direct current voltage in a chamber, applying the direct current voltage in the chamber, introducing reaction gas into the chamber, ionizing the reaction gas in the chamber to form plasma, wherein the plasma can remove dangling bonds on the side wall of the initial pattern layer 101, the plasma bombards the silicon-containing target under the action of the direct current voltage, atoms bombarded from the silicon-containing target are deposited on the side wall and the top wall of the initial pattern layer 101, the thickness of the atomic deposition on the side wall of the initial pattern layer 101 is approximately consistent with that of the atomic deposition on the top wall of the initial pattern layer 101, and the deposition on the side wall of the initial pattern layer 101 is used as the covering layer 106.
It should be noted that, in the process of forming the capping layer 106 by using the dc-additive plasma process, the chamber pressure should not be too high or too low. If the chamber pressure is too low, the deposition rate of the atoms bombarded from the silicon-containing target material is too fast, which tends to cause the thickness of the capping layer 106 formed on the top wall of the initial pattern layer 101 to be larger than that of the capping layer 106 on the side wall of the initial pattern layer 101, and thus the quality of the formation of the capping layer 106 is poor. If the chamber pressure is too high, the deposition rate of the bombarded atoms in the silicon-containing target material is too slow, which tends to result in too slow a formation rate of the cap layer 106. In this embodiment, the chamber pressure is 4mTorr to 50mTorr during the formation of the cap layer 106 using a DC additive plasma process.
It should be noted that, in the process of forming the capping layer 106 by using the dc additive plasma process, the Source power (Source power) should not be too high or too low. If the source power is too high, the density of the plasma in the chamber is high, and accordingly, the deposition process of the atoms bombarded from the silicon-containing target material is susceptible to the plasma moving toward the chamber anode, resulting in poor uniformity of the thickness of the formed capping layer 106. If the source power is too low, the density of plasma ionized in the chamber is low, and correspondingly, the deposition rate of atoms bombarded from the silicon-containing target material is too slow, resulting in low efficiency of forming the capping layer 106. In this embodiment, the source power is 100W to 1000W.
It should be noted that, in the process of forming the capping layer 106 by using the dc additive plasma process, the bias power (bias power) should not be too large or too small. If the bias power is too large, the energy obtained by the plasma is too large, and the deposition process of the atoms bombarded from the silicon-containing target material is susceptible to the plasma moving to the chamber anode, so that the thickness uniformity of the formed covering layer 106 is poor. In this embodiment, the bias power is less than 500W.
It should be noted that, in the process of forming the capping layer 106 by using the dc-additive plasma process, the dc voltage is not too high. If the dc voltage is too large, the plasma is likely to act on the dc voltage, so that the energy of the plasma is too large, and the deposition rate of atoms bombarded from the silicon-containing target material is too fast, which is likely to cause the formation rate of the cap layer 106 to be too fast. In this embodiment, the dc voltage is less than 1200V.
In this embodiment, the reaction gas includes fluorocarbon gas and N2Ar and H2One or more of (a).
The overlay layer 106 serves to block O, H in the environment and water from contacting the original pattern layer 101 after removal of the dangling bonds, so that the formed pattern layer 107 is not prone to dangling bonds on its sidewalls.
It should be noted that, in the step of forming the covering layer 106, the covering layer 106 is not too thick or too thin. And forming a conformal side wall material layer covering the pattern layer 107 and the substrate 100 between the pattern layers 107, removing the top wall of the pattern layer 107 and the side wall material layer on the surface of the substrate 100, forming a side wall layer on the side wall of the pattern layer 107, and etching the covering layer 106 on the substrate 100 in the process of forming the side wall layer. If the capping layer 106 is too thick, the process time for forming the capping layer 106 may be increased, which may waste too much process material, and may also result in too long process time for subsequently etching the capping layer 106 on the substrate 100. If the cover layer 106 is too thin, the cover layer 106 cannot well block O, H in the environment and water from contacting the original pattern layer 101 after the dangling bonds are removed, which easily results in the formation of dangling bonds on the side walls of the formed pattern layer 107, and the macro representation is that the surface roughness of the side walls of the pattern layer 107 is large. In this embodiment, the thickness of the covering layer 106 is 0.5 nm to 3 nm.
As shown in fig. 9 and 10, the method for forming the semiconductor structure further includes: after the pattern layer 107 is formed, forming a side wall material layer 108 which conformally covers the pattern layer 107 and the substrate 100 between the pattern layers 107; the side wall material layer 108 on the substrate 100 between the top of the pattern layer 107 and the pattern layer 107 is removed, and the remaining side wall material layer 108 on the side wall of the pattern layer 107 is used as a side wall layer 109 (as shown in fig. 9).
The sidewall layer 109 is used as an etching mask for subsequent etching of the substrate 100 to form a target pattern. The side wall of the pattern layer 107 has a smaller surface roughness, and the side wall layer 109 is formed on the side wall of the pattern layer 107, so that the side wall of the side wall layer 109 has a smaller surface roughness, and the roughness of a target pattern formed by etching the substrate 100 with the side wall layer 109 as a mask is smaller.
Specifically, the material of the sidewall material layer 108 includes: one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon nitride, and boron nitride silicon carbide. In this embodiment, the material of the sidewall material layer 108 is silicon nitride.
In this embodiment, the sidewall material Layer 108 is formed by an Atomic Layer Deposition (ALD) process. The ald process includes performing a plurality of ald cycles to form a sidewall material layer 108 of a desired thickness. The gap filling performance and the step coverage performance of the atomic layer deposition process are good, the conformal coverage capability of the side wall material layer 108 is improved, and because the surface roughness of the side wall of the initial pattern layer 101 is small, the side wall surface roughness of the side wall material layer 108 on the side wall of the pattern layer 107 is small, and the side wall surface roughness of the corresponding subsequently formed side wall layer 109 is small; in other embodiments, other deposition processes may be further used to form the side wall material layer, for example: plasma chemical vapor deposition processes, and the like.
In this embodiment, the sidewall material layer 108 on the substrate 100 and between the pattern layers 107 and the top of the pattern layer 107 are removed by a dry etching process to form a sidewall layer 109. Specifically, the side wall material layer 108 is etched by using a maskless dry etching process, the dry etching process has the characteristic of anisotropic etching, and a photomask (Mask) is not needed in the step of forming the side wall layer 109, so that the process cost is reduced. The top end of the pattern layer 107 and the side wall material layer 108 on the substrate 100 are also removed completely, and meanwhile, the side wall material layer 108 is prevented from being etched transversely, so that the roughness of the side wall surface of the formed side wall layer 109 is small.
The method for forming the semiconductor structure further comprises the following steps: after the side wall layer 109 is formed, the core layer 110 is removed.
Removing the core layer 110 prepares for subsequent etching of the substrate 100 with the sidewall layer 109 as a mask to form a target pattern.
In this embodiment, the core layer 103 is removed by a dry etching process. The dry etching process has an anisotropic etching characteristic, and in the step of removing the core layer 103, the lateral etching of the sidewall layer 109 is not easy to perform, so that the roughness of the sidewall surface of the sidewall layer 109 is small. And in the process of removing the core layer 103 by adopting a dry etching process, the substrate mask material layer can be used as an etching stop layer.
Specifically, the etching gas used in the step of removing the core layer 110 includes NF3And H2。
It should be noted that, during the process of etching the sidewall material layer 108 to form the sidewall layer 109 and the process of removing the core layer 103, the substrate mask material layer is more difficult to be etched, and the substrate mask material layer plays a role of stopping etching, so as to well protect the substrate 100.
It should be further noted that, in the process of etching the sidewall material layer 108 by using a dry etching process to form the sidewall layer 109, the covering layer 106 is also etched, so that the covering layer 106 is also formed at the bottom of the sidewall layer 109.
As shown in fig. 11, after the core layer 110 is removed, the substrate 100 is etched by using the sidewall layer 109 as a mask, so as to form a residual substrate 110 and a target pattern 111 located on the residual substrate 110.
The target pattern 111 is prepared for subsequent formation of a semiconductor structure. The side wall surface roughness of the side wall layer 109 is small, so that the surface roughness of the side wall of the target pattern formed by etching the substrate 100 by using the side wall layer 109 as a mask is small.
In this embodiment, the target pattern 111 is a fin portion. In other embodiments, the target pattern may also be a gate structure, and specifically, the gate structure is a polysilicon gate structure.
In this embodiment, the substrate 100 is etched by using the sidewall layer 109 as a mask and using a dry etching process to form a target pattern 111. The dry etching process is an anisotropic etching process, has good etching profile controllability, is favorable for making the surface roughness of the side wall of the target pattern 111 smaller, and is also favorable for improving the removal efficiency of the substrate 100.
The method for forming the semiconductor structure further includes: before the substrate 100 is etched by taking the side wall layer 109 as a mask, the substrate mask material layer is etched by taking the side wall layer 109 as a mask to form a substrate mask layer.
Therefore, in the step of etching the substrate 100 to form the target pattern 111, the substrate mask layer, the covering layer 106 and the sidewall layer 109 are used together as an etching mask for etching the substrate 100.
Fig. 12 to 14 are schematic structural views corresponding to respective steps in a second embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 12, a substrate 200 and an initial pattern layer 201 on the substrate 200 are formed, wherein the initial pattern layer 201 is formed by using an etching process.
The substrate 200 provides a process foundation for subsequently forming semiconductor structures.
In this embodiment, the substrate 200 is made of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The initial pattern layer 201 provides a process foundation for the subsequent formation of the capping layer.
In this embodiment, the formed semiconductor structure is a fin field effect transistor (FinFET) as an example, the initial pattern layer 201 is an initial fin portion, and the initial pattern layer 201 is prepared for forming a fin portion subsequently.
In this embodiment, the material of the initial pattern layer 201 is monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the material of the initial pattern layer may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The steps of forming the substrate 200 and the initial pattern layer 201 include: providing a substrate (not shown); forming a mask layer (not shown) on the substrate; and etching the base by taking the mask layer as a mask to form a substrate 200 and an initial pattern layer 201 positioned on the substrate 200.
In this embodiment, the substrate is etched by using the mask layer as a mask and using a dry etching process to form the substrate 200 and the initial pattern layer 201. The dry etching process is an anisotropic etching process, has good etching profile controllability, is favorable for making the surface roughness of the side wall of the initial pattern layer 201 smaller, and is also favorable for improving the removal efficiency of the substrate.
The method for forming the semiconductor structure further comprises the following steps: after the formation of the initial pattern layers 201 and before the formation of the cover layer, an isolation layer 202 is formed on the substrate 200 between the initial pattern layers 201, and the isolation layer 202 covers a part of the sidewall of the initial pattern layers 201.
The isolation layer 202 is used to electrically isolate adjacent initial pattern layers 201.
In this embodiment, the material of the isolation layer 202 includes silicon oxide. The silicon oxide is a dielectric material which is common in process and low in cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 202; in addition, the smaller dielectric constant of silicon oxide is beneficial to improve the function of the subsequent isolation layer 202 for isolating adjacent devices.
The step of forming the isolation layer 202 includes: forming an isolation material layer (not shown) on the initial pattern layer 201 and the substrate 200, wherein the top of the isolation material layer is higher than the top of the mask layer; carrying out planarization treatment on the isolation material layer; after the planarization treatment, the isolation material layer with a certain thickness is etched back to form an isolation layer 202, and the isolation layer 202 covers a part of the sidewall of the initial pattern layer 201.
In this embodiment, the isolation material layer is formed by a Flowable Chemical Vapor Deposition (FCVD) process. The flowable chemical vapor deposition process has good filling capability, is suitable for filling openings with high aspect ratios, is favorable for reducing the probability of defects such as cavities and the like in the isolation material layer, and is correspondingly favorable for improving the film forming quality of the isolation layer 202.
It should be noted that, in the process of performing planarization treatment on the isolation material layer, the mask layer is removed.
Referring to fig. 13, a capping layer 203 is formed on sidewalls of the preliminary pattern layer 201 using a plasma deposition process, and the preliminary pattern layer 201 and the capping layer 203 serve as a pattern layer 205.
In the embodiment of the invention, the initial pattern layer 201 is formed by an etching process, and in the etching process, a dangling bond formed by the etching process exists on the side wall of the initial pattern layer 201, and the macro representation is that the surface roughness of the side wall of the initial pattern layer 201 is larger; in the process of forming the covering layer 203 on the side wall of the initial pattern layer 201 by using a plasma deposition process, the plasma generated by the deposition process can remove dangling bonds on the side wall of the initial pattern layer 201, so that the side wall of the initial pattern layer 201 has smaller surface roughness, the covering layer 203 is formed on the side wall of the initial pattern layer 201, therefore, the side wall surface roughness of the pattern layer 205 is smaller, and the covering layer 203 is formed by the deposition process, therefore, the surface of the covering layer 203 does not have dangling bonds, so that the side wall of the covering layer 203 is not easy to contact with water, O and H in the environment to form dangling bonds, and the surface roughness of the side wall of the pattern layer 205 is smaller, thereby being beneficial to improving the electrical property of the semiconductor structure.
In the step of forming the covering layer 203 on the sidewall of the initial pattern layer 201, the initial pattern layer 201 and the covering layer 203 on the sidewall of the initial pattern layer 201 are used as the pattern layer 205, and the pattern layer 205 is used as a fin portion.
Specific process parameters for forming the covering layer 203 on the sidewall of the initial pattern layer 201 are not described herein with reference to the first embodiment.
It should be noted that, in the step of forming the covering layer 203 on the sidewall of the initial pattern layer 201, the covering layer 203 conformally covers the initial fin portion exposed by the isolation layer 202 and the top of the isolation layer 202.
Referring to fig. 14, the method for forming the semiconductor structure further includes: after the forming of the covering layer 203, the method further includes: the cover layer 203 on top of the isolation layer 202 is removed.
The subsequent steps further comprise: and forming a gate structure crossing the fin part. By removing the capping layer 203 on top of the isolation layer 202, preparation is made for the subsequent formation of a gate structure.
The step of removing the cover layer 203 on top of the isolation layer 202 comprises: the capping layer 203 on top of the isolation layer 202 is oxidized using an anisotropic oxidation process to form an oxide layer 206.
It should be noted that, during the process of performing the oxidation treatment on the capping layer 203 on the top of the isolation layer 202 by using the anisotropic oxidation process, the capping layer 203 on the top of the initial pattern layer 201 is also oxidized into the oxide layer 206.
In this embodiment, the material of the covering layer 203 is single crystal silicon, polycrystalline silicon or amorphous silicon. Correspondingly, the capping layer 203 on top of the isolation layer 202 is oxidized, and the material of the oxide layer 206 is silicon oxide. The silicon oxide is a dielectric material which is common in process and low in cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 202; in addition, the smaller dielectric constant of silicon oxide is beneficial to improve the function of the subsequent isolation layer 202 for isolating adjacent devices.
In this embodiment, the parameters of the anisotropic oxidation process include: the reaction gas comprises oxygen, and the source power is 300W to 1000W; the pressure is 4mTorr to 100mTorr, the bias power is 0 to 500W, and the flow rate of the reaction gas is 50sccm to 500 sccm.
In the process of the anisotropic oxidation process, oxygen gas introduced into the chamber is converted into plasma, and the covering layer 203 on the top of the isolation layer 202 is bombarded by using the plasma formed by the oxygen gas, so that the covering layer 203 on the top of the isolation layer 202 is oxidized.
During the anisotropic oxidation process, the chamber pressure should not be too high or too low. If the pressure of the chamber is too low, the speed of oxygen ions formed by plasmatizing oxygen is too fast, and the oxygen ions easily etch the covering layer 203 on the surface of the isolation layer 202 and a part of the thickness of the isolation layer 202, so that the thickness of the isolation layer 202 is too thin, and adjacent devices cannot be well isolated. If the chamber pressure is too high, the oxygen ions formed by the ionization of oxygen tend to move isotropically, i.e., the capping layer 203 on the sidewalls of the fin 201 is oxidized. In this embodiment, the chamber pressure is between 4mTorr and 100mTorr during the anisotropic oxidation process.
During the anisotropic oxidation process, the source power should not be too high or too low. If the source power is too high, the oxidation uniformity of the capping layer 203 on the surface of the isolation layer 202 in the chamber is poor, resulting in poor uniformity of the subsequently formed semiconductor device. If the source power is too low, the density of plasma ionized in the chamber is low, and accordingly, the oxidation rate of the cap layer 203 on the surface of the isolation layer 202 is low. In this embodiment, the source power is 300W to 1000W.
In the process of the anisotropic oxidation process, the bias power is not too large or too small. If the bias power is too large, the ionization-formed oxygen ions are likely to obtain too large energy, and the oxygen ions are likely to etch the covering layer 203 on the surface of the isolation layer 202 and the isolation layer 202 with a part of thickness, so that the thickness of the isolation layer 202 is too thin, and adjacent devices cannot be well isolated. In this embodiment, the bias power is less than 500W.
During the anisotropic oxidation process, the flow of the reaction gas should not be too large or too small. If the flow rate of the reaction gas is too large, the oxidation uniformity of the capping layer 203 on the surface of the isolation layer 202 in each position in the chamber is poor, which results in poor uniformity of the subsequently formed semiconductor device. If the flow rate of the reaction gas is too small, the density of plasma formed by ionization in the chamber is likely to be low, and accordingly, the oxidation rate of the cover layer 203 on the surface of the isolation layer 202 is low. In this embodiment, the flow rate of the reaction gas is 50sccm to 500 sccm.
It should be noted that, in other embodiments, in the step of forming the covering layer on the sidewall of the initial pattern layer, the covering layer conformally covers the initial fin portion and the substrate; after the covering layer is formed, forming an isolation layer on the substrate between the pattern layers, wherein the isolation layer covers partial side walls of the pattern layers; after the isolation layer is formed, the covering layer on the top of the isolation layer is removed.
The material of the initial pattern layer comprises monocrystalline silicon, polycrystalline silicon or amorphous silicon, and the material of the covering layer also comprises the monocrystalline silicon, the polycrystalline silicon or the amorphous silicon. After the covering layer is formed, the isolation layer is formed, so that the isolation layer can better isolate adjacent fin parts.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 8, a schematic diagram of a first embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; an initial pattern layer 101, located on the substrate 100, the initial pattern layer 101 being formed by using an etching process; and the covering layer 106 is positioned on the side wall of the initial pattern layer 101, the covering layer 106 is formed by a plasma deposition process, and the initial pattern layer 101 and the covering layer 106 are used as a pattern layer 107.
In the semiconductor structure provided by the embodiment of the invention, the initial pattern layer 101 is formed by an etching process, and in the etching process, a dangling bond formed by the etching process exists on the side wall of the initial pattern layer 101, and the macro representation is that the surface roughness of the side wall of the initial pattern layer 101 is larger; the covering layer 106 is formed on the side wall of the initial pattern layer 101 by using a plasma deposition process, plasma generated in the plasma deposition process can remove dangling bonds on the side wall of the initial pattern layer 101, so that the side wall of the initial pattern layer 101 has smaller surface roughness, the covering layer 106 is formed on the side wall of the initial pattern layer 101, therefore, the surface roughness of the side wall of the pattern layer 107 is smaller, and the covering layer is formed by the plasma deposition process, so that the surface of the covering layer does not have dangling bonds, and therefore, the side wall of the covering layer is not easy to react with water, O and H in the air to form dangling bonds, the surface roughness of the side wall of the pattern layer 107 is smaller, and the electrical performance of a semiconductor structure is improved.
The substrate 100 provides a process foundation for the formation of semiconductor structures. In this embodiment, the formed semiconductor structure is a fin field effect transistor (FinFET), and the corresponding target pattern is a fin portion. In other embodiments, the target pattern to be formed subsequently may also be a gate structure.
In this embodiment, the substrate 100 is made of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. Components, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, inductors, or the like, can also be formed within the substrate 100.
In this embodiment, the initial graphics layer 101 is an initial core layer. In other embodiments, the initial graphic layer may also be an initial gate structure.
The material of the initial pattern layer 101 is monocrystalline silicon, polycrystalline silicon or amorphous silicon. In other embodiments, the initial pattern layer can also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like.
The semiconductor structure further includes: a layer of substrate masking material (not shown) is located between the substrate 100 and the initial pattern layer 101.
Specifically, the initial pattern layer 101 is formed by etching a core material layer (not shown in the figure), and during the process of forming the initial pattern layer 101 by etching, the etching rate of the substrate mask material layer is smaller than that of the core material layer, so that the substrate mask material layer is used as an etching stop layer, thereby protecting the substrate 100.
In this embodiment, the material of the substrate mask material layer includes one or more of SiN, SiON, SiOC, and metal oxide. In this embodiment, the material of the substrate mask material layer includes SiN, which is a dielectric material with a common process and low cost, and has high process compatibility, thereby being beneficial to reducing the process difficulty and process cost for forming the substrate mask material layer.
The overlay layer 106 serves to block O, H in the environment and water from contacting the original pattern layer 101 after removal of the dangling bonds, so that the formed pattern layer 107 is not prone to dangling bonds on its sidewalls.
The capping layer 106 is formed by a plasma deposition process. Specifically, the plasma deposition process comprises: a direct current superimposed plasma process or a plasma enhanced atomic layer deposition process.
Specifically, the dangling bonds on the side wall of the initial pattern layer 101 can be removed by plasma generated in the plasma deposition process, the plasma bombards the silicon-containing target under the action of direct-current voltage, atoms bombarded from the silicon-containing target are deposited on the side wall and the top wall of the initial pattern layer 101, the thickness of the atomic deposition on the side wall of the initial pattern layer 101 is approximately consistent with that of the atomic deposition on the top wall of the initial pattern layer 101, and the deposition on the side wall of the initial pattern layer 101 is used as the covering layer 106.
It should be noted that the cover layer 106 is also formed on the substrate 100 between the initial pattern layers 101.
The original graphics layer 101 and the overlay layer 106 located at the sidewall of the original graphics layer 101 serve as graphics layers. In this embodiment, the graphics layer 107 is a core layer. In other embodiments, the graphic layer may be a gate structure.
In this embodiment, the material of the cover layer 106 is the same as that of the initial pattern layer 101. The material of the capping layer 106 is the same as that of the preliminary pattern layer 101, and thus the electrical characteristics of the entire material of the pattern layer 107 can be formed to be the same as those of the entire material of the preliminary pattern layer 101 while reducing the surface roughness of the sidewall of the preliminary pattern layer 101.
Specifically, the material of the covering layer 106 is monocrystalline silicon, polycrystalline silicon or amorphous silicon.
It should be noted that the cover layer 106 is not too thick or too thin. If the capping layer 106 is too thick, the process time for forming the capping layer 106 is easily increased, and excessive process materials are wasted. If the cover layer 106 is too thin, the cover layer 106 cannot well block O, H in the environment and water from contacting the original pattern layer 101 after the dangling bonds are removed, which easily results in the formation of dangling bonds on the side walls of the formed pattern layer 107, and the macro representation is that the surface roughness of the side walls of the pattern layer 107 is large. In this embodiment, the thickness of the covering layer 106 is 0.5 nm to 3 nm.
Referring to fig. 13, a schematic diagram of a second embodiment of the semiconductor structure of the present invention is shown.
The same points of the semiconductor structure of the present invention as those of the first embodiment will not be described herein again, and the differences from the first embodiment are: in this embodiment, the initial pattern layer 201 is an initial fin portion.
The semiconductor structure further includes: an isolation layer 202 on the substrate 100 between the initial pattern layers 201, wherein the isolation layer 202 covers a part of the sidewalls of the initial pattern layers 201.
The isolation layer 202 is used to electrically isolate adjacent initial pattern layers 201, that is, the isolation layer 202 is used to electrically isolate adjacent initial fins.
In this embodiment, the material of the isolation layer 202 includes silicon oxide. The silicon oxide is a dielectric material which is common in process and low in cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 202; in addition, the smaller dielectric constant of silicon oxide is beneficial to improve the function of the subsequent isolation layer 202 for isolating adjacent devices.
The covering layer 203 covers the sidewalls of the initial pattern layer exposed from the isolation layer 202, and the pattern layer 205 is a fin portion.
The semiconductor structure of this embodiment may be formed by the formation method described in the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
forming a substrate and an initial pattern layer positioned on the substrate, wherein the initial pattern layer is formed by utilizing an etching process;
and forming a covering layer on the side wall of the initial pattern layer by using a plasma deposition process, wherein the initial pattern layer and the covering layer are used as pattern layers.
2. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the capping layer, a material of the capping layer is the same as a material of the initial pattern layer.
3. The method of claim 1 or 2, wherein the material of the capping layer is single crystal silicon, polycrystalline silicon, or amorphous silicon.
4. The method of forming a semiconductor structure of claim 1, wherein the etching process is a dry etching process.
5. The method of claim 1, wherein the plasma deposition process comprises a direct current additive plasma process or a plasma enhanced atomic layer deposition process.
6. The method of claim 1, wherein the plasma deposition process is a dc-additive plasma process, and process parameters of the dc-additive plasma process comprise: the pressure of the chamber is 4mTorr to 50mTorr, the source power is 100W to 1000W, the bias power is 0W to 500W, the DC voltage is 0V to 1200V, and the adopted reaction gases comprise fluorocarbon gas and N2Ar and H2One or more of (a).
7. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the capping layer, the capping layer has a thickness of 0.5 nm to 3 nm.
8. The method of claim 1, wherein in the step of forming a substrate and an initial pattern layer on the substrate, the initial pattern layer is an initial fin;
in the step of forming a covering layer on the side wall of the initial pattern layer, the initial pattern layer and the covering layer on the side wall of the initial pattern layer are used as the pattern layer, and the pattern layer is used as a fin portion.
9. The method of forming a semiconductor structure of claim 8, wherein after forming the preliminary pattern layers and before forming the capping layer, forming an isolation layer on the substrate between the preliminary pattern layers, the isolation layer covering a portion of sidewalls of the preliminary pattern layers;
in the step of forming the covering layer on the side wall of the initial pattern layer, the covering layer conformally covers the initial fin part exposed by the isolation layer and the top of the isolation layer;
after the covering layer is formed, the method further comprises the following steps: removing the capping layer on top of the isolation layer.
10. The method of forming a semiconductor structure of claim 9, wherein removing the capping layer on top of the isolation layer comprises: and oxidizing the covering layer on the top of the isolation layer by adopting an anisotropic oxidation process to form an oxide layer.
11. The method of forming a semiconductor structure of claim 10, wherein the parameters of the anisotropic oxidation process comprise: the reaction gas comprises oxygen, and the source power is 300W to 1000W; the pressure is 4mTorr to 100mTorr, the bias power is 0 to 500W, and the flow rate of the reaction gas is 50sccm to 500 sccm.
12. The method of forming a semiconductor structure of claim 1, wherein in the step of forming a substrate and an initial pattern layer on the substrate, the initial pattern layer is an initial core layer;
in the step of forming a covering layer on the side wall of the initial pattern layer, the covering layer conformally covers the initial pattern layer and the substrate between the initial pattern layer, the initial pattern layer and the covering layer positioned on the side wall of the initial pattern layer are used as pattern layers, and the pattern layers are core layers.
13. The method of forming a semiconductor structure of claim 12, further comprising: after the graphic layer is formed, forming a side wall material layer which conformally covers the graphic layer;
removing the side wall material layer on the substrate between the top of the graphic layer and the graphic layer, wherein the rest side wall material layer on the side wall of the graphic layer is used as a side wall layer;
after the side wall layer is formed, removing the graphic layer;
and after removing the pattern layer, etching the substrate by taking the side wall layer as a mask to form a residual substrate and a target pattern on the residual substrate.
14. The method of claim 13, wherein the target feature is a fin or a gate structure.
15. A semiconductor structure, comprising:
a substrate;
the initial pattern layer is positioned on the substrate and is formed by utilizing an etching process;
and the covering layer is positioned on the side wall of the initial pattern layer, the covering layer is formed by a plasma deposition process, and the initial pattern layer and the covering layer are used as pattern layers.
16. The semiconductor structure of claim 15, wherein the plasma deposition process comprises: a direct current superimposed plasma process or a plasma enhanced atomic layer deposition process.
17. The semiconductor structure of claim 15, wherein a material of the initial pattern layer is the same as a material of the capping layer.
18. The semiconductor structure of claim 15 or 17, wherein the material of the initial pattern layer is single crystal silicon, polycrystalline silicon, or amorphous silicon, and the material of the capping layer is single crystal silicon, polycrystalline silicon, or amorphous silicon.
19. The semiconductor structure of claim 15, wherein the capping layer has a thickness of 0.5 nm to 3 nm.
20. The semiconductor structure of claim 15, wherein the initial graphics layer is an initial core layer, the graphics layer being a core layer;
or the initial graphic layer is an initial fin part, and the graphic layer is a fin part;
or, the initial graphic layer is an initial gate structure, and the graphic layer is a gate structure.
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| CN201911236816.3A CN112928165B (en) | 2019-12-05 | 2019-12-05 | Semiconductor structure and forming method thereof |
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