CN112913032B - Semiconductor device and power conversion device - Google Patents

Semiconductor device and power conversion device Download PDF

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Publication number
CN112913032B
CN112913032B CN201880098434.6A CN201880098434A CN112913032B CN 112913032 B CN112913032 B CN 112913032B CN 201880098434 A CN201880098434 A CN 201880098434A CN 112913032 B CN112913032 B CN 112913032B
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layer
semiconductor device
trench
insulating layer
type
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CN112913032A (en
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伊藤正尚
古桥壮之
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
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    • H01L29/0692—Surface layout
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    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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Abstract

The semiconductor device according to the present invention includes a semiconductor region having a1 st main surface, the semiconductor region including: the n-type column layers and the p-type column layers are alternately arranged along the 1 st main surface; the p-type 1 st well layer is arranged in the n-type column layer and on the upper surface of the n-type column layer; the n-type 1 st source electrode layer is arranged in the 1 st well layer and on the upper surface of the 1 st well layer; the 1 st side insulating layer is arranged on the side surface in the 1 st groove arranged at the boundary of the n-type column layer and the p-type column layer and is connected with the 1 st well layer and the 1 st source electrode layer; the 1 st bottom surface insulating layer is arranged on the bottom surface in the 1 st groove, and at least one part of the bottom surface insulating layer is connected with the p-type column layer; and a1 st gate electrode disposed in the 1 st trench, facing the 1 st well layer and the 1 st source layer through the 1 st side insulating layer, and facing the p-type column layer through the 1 st bottom insulating layer.

Description

Semiconductor device and power conversion device
Technical Field
The present invention relates to a semiconductor device and a power conversion device.
Background
In the field of power electronics, switching elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide-semiconductor field effect transistors) and IGBTs (insulated gate bipolar transistors) are used to drive loads of motors such as motors. These switching elements are operated by switching on states of low resistance and off states of high resistance by inputting control signals. In power electronics applications, it is important that these switching elements have a high withstand voltage in the off state in order to handle high voltage inputs. The high withstand voltage is generally maintained by expanding the depletion layer to the drift layer. The thicker the drift layer, the higher the withstand voltage can be obtained, and the lower the impurity concentration of the drift layer, the wider the depletion layer width, so that the higher the withstand voltage can be obtained.
On the other hand, in order to reduce conduction loss in the on state, low resistance is required. The resistance of the drift layer is one of the resistance components of the on-resistance, and is desirably as low as possible. The resistance of the drift layer can be reduced by reducing the thickness of the drift layer or increasing the impurity concentration of the drift layer. However, as described above, when the thickness of the drift layer is small and the impurity concentration of the drift layer is high, a high withstand voltage is not obtained. In this way, the withstand voltage in the off state and the on-resistance in the on state are in a trade-off relationship.
As a structure capable of improving a compromise between the withstand voltage in the off state and the on-resistance in the on state, a super junction (superjunction) structure as described in patent document 1 is proposed. In the super junction structure, n-type column layers and p-type column layers having long shapes and the like are alternately arranged in a direction perpendicular to a direction in which current flows, and charge balance is obtained so that effective impurity amounts in both column layers are equal. The effective impurity amount is an amount of an impurity that effectively functions as an acceptor in the p-type semiconductor and an amount of an impurity that effectively functions as a donor in the n-type semiconductor.
By adopting the super junction structure, the relationship between the breakdown voltage in the off state and the on-resistance in the on state, which is a problem of the conventional switching element, can be improved. That is, the semiconductor device having the super junction structure can maintain the on-state resistance as it is and can improve the withstand voltage as it is, for example, while maintaining the on-state resistance as it is, as compared with the conventional switching element.
Prior art literature
Patent literature
Patent document 1: japanese patent laid-open No. 2006-313892
Disclosure of Invention
The bottom surface of the trench of the semiconductor element in patent document 1 is in contact with the n-type pillar layer. As a result, dielectric breakdown may occur due to electric field concentration at the bottom of the trench.
The present invention aims to solve the above problems by relaxing the electric field concentration at the bottom of a trench, and as a result, a highly reliable semiconductor device is obtained.
The semiconductor device of the present invention includes a semiconductor region including a 1 st main surface and a2 nd main surface on the opposite side of the 1 st main surface, wherein the semiconductor region includes: the 1 st column layer of the 1 st conductive type and the 2 nd column layer of the 2 nd conductive type are alternately arranged along the 1 st main surface; the 1 st well layer of the 2 nd conductive type is arranged in the 1 st column layer and on the upper surface of the 1 st column layer; a 1 st source layer of 1 st conductivity type disposed in the 1 st well layer and on an upper surface of the 1 st well layer; the 1 st side insulating layer is arranged on the side surface in the 1 st groove arranged at the boundary of the 1 st column layer and the 2 nd column layer and is connected with the 1 st well layer and the 1 st source electrode layer; the 1 st bottom surface insulating layer is arranged on the bottom surface in the 1 st groove, and at least one part of the 1 st bottom surface insulating layer is connected with the 2 nd column body layer; and a 1 st gate electrode provided in the 1 st trench, facing the 1 st well layer and the 1 st source layer through the 1 st side insulating layer, facing the 2 nd pillar layer through the 1 st bottom insulating layer, the 2 nd pillar layer including a 1 st conductive type 2 nd source layer provided in the 2 nd pillar layer and on the upper surface of the 2 nd pillar layer, the 1 st side insulating layer being provided on both sides of the 1 st trench, in contact with the 2 nd conductive type region and the 2 nd source layer in the 2 nd pillar layer, the 1 st bottom insulating layer in contact with the 2 nd conductive type region in the 2 nd pillar layer, and the bottom surface of the 2 nd source layer being closer to the 2 nd main surface than the bottom surface of the 1 st source layer.
The semiconductor device of the present invention includes: the 1 st bottom surface insulating layer is arranged on the bottom surface of the 1 st groove; and a1 st gate electrode disposed in the 1 st trench, facing the 1 st well layer and the 1 st source layer through the 1 st side insulating layer, and facing the 2 nd column layer through the 1 st bottom insulating layer. As a result, the electric field applied to the 1 st bottom insulating layer through the 2 nd pillar layer depleted in the off state of the semiconductor device is reduced. As a result, a highly reliable semiconductor device can be obtained.
Drawings
Fig. 1 is a cross-sectional view of A-A' of a semiconductor device in embodiment 1 of the present invention.
Fig. 2 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 1 of the present invention.
Fig. 3 is a cross-sectional view A-A' showing the operation of the semiconductor device in embodiment 1 of the present invention.
Fig. 4 is a diagram showing a method for manufacturing a semiconductor device in embodiment 1 of the present invention.
Fig. 5 is a diagram showing a method for manufacturing a semiconductor device in embodiment 1 of the present invention.
Fig. 6 is a diagram showing a method for manufacturing a semiconductor device in embodiment 1 of the present invention.
Fig. 7 is a diagram showing a method for manufacturing a semiconductor device in embodiment 1 of the present invention.
Fig. 8 is a diagram showing a method for manufacturing a semiconductor device in embodiment 1 of the present invention.
Fig. 9 is a diagram showing a method for manufacturing a semiconductor device in embodiment 1 of the present invention.
Fig. 10 is a diagram showing a method for manufacturing a semiconductor device in embodiment 1 of the present invention.
Fig. 11 is a diagram showing a method for manufacturing a semiconductor device in embodiment 1 of the present invention.
Fig. 12 is a diagram showing a method for manufacturing a semiconductor device in embodiment 1 of the present invention.
Fig. 13 is a B-B' cross-sectional view of the semiconductor device in embodiment 2 of the present invention.
Fig. 14 is a plan view of a semiconductor device in embodiment 2 of the present invention.
Fig. 15 is a B-B' cross-sectional view showing an operation of the semiconductor device in embodiment 2 of the present invention.
Fig. 16 is a C-C' cross-sectional view of the semiconductor device in embodiment 3 of the present invention.
Fig. 17 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 3 of the present invention.
Fig. 18 is a D-D' cross-sectional view of the semiconductor device in embodiment 4 of the present invention.
Fig. 19 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 4 of the present invention.
Fig. 20 is an E-E' cross-sectional view of the semiconductor device in embodiment 5 of the present invention.
Fig. 21 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 5 of the present invention.
Fig. 22 is a cross-sectional view of F-F' of the semiconductor device in embodiment 6 of the present invention.
Fig. 23 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 6 of the present invention.
Fig. 24 is a cross-sectional view of G-G' of the semiconductor device in embodiment 7 of the present invention.
Fig. 25 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 7 of the present invention.
Fig. 26 is a cross-sectional view of H-H' of the semiconductor device in embodiment 8 of the present invention.
Fig. 27 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 8 of the present invention.
Fig. 28 is a cross-sectional view of I-I' of the semiconductor device in embodiment 8 of the present invention.
Fig. 29 is a cross-sectional view of I-I' of the semiconductor device in embodiment 8 of the present invention.
Fig. 30 is a cross-sectional view of a J-J' of the semiconductor device in embodiment 9 of the present invention.
Fig. 31 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 9 of the present invention.
Fig. 32 is a cross-sectional view of a K-K' semiconductor device in embodiment 10 of the present invention.
Fig. 33 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 10 of the present invention.
Fig. 34 is a cross-sectional view of L-L' of the semiconductor device in embodiment 11 of the present invention.
Fig. 35 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 11 of the present invention.
Fig. 36 is a cross-sectional view of a semiconductor device M-M' in embodiment 11 of the present invention.
Fig. 37 is a cross-sectional view of a semiconductor device M-M' in embodiment 11 of the present invention.
Fig. 38 is a cross-sectional view of N-N' of the semiconductor device in embodiment 12 of the present invention.
Fig. 39 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 12 of the present invention.
Fig. 40 is a cross-sectional view of an o—o' semiconductor device in embodiment 13 of the present invention.
Fig. 41 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 13 of the present invention.
Fig. 42 is a cross-sectional view of P-P' of the semiconductor device in embodiment 14 of the present invention.
Fig. 43 is a plan view showing the upper surface of a semiconductor region in the semiconductor device in embodiment 14 of the present invention.
Fig. 44 is a functional configuration diagram of a power conversion device in embodiment 15 of the present invention.
Detailed Description
Embodiment 1
The structure of the present embodiment will be described below with reference to fig. 1 to 2. In this specification, the semiconductor device will be described as a silicon carbide MOSFET, the 1 st conductivity type will be n-type, and the 2 nd conductivity type will be p-type. Further, when silicon carbide is used as a material of the semiconductor device, low loss and high temperature of an operable temperature can be achieved.
Fig. 1 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines a to a' of fig. 2. Fig. 2 is a plan view showing an upper surface of a semiconductor region in the semiconductor device of the present embodiment.
As shown in fig. 1, the semiconductor device in the present embodiment includes a semiconductor region 40, an interlayer insulating layer 33, a front ohmic electrode 81, a source electrode 82, a back ohmic electrode 91, and a drain electrode 92. The semiconductor region 40 includes an n-type low-resistance silicon carbide substrate 11 as a semiconductor substrate, an n-type epitaxial crystal layer 12, and a super junction layer 15 including an n-type pillar layer 13 as a1 st pillar layer and a p-type pillar layer 14 as a2 nd pillar layer. The n-type pillar layer 13 includes a p-type 1 st well layer 21, an n+ -type 1 st source layer 22, and a1 st p+ -type layer 23. The p-type pillar layer 14 includes a 2p+ -type layer 52.
The semiconductor region 40 has a1 st main surface and a2 nd main surface. In fig. 1, the 1 st main surface is the upper surface of the semiconductor region 40 on the paper surface. The 2 nd main surface is the surface of the lower die of the semiconductor region 40. That is, the 2 nd main surface is provided on the opposite side of the 1 st main surface. The silicon carbide substrate 11 is n+ type. The silicon carbide substrate 11 is provided on the 2 nd main surface in the semiconductor region 40. The surface of the silicon carbide substrate 11 on the 1 st main surface side is inclined at an off angle of 4 ° with respect to the (0001) plane direction [11-20 ]. The polytype of the silicon carbide substrate 11 is, for example, 4H. The n+ type indicates that the impurity concentration is higher than the n type.
An n-type epitaxial crystal layer 12 is formed on the upper surface of the silicon carbide substrate 11. The epitaxial crystalline layer 12 includes silicon carbide having an impurity concentration of, for example, n-type 1×10 13cm-3～1×1018cm-3 and a thickness of, for example, 5 to 150 μm.
On the upper surface of the epitaxial crystalline layer 12, a super junction layer 15 is provided. The super junction layer 15 includes an elongated n-type pillar layer 13 and an elongated p-type pillar layer 14 alternately arranged along the 1 st main surface of the semiconductor region 40. The charge balance is obtained so that the amount of n-type effective impurities contained in the region other than the 1 st well layer 21 described later in the 1 st n-type column layer 13 is equal to the amount of p-type effective impurities contained in the 1 p-type column layer 14. As shown in fig. 2, the n-type pillar layer 13 and the p-type pillar layer 14 are formed in a stripe shape in a plan view. That is, the super junction layer 15 has a stripe shape in a plan view.
Inside the n-type pillar layer 13 and on the upper surface of the n-type pillar layer 13, a p-type 1 st well layer 21 is selectively provided. The 1 st well layer 21 is formed in a stripe shape in a plan view. As the p-type impurity, aluminum (Al) is used. Inside the 1 st well layer 21 and on the upper surface of the 1 st well layer 21, an n+ -type 1 st source layer 22 is selectively provided. As shown in fig. 2, in the present embodiment, the 1 st source layer 22 is formed in a stripe shape in a plan view. Further, nitrogen (N) is used as an N-type impurity.
The depth of the 1 st well layer 21 is, for example, about 0.5 to 3 μm. The impurity concentration of the 1 st well layer 21 is higher than that of the epitaxial crystal layer 12, and is set to be in the range of 1×10 17cm-3～1×1019cm-3, for example. The impurity concentration of the 1 st source layer 22 is set to, for example, a range of 1×10 18cm-3～1×1021cm-3, and the impurity concentration of the ion-implanted n-type exceeds the impurity concentration of the 1 st well layer 21 p-type.
The 1 st trench 74 is provided at the boundary of the n-type cylinder layer 13 and the p-type cylinder layer 14. The 1 st groove 74 has side surfaces and a bottom surface. The 1 st trench 74 is entirely within the p-type cylinder layer 14. The bottom surface of the 1 st trench 74 is formed deeper than the 1 st well layer 21. As shown in fig. 2, the 1 st groove 74 is formed in a stripe shape in a plan view. As shown in fig. 1, the 1 st trench 74 has its side surface perpendicular to the silicon carbide substrate 11, and the 1 st trench 74 has its bottom surface parallel to the silicon carbide substrate 11. However, the side surfaces of the 1 st trench 74 may not necessarily be perpendicular to the silicon carbide substrate 11. The bottom surface of the 1 st trench 74 may not necessarily be parallel to the silicon carbide substrate 11.
A1 st side insulating layer 35 including silicon dioxide is formed on the entire side surface of the 1 st trench 74. A1 st bottom insulating layer 36 including silicon dioxide is formed on the entire bottom surface of the 1 st trench 74. The 1 st side insulating layer 35 is provided so as to be in contact with the 1 st well layer 21 and the 1 st source layer 22. The 1 st bottom insulating layer 36 is provided so as to be in contact with the p-type column layer 14. The 1 st gate electrode 71 is disposed within the 1 st trench 74. The 1 st gate electrode 71 faces the 1 st well layer 21 and the 1 st source layer 22 through the 1 st side insulating layer 35. The 1 st gate electrode faces the p-type column layer 14 through the 1 st bottom insulating layer 36. In the material of the 1 st gate electrode 71, doped polysilicon is used, for example.
As shown in fig. 1, a 1st p+ -type layer 23 is formed in a region not in contact with the 1 st side insulating layer 35 in a region above the 1 st well layer 21. The 1st p+ -type layer 23 is connected to the 1 st well layer 21. The p+ type indicates that the impurity concentration is higher than the p type. As shown in fig. 2, the 1st p+ -type layer 23 is formed in a stripe shape in a plan view.
As shown in fig. 1, a 2p+ -type layer 52 is formed in a region not in contact with the 1 st side insulating layer 35 in a region above the p-type column layer 14. As shown in fig. 2, the 2p+ -type layer 52 is formed in a stripe shape in a plan view.
The 1st p+ -type layer 23 is a layer provided to improve electrical contact between the 1 st well layer 21 and a front ohmic electrode 81 described later. The 2p+ -type layer 52 is provided so that the electrical contact between the p-type column layer 14 and a front ohmic electrode 81 described later is good. The impurity concentration of the 1st p+ type layer 23 and the 2st p+ type layer 52 is preferably set to be higher than the impurity concentration of the 1 st well layer 21, for example, in the range of 1×10 19cm-3～1×1021cm-3. The reason for this is that the 1st p+ -type layer 23 and the 2nd p+ -type layer 52 are preferably low-resistance.
As shown in fig. 1, a front ohmic electrode 81 is provided on the 1 st source layer 22, the 11p+ -type layer 23, and the 2p+ -type layer 52. Further, a source electrode 82 is provided on the front ohmic electrode 81. The source electrode 82 is electrically connected to the 1 st source layer 22, the 11p+ -type layer 23, and the 2p+ -type layer 52 via the front ohmic electrode 81. The front ohmic electrode 81 reduces the contact resistance between the source electrode 82 and the 1 st source layer 22, the 1 st p+ -type layer 23, and the 2 nd p+ -type layer 52.
As shown in fig. 1, an interlayer insulating layer 33 is provided between the source electrode 82 and the 1 st gate electrode 71 and between the p-type pillar layer 14. The 1 st gate electrode 71 and the source electrode 82 are electrically insulated by the interlayer insulating layer 33.
Further, according to fig. 1, a partial region of the interlayer insulating layer 33 is provided on the upper surface of the 1 st source layer 22. However, a partial region of the interlayer insulating layer 33 may not be provided on the upper surface of the 1 st source layer 22. In addition, a part of the interlayer insulating layer 33 may be provided on the upper surface of the 2p+ -type layer 52 or may not be provided on the upper surface of the 2p+ -type layer 52.
As shown in fig. 1, a drain electrode 92 is formed on the 2 nd main surface side of the semiconductor region 40 through a back ohmic electrode 91. Gold or other metals or a laminate thereof is used for the drain electrode 92.
Next, an operation of the semiconductor device in this embodiment will be described. Fig. 3 is a cross-sectional view A-A' showing the operation of the semiconductor device in the present embodiment. When a voltage higher than a specific voltage value (1 st threshold voltage) is applied to the 1 st gate electrode 71, a channel is formed in a region in the 1 st well layer 21 that is in contact with the 1 st side insulating layer 35. As a result, the resistance value between the drain electrode 92 and the source electrode 82 becomes low, and a positive voltage is applied to the drain electrode 92, so that a current (on state) flows between the drain electrode 92 and the source electrode 82 in the direction of the arrow 501.
On the other hand, when a voltage lower than the 1 st threshold voltage is applied to the 1 st gate electrode 71, the channel disappears. As a result, the resistance between the drain electrode 92 and the source electrode 82 of the semiconductor device increases, and almost no current flows (off state).
Next, a method for manufacturing a semiconductor device in this embodiment mode will be described. Fig. 4 to 12 are diagrams showing a method for manufacturing the semiconductor device according to the present embodiment. The super junction structure is formed mainly by 2 methods, i.e., a multi-epitaxy method and a trench filling method. The multiple epitaxy method is a method in which epitaxial growth of an n-type semiconductor layer and ion implantation of a p-type impurity are repeated. In the super junction structure, in order to improve withstand voltage, it is effective to increase the depth of the p-type column layer. In the multi-epitaxy system, the number of repetitions is determined by the implantation depth of the ion implantation. For example, in the case of being able to implant to a depth of 1 μm, in the case of forming a 10 μm super junction layer, it is necessary to repeat epitaxial growth and ion implantation 10 times.
On the other hand, the trench filling method is a method in which first, after epitaxially growing a semiconductor layer of n-type conductivity to a thickness of a super junction layer necessary for the formation of a trench by anisotropic etching, then, epitaxially growing a semiconductor layer of p-type conductivity to embed the trench. The trench filling method has a smaller number of process steps than the multi-epitaxy method. The method for manufacturing a semiconductor device described in this embodiment mode is a method for manufacturing a trench filling method.
First, as shown in fig. 4, an n+ -type silicon carbide substrate 11 is prepared. Next, as shown in fig. 5, an n-type epitaxial crystalline layer 12 is epitaxially grown on the silicon carbide substrate 11 by a chemical vapor deposition (chemical vapor deposition: CVD) method. As will be described later, the n-type column layer 13 is formed of the epitaxial crystalline layer 12. The thickness of the epitaxial crystal layer 12 may be appropriately set according to the thickness of the n-type pillar layer 13.
Next, an oxide film 17 is deposited on the surface of the epitaxial crystalline layer 12. The oxide film 17 is deposited so as to serve as a mask for etching to form the p-type column layer 14 in a later process. The thickness of the oxide film 17 may be appropriately set according to the thickness of the p-type column layer 14.
After the deposition of the oxide film 17, as shown in fig. 6, a mask pattern including the oxide film 17 for forming the p-type pillar layer 14 is formed using a photoresist.
Next, the epitaxial crystal layer 12 is etched (etching step 1). As shown in fig. 7, a mask pattern formed of an oxide film 17 is deposited on the surface of the epitaxial crystalline layer 12 at intervals. Therefore, a plurality of pillar-forming trenches 18 are formed in the epitaxial crystal layer 12 at intervals. Since the shape of the p-type pillar layer 14 formed in the subsequent step is the shape of the pillar-forming trench 18, it is preferable to etch by dry etching in which the control of the shape of the pillar-forming trench 18 is simpler.
Next, as shown in fig. 8, epitaxial growth is performed to grow an epitaxial crystal layer 19 of p-type silicon carbide in the column forming trench 18 (crystal growth step). The impurity concentration of the epitaxial crystal layer 19 of p-type silicon carbide is set so that the amount of effective impurities contained in the region of the n-type column layer 13 excluding the 1 st well layer 21 is the same as the amount of effective impurities contained in the p-type column layer 14, that is, the charge balance.
Next, as shown in fig. 9, a part of the p-type epitaxial crystal layer 19 and the n-type epitaxial crystal layer 12 is removed by chemical mechanical polishing (CHEMICAL MECHANICAL polishing: CMP), and the n-type epitaxial crystal layer 12 is exposed on the upper surface side of the silicon carbide substrate 11. An n-type column layer 13 is formed from a part of the n-type epitaxial crystal layer 12 exposed on the upper surface side of the silicon carbide substrate 11. The p-type column layer 14 is formed from the p-type epitaxial crystalline layer 19. The super junction layer 15 is formed by the n-type pillar layer 13 and the p-type pillar layer 14.
Next, an implantation mask is formed by using a photoresist or the like, al ions, which are p-type impurities, are ion-implanted into the upper portion of the n-type column layer 13, and as shown in fig. 10, the 1 st well layer 21 of the 2 nd conductivity type is formed in the n-type column layer 13 and on the upper surface of the n-type column layer 13 (1 st ion implantation step). After the ion implantation is completed, the implantation mask is removed.
Next, an implantation mask is formed by using a photoresist or the like, and N ions, which are N-type impurities, are ion-implanted into the upper portion of the 1 st well layer 21, and as shown in fig. 10, the 1 st source layer 22 of the 1 st conductivity type is selectively formed in the 1 st well layer 21 and on the upper surface of the 1 st well layer 21 (a 2 nd ion implantation step). After the ion implantation is completed, the implantation mask is removed.
The 1 st source layer 22 has a depth shallower than the 1 st well layer 21. Since the channel length is determined by the difference between the depth of the 1 st source layer 22 and the depth of the 1 st well layer 21, the depth of the 1 st source layer 22 may be set so that desired electrical characteristics can be obtained.
Next, an implantation mask is formed by photoresist or the like, and Al, which is a p-type impurity, is ion-implanted in the upper portion of the p-type column layer 14 and the upper portion of the 1 st source layer 22, thereby forming the 1p+ -type layer 23 and the 2p+ -type layer 52 at the same time, as shown in fig. 10. After the ion implantation is completed, the implantation mask is removed.
The order of forming the 1 st well layer 21, the 1 st source layer 22, the 1 st p+ -type layer 23, and the 2 nd p+ -type layer 52 may not necessarily be the above-described order of steps.
Then, annealing treatment is performed in an inert gas atmosphere such as argon (Ar) gas or vacuum, for example, at 1500 to 2100℃for 30 seconds to 1 hour. By this annealing treatment, ion-implanted Al and N are electrically activated.
Next, as shown in fig. 11, the 1 st trench 74 is formed (2 nd etching step). Specifically, first, an etching mask is formed by using a resist or the like so as to etch a region including at least the p-type column layer 14 at the boundary between the n-type column layer 13 and the p-type column layer 14. Thereafter, the 1 st trench 74 is formed by etching, and finally the etching mask is removed.
Further, the oxide film 17 does not necessarily have to be used as a mask pattern, and a resist mask or the like may be used. The annealing step and the step of forming the 1 st trench 74 may be performed in any order, and the annealing treatment may be performed after the 1 st trench 74 is formed.
Next, a silicon oxide layer is formed on the side surfaces and the bottom surface of the 1 st trench 74 by a thermal oxidation method or a CVD method (insulating layer forming step). Thus, as shown in fig. 12, the 1 st side insulating layer 35 is formed on the side surface of the 1 st trench 74, and the 1 st bottom insulating layer 36 is formed on the bottom surface of the 1 st trench 74. The thickness of the 1 st side insulating layer 35 and the 1 st bottom insulating layer 36 are, for example, 30nm to 150nm, respectively.
Next, doped polysilicon is formed by CVD in the region surrounded by the 1 st side insulating layer 35 and the 1 st bottom insulating layer 36 (gate formation step). At this time, the doped polysilicon is preferably sufficiently buried in the 1 st trench 74.
Next, the doped polysilicon deposited on the upper surface of the super junction layer 15 is removed by etching back. At this time, the doped polysilicon in the 1 st trench 74 remains. The 1 st gate electrode 71 is formed by doped polysilicon remaining inside the 1 st trench 74 as shown in fig. 12. Further, even if the upper surface of the doped polysilicon inside the 1 st trench 74 is below the upper surface of the super junction layer 15, there is no problem. But the upper surface of the doped polysilicon inside the 1 st trench 74 needs to be above the bottom surface of the 1 st source layer 22. Through this process, the semiconductor region 40 is completed.
Next, an insulating layer is deposited on the 1 st main surface of the semiconductor region 40 by CVD or the like. Then, the insulating layer is removed by using a resist mask or the like in the active region, thereby forming source contact holes reaching the 1 st source layer 22, the 1 st p+ -type layer 23, and the 2 nd p+ -type layer 52. At this time, the interlayer insulating layer 33 is formed from the remaining insulating layer. The active region is a semiconductor region through which a current flows when a voltage is applied to the semiconductor device. In addition, a semiconductor region formed along the periphery of the active region is referred to as a termination region.
Next, a metal film containing nickel (Ni) as a main component is formed on the 1 st main surface of the semiconductor region 40 by a sputtering deposition method or the like, and then a heat treatment at a temperature of 600to 1100 ℃ is performed to react the metal film containing Ni as a main component with the upper surfaces of the 1 st source layer 22, the 1p+ -type layer 23, and the 2p+ -type layer 52, thereby forming a silicide layer therebetween. Next, the metal film remaining on the interlayer insulating layer 33 other than the reacted silicide layer is removed. Thereby, the front ohmic electrode 81 is formed.
Next, a metal film containing Ni as a main component is formed on the 2 nd main surface of the semiconductor region 40 by using a sputtering deposition method or the like, and then, a heat treatment is performed on the 2 nd main surface of the semiconductor region 40, whereby the back ohmic electrode 91 is formed on the 2 nd main surface of the semiconductor region 40.
Next, a metal film containing Al is formed on the 1 st main surface of the semiconductor region 40 by a sputtering deposition method, a vacuum deposition method, or the like. In this case, it is preferable that the metal is completely buried in each contact hole. Thereafter, the metal film at an unnecessary portion is removed by wet etching using a resist mask or the like, whereby the source electrode 82 is formed.
Next, a metal film containing gold is formed on the surface of the back ohmic electrode 91 by sputtering deposition or the like, and the drain electrode 92 is formed. Through the above-described series of steps, the semiconductor device in the present embodiment shown in fig. 1 is completed.
The step of forming a semiconductor layer of the 2 nd conductivity type formed in the terminal region, which is generally called a guard ring, the step of forming an insulating layer formed under the terminal region, such as a gate wiring or a gate pad, which is generally called a field insulating layer, and the like, may be added as appropriate to the series of steps.
In general, in each process of the manufacturing process of the semiconductor device, the local shape of the semiconductor device affects the final processing of the process. Therefore, for example, when the shape is not periodic, the final processing of the partial shape may not be constant, and the partial characteristics may be deviated. The local variation in characteristics causes deterioration in the reliability of the element. Therefore, in the present embodiment, the interval between the n-type column layers 13 and the interval between the p-type column layers 14 are made constant, thereby suppressing local variation in characteristics and preventing deterioration in the reliability of the semiconductor device.
The region formed of a semiconductor such as the 1 st well layer 21 and the 1 st source layer 22, and the region excluding the semiconductor such as the 1 st trench 74 are preferably formed in a stripe shape as described in the present embodiment. When the crystal growth process is performed using the silicon carbide substrate 11 having the off-angle, there is a possibility that the alignment mark used in the exposure process for resist patterning is shifted in a direction corresponding to the off-angle. In this case, the region formed of the semiconductor such as the 1 st well layer 21 and the 1 st source layer 22, and the region formed of the semiconductor such as the 1 st trench 74 are formed at positions offset from the n-type pillar layer 13 in the direction corresponding to the offset angle.
For example, when the region formed of the semiconductor such as the 1 st well layer 21 and the 1 st source layer 22, and the region formed of the semiconductor such as the 1 st trench 74 are formed in a lattice shape, there is a possibility that characteristic fluctuation occurs even when the alignment mark is shifted in any direction. However, when the region formed of the semiconductor such as the 1 st well layer 21 and the 1 st source layer 22, and the region formed of the semiconductor such as the 1 st trench 74 are formed in a stripe shape, the characteristic variation can be suppressed by matching the direction in which the misalignment of the alignment mark occurs with the direction in which the stripe extends. In addition, the greater the depth of the p-type pillar layer 14, the greater the magnitude of the offset.
As described above, the semiconductor device according to the present invention includes: a1 st bottom insulating layer 36 provided on the bottom surface of the 1 st trench 74; and a1 st gate electrode provided in the 1 st trench 74, facing the 1 st well layer 21 and the 1 st source layer 22 through the 1 st side insulating layer 35, and facing the p-type column layer 14 through the 1 st bottom insulating layer 36. As a result, the electric field applied to the 1 st bottom insulating layer 36 by the p-type column layer 14 depleted in the off state of the semiconductor device in this embodiment is reduced. As a result, a highly reliable semiconductor device can be obtained.
In addition, in the case of a conventional semiconductor device having a super junction structure, there is no need to add a step of forming a p-type semiconductor layer for reducing an electric field.
In particular, if the entire 1 st bottom insulating layer 36 is in contact with the p-type pillar layer 14, the effect of reducing the electric field is further enhanced, and the reliability of the silicon carbide MOSFET is further improved.
As shown in fig. 1 and 2, the 1 st trench 74 is provided on the boundary with the n-type column layer 13 on both sides with respect to the p-type column layer 14 formed in a stripe shape, but may be provided on any boundary on one side. However, when the p-type column layer 14 formed in a stripe shape is provided at the boundary with the n-type column layer 13 on both sides, the channel width density is larger than that at the boundary on any one side, and as a result, the on-resistance can be reduced.
Embodiment 2
The structure of the present embodiment will be described below with reference to fig. 13 to 15. Fig. 13 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines B-B' of fig. 14. Fig. 14 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. In addition, most of the semiconductor device of this embodiment is the same as embodiment 1, and only differences from the semiconductor device of embodiment 1 will be described.
As shown in fig. 13, the semiconductor device according to the present embodiment has a structure in which a p-type 2 nd well layer 26 is provided in a p-type pillar layer 14 and on the upper surface of the p-type pillar layer 14, in addition to the structure of the semiconductor device according to embodiment 1. Further, an n+ -type 2 nd source layer 27 is provided in the 2 nd well layer 26 and on the upper surface of the 2 nd well layer 26. The p-type pillar layer 14 in this embodiment includes a2 nd well layer 26 and a2 nd source layer 27.
As shown in fig. 13, the 1 st side insulating layer 35 is provided on both sides of the 1 st trench 74. The 1 st side insulating layer 35 is connected to the 2 nd well layer 26 and the 2 nd source layer 27. The 1 st bottom insulating layer 36 is connected to the 2 nd well layer 26. That is, the 1 st bottom insulating layer 36 contacts the p-type region in the p-type pillar layer 14. The 2 nd well layer 26 is formed in a stripe shape in a plan view.
The impurity concentration of the 2 nd well layer 26 may be the same as or different from the impurity concentration of the region of the p-type column layer 14 other than the 2 nd well layer 26. The impurity concentration of the 2 nd well layer 26 may have a distribution such that the concentration varies in a direction perpendicular to the silicon carbide substrate 11. The concentration distribution of the impurity concentration of the 2 nd well layer 26 may be such that the impurity concentration at the portion in contact with the 1 st bottom insulating layer 36 is the same as the impurity concentration at the region of the p-type column layer 14 other than the 2 nd well layer 26. In general, the threshold voltage of the MOSFET depends on the impurity concentration of the well region, and therefore the impurity concentration of the 2 nd well layer 26 may be an appropriate impurity concentration such that the target threshold voltage is achieved. In the present embodiment, the impurity concentration of the 2 nd well layer 26 is higher than the impurity concentration of the region of the p-type column layer 14 other than the 2 nd well layer 26, and the impurity concentration of the 2 nd well layer 26 is constant.
As shown in fig. 13, an n+ -type 2 nd source layer 27 is formed in the 2 nd well layer 26 and on the upper surface of the 2 nd well layer 26. As shown in fig. 14, the 2 nd source layer 27 is formed in a stripe shape in a plan view. The front ohmic electrode 81 in the present embodiment is connected to the 2 nd source layer 27 in addition to the 1 st source layer 22, the 1 st p+ -type layer 23, and the 2 nd p+ -type layer 52.
Next, an operation of the semiconductor device in this embodiment will be described. Fig. 15 is a B-B 'cross-sectional view showing an operation of the semiconductor device in the present embodiment, and is a cross-sectional view of a portion of an auxiliary line connecting B-B' of fig. 14. When a voltage higher than a specific voltage value (1 st threshold voltage) is applied to the 1 st gate electrode 71, a channel is formed in a region in the 1 st well layer 21 that is in contact with the 1 st side insulating layer 35. As a result, as in embodiment 1, a positive voltage is applied to the drain electrode 92, and a current flows between the drain electrode 92 and the source electrode 82 in the direction of arrow 501.
Further, in the semiconductor device according to the present embodiment, the 2 nd source layer 27 electrically connected to the source electrode 82 is provided on the p-type column layer 14. Therefore, when a voltage higher than a specific voltage value (2 nd threshold voltage) is applied to the 1 st gate electrode 71, a channel is formed also in the region in the 2 nd well layer 26 that is in contact with the 1 st side insulating layer 35. As a result, a positive voltage is applied to the drain electrode 92, so that a current flows between the drain electrode 92 and the source electrode 82 in the direction of arrow 501, and a current also flows in the direction of arrow 502. The 1 st threshold voltage and the 2 nd threshold voltage may be the same or different.
Next, a method for manufacturing a semiconductor device in this embodiment mode will be described. The method for manufacturing a semiconductor device according to this embodiment is largely the same as that of embodiment 1, and only differences from the method for manufacturing a semiconductor device according to embodiment 1 will be described.
The method of manufacturing a semiconductor device according to the present embodiment includes a step of forming the 2 nd well layer 26 on the upper surface of the p-type column layer 14. In the above step, al (aluminum) as a p-type impurity is ion-implanted through an implantation mask such as a photoresist on the upper surface of the p-type column layer 14 shown in fig. 9, thereby forming the 2 nd well layer 26 shown in fig. 13. The depth of the 2 nd well layer 26 is, for example, about 0.5 to 4 μm. The depth of the 2 nd well layer 26 is shallower than the depth of the p-type pillar layer 14. The impurity concentration of the 2 nd well layer 26 is the same as or higher than that of the region of the p-type column layer 14 other than the 2 nd well layer 26, and is set to, for example, a range of 1×10 17cm-3～1×1019cm-3. After the ion implantation is completed, the implantation mask is removed.
The method for manufacturing a semiconductor device according to the present embodiment includes a step of forming the 2 nd source layer 27 on the upper surface of the 2 nd well layer 26 formed in the above. In the above step, N (nitrogen) as an N-type impurity is ion-implanted into the upper surface of the 2 nd well layer 26 formed in the above step through the implantation mask of the photoresist, thereby forming a2 nd source layer 27 as shown in fig. 13.
The depth of the 2 nd source layer 27 is shallower than the depth of the 2 nd well layer 26. The depth of the 2 nd source layer 27 must be shallower than the depth of the p-type pillar layer 14. The impurity concentration of the 2 nd source layer 27 may be higher than the impurity concentration of the 1 st source layer 22 or lower than the impurity concentration of the 1 st source layer 22. The impurity concentration of the 2 nd source layer 27 may have a concentration distribution in a direction perpendicular to the silicon carbide substrate 11. For example, in the range of 1×10 18cm-3～1×1021cm-3, the impurity concentration of the n-type ion implantation in this step exceeds the impurity concentration of the p-type ion implantation in the 2 nd well layer 26. After the ion implantation is completed, the implantation mask is removed.
The step of forming the 2 nd well layer 26 on the upper surface of the p-type column layer 14 and the step of forming the 2 nd source layer 27 on the upper surface of the 2 nd well layer 26 described above may be added before or after the steps of forming the 1 st well layer 21, the 1 st source layer 22, the 1p+ -type layer 23, and the 2p+ -type layer 52, and the order of the steps may be arbitrary, or may not be the above-described order of the steps.
As described above, the semiconductor device in the present embodiment is provided with the p-type 2 nd well layer 26 in the p-type pillar layer 14 and on the upper surface of the p-type pillar layer 14. As shown in fig. 13, the 1 st side insulating layer 35 is connected to the 2 nd well layer 26 and the 2 nd source layer 27, and the 1 st bottom insulating layer 36 is connected to the 2 nd well layer 26. As a result, when the semiconductor device is turned on, a channel is formed also in the region in the 2 nd well layer 26 that contacts the 1 st side insulating layer 35. On the other hand, the semiconductor element described in patent document 1 has 1 trench gate type gate structure provided in an n-type pillar layer. Therefore, the semiconductor device according to the present embodiment has a larger channel width density than the semiconductor element described in patent document 1. Therefore, the semiconductor device according to the present embodiment has a further effect that the on-resistance can be reduced as compared with the semiconductor element described in patent document 1.
Further, the deeper the depth of the trench formed in the trench filling method, the larger the width of the p-type column layer becomes according to the restrictions in the process. For example, when silicon carbide is used as a semiconductor material, a p-type column layer having a depth of about 40 μm is required to achieve a withstand voltage of 6.5 kV. In the trench filling method, in general, a trench is formed by dry etching using a pattern of a deposited oxide film as a mask. The pattern of depositing the oxide film is formed by dry etching using a patterned resist mask after depositing the oxide film over the wafer. That is, in order to form a trench on a wafer, the dry etching process was performed 2 times.
In dry etching, the oxide film mask or the resist mask is gradually etched not only from its upper surface but also from its end face, so in the case of using a positive resist, the width or area of the finally processed trench region is larger than that in the photolithography of the resist mask. When forming a trench having a depth of about 40 μm for achieving a withstand voltage of 6.5kV, the width of the trench to be formed becomes about 7 μm or more even when the exposure region in photolithography is sufficiently narrow due to the influence of etching of the mask end face.
On the other hand, regarding the region where the trench is not formed, that is, the region where the mask is provided, the width of the mask cannot be narrowed to any extent. This is because, when the resist width is small, the resist collapses or the mask is peeled off from the wafer, and the intended pattern may not be formed. In particular, when the super junction structure is formed, the aspect ratio of the mask pattern in plan view is extremely large, and thus the possibility of occurrence of these pattern formation failures is increased. Therefore, in order to stably form the trench structure, the n-type pillar layer needs to have a width of approximately 5 μm or more. Therefore, in order to form the p-type pillar layer 14 having a depth of about 40 μm, the pillar pitch is about 12 μm or more.
In the case of manufacturing the semiconductor device according to the present embodiment using the trench filling method, which is more productive than the multiple epitaxy method, the width of the p-type column layer 14 becomes extremely large. In the case of the semiconductor element described in patent document 1, since the trench is not provided in the p-type column layer, the influence of the reduction in the channel width density is large. In the semiconductor device of the present embodiment, the effect of reducing the on-resistance of the semiconductor device is significant as compared with the semiconductor element described in patent document 1.
In general, it is difficult to grow epitaxial crystals of silicon carbide in a trench formed in silicon carbide, as compared with the case where silicon is buried in a trench formed in silicon. Therefore, in the case of forming the p-type column layer 14 by the trench filling method, there is a possibility that the 1 st trench 74 needs to be wider than silicon. Therefore, the effect of reducing the on-resistance of the semiconductor device in silicon carbide is significant.
In addition, in the case where the depth of the 2 nd well layer 26 is shallower than the depth of the 1 st trench 74, and the impurity concentration profile of the 2 nd well layer 26 is the same as that of the 1 st well layer 21, the 2 nd well layer 26 and the 1 st well layer 21 may be formed simultaneously. In this case, since a single implantation mask can be used, patterning and the number of times of implantation can be reduced, and further effects such as simplification of the manufacturing process can be obtained.
In addition, when the impurity concentration profile of the 2 nd source layer 27 is the same as that of the 1 st source layer 22, the 2 nd source layer 27 and the 1 st source layer 22 may be formed simultaneously. In this case, since a single implantation mask can be used, patterning and the number of times of implantation can be reduced, and further effects such as simplification of the manufacturing process can be obtained.
Embodiment 3
The structure of the present embodiment will be described below with reference to fig. 16 to 17. Fig. 16 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines C-C' of fig. 17. Fig. 17 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. In addition, most of the semiconductor device of this embodiment mode are common to embodiment mode 2, and only differences from the semiconductor device of embodiment mode 2 will be described.
As shown in fig. 16, the semiconductor device according to the present embodiment has a 2 nd source layer 27a instead of the 2 nd source layer 27, in contrast to the structure of the semiconductor device according to embodiment 2. The 2 nd source layer 27a is formed deeper than the 1 st source layer 22. That is, the bottom surface of the 2 nd source layer 27a is closer to the 2 nd main surface of the semiconductor region 40 than the bottom surface of the 1 st source layer 22.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. In the method for manufacturing a semiconductor device according to this embodiment, ion implantation may be performed so that the depth of the 2 nd source layer 27a is deeper than the depth of the 1 st source layer 22 than in the step of forming the 2 nd source layer 27 according to embodiment 2.
As described above, in the semiconductor device according to the present embodiment, the bottom surface of the 2 nd source layer 27a is closer to the silicon carbide substrate 11 than the bottom surface of the 1 st source layer 22. As a result, the channel length formed on the 2 nd well layer 26 side is shorter than that of the semiconductor device in embodiment 2, and the channel resistance on the 2 nd well layer 26 side is smaller. As a result, the on-resistance of the semiconductor device can be further reduced as compared with embodiment 2.
Embodiment 4
The structure of the present embodiment will be described below with reference to fig. 18 to 19. Fig. 18 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines D-D' in fig. 19. Fig. 19 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. In addition, most of the semiconductor device of this embodiment mode are common to embodiment mode 2, and only differences from the semiconductor device of embodiment mode 2 will be described.
As shown in fig. 18, the semiconductor device according to the present embodiment includes a1 st bottom insulating layer 36a instead of the 1 st bottom insulating layer 36. The 1 st bottom insulating layer 36a is formed to have a smaller film thickness than the 1 st side insulating layer 35.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. In the method for manufacturing a semiconductor device according to this embodiment, the 1 st bottom insulating layer 36a may have a smaller film thickness than the 1 st side insulating layer 35, compared to the step of forming the 1 st bottom insulating layer 36 according to embodiment 2.
In the present embodiment, the (0001) plane is used as the surface of the silicon carbide substrate 11 on the 1 st main surface side. (0001) The face is the face of silicon carbide where the oxidation rate is the slowest among crystal faces. Therefore, by forming the 1 st side insulating layer 35 and the 1 st bottom insulating layer 36a by thermal oxidation, the thickness of the 1 st bottom insulating layer 36a is naturally thinner than the thickness of the 1 st side insulating layer 35.
As described above, in the semiconductor device according to the present embodiment, the 1 st bottom insulating layer 36a has a smaller film thickness than the 1 st side insulating layer 35. Therefore, when the semiconductor device of this embodiment is in an on state, an electric field larger than that of the semiconductor device of embodiment 2 is applied to the vicinity of the 1 st bottom insulating layer 36 a. That is, when the semiconductor device is on, a large amount of inversion carriers are generated near the 1 st bottom insulating layer 36a, and the channel resistance decreases. As a result, the on-resistance of the semiconductor device can be further reduced as compared with embodiment 2.
Embodiment 5
The structure of the present embodiment will be described below with reference to fig. 20 to 21. Fig. 20 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines E-E' of fig. 21. Fig. 21 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment.
The semiconductor device of this embodiment includes both the 2 nd source layer 27a of embodiment 3 and the 1 st bottom insulating layer 36a of embodiment 4. The method of manufacturing a semiconductor device in this embodiment is also a method of combining the method of manufacturing the 2 nd source layer 27a in embodiment 3 and the method of manufacturing the 1 st bottom insulating layer 36a in embodiment 4, and detailed description thereof is omitted.
As described above, since the 2 nd source layer 27a of embodiment 3 and the 1 st bottom insulating layer 36a of embodiment 4 are provided at the same time, the same effect as that of the semiconductor device of embodiment 3 and embodiment 4 is obtained.
Embodiment 6
The structure of the present embodiment will be described below with reference to fig. 22 to 23. Fig. 22 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines F-F' in fig. 23. Fig. 23 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. In addition, most of the semiconductor device of this embodiment mode are common to embodiment mode 2, and only differences from the semiconductor device of embodiment mode 2 will be described.
As shown in fig. 22, the semiconductor device in this embodiment includes a1 st trench 74a instead of the 1 st trench 74. The 1 st trench 74a is formed across the boundary of the n-type cylinder layer 13 and the p-type cylinder layer 14. That is, the 1 st bottom insulating layer 36 in this embodiment is provided so as to be in contact with the 2 nd well layer 26 of the n-type pillar layer 13 and the p-type pillar layer 14. The electric field concentration in the 1 st bottom insulating layer 36 in the present embodiment is alleviated by the depletion layer generated at the interface between the n-type column layer 13 and the 2 nd well layer 26 and the p-type column layer 14 near the bottom of the 1 st trench 74a.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. In the method of manufacturing the semiconductor device according to the present embodiment, the 1 st trench 74a may be etched so as to be formed at a position crossing the boundary between the n-type column layer 13 and the p-type column layer 14, with respect to the step of forming the 1 st trench 74 shown in fig. 11. That is, the position of the opening pattern of the mask at the time of forming the 1 st trench 74a may be a position crossing the boundary between the n-type column layer 13 and the p-type column layer 14.
As described above, the semiconductor device in this embodiment mode is provided such that the 1 st bottom insulating layer 36 is in contact with the 2 nd well layer 26 of the n-type pillar layer 13 and the p-type pillar layer 14. Therefore, when the semiconductor device is turned on, the lateral channel length generated in the 2 nd well layer 26 is shorter than that of the semiconductor device in embodiment 2. As a result, the channel resistance of the semiconductor device is further reduced.
In addition, the semiconductor device in this embodiment may have the 2 nd source layer 27a deeper than the 1 st source layer 22 in place of the 2 nd source layer 27, as in embodiment 3. In this case, the same effect as in the semiconductor device in embodiment 3 is achieved.
Embodiment 7
The structure of the present embodiment will be described below with reference to fig. 24 to 25. Fig. 24 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines G-G' of fig. 25. Fig. 25 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. The E-E 'section of the semiconductor device in embodiment 5 shown in fig. 20 has the same structure as the G-G' section of the semiconductor device in this embodiment shown in fig. 25. Most of the semiconductor device of this embodiment is common to embodiment 5, and only differences from the semiconductor device of embodiment 5 will be described.
As shown in fig. 25, the semiconductor device according to the present embodiment includes, in addition to the 1 st trench 74 having a stripe shape in a plan view, a2 nd trench 74b (a portion surrounded by a broken line in fig. 25) in the n-type pillar layer 13 in a direction perpendicular to the 1 st trench 74 in a plan view. On the side surface inside the 2 nd trench 74b, a2 nd side surface insulating layer 35b is provided. A2 nd bottom insulating layer, not shown, is provided on the bottom surface of the 2 nd trench 74 b. In the 2 nd trench 74b, a2 nd gate electrode 71b is provided so as to face the 1 st well layer 21 and the 1 st source layer 22 through the 2 nd side insulating layer 35b. As shown in fig. 25, the 2 nd groove 74b is connected to the 1 st groove 74 in a plan view.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. The method of manufacturing the semiconductor device in this embodiment is the same as the method of manufacturing the semiconductor device in embodiment 5 except that the 2 nd trench 74b is formed. The 2 nd trench 74b can be manufactured by the same manufacturing method as the 1 st trench 74.
As described above, the semiconductor device according to the present embodiment includes the 1 st trench 74 having a stripe shape in a planar view, and the 2 nd trench 74b is provided in the n-type pillar layer 13 in a vertical direction in a planar view. Accordingly, the channel width density is larger than that of the semiconductor device in embodiment mode 5 in correspondence with the amount of the 2 nd trench 74 b. As a result, the channel resistance of the semiconductor device is further reduced.
In the semiconductor device according to the present embodiment, as in embodiment 1, the electric field applied to the 1 st bottom insulating layer 36a by the p-type column layer 14 depleted in the off state of the semiconductor device according to the present embodiment is reduced. As a result, a highly reliable semiconductor device can be obtained.
In the p-type column layer 14 of the present embodiment, the 2 nd well layer 26 and the 2 nd source layer 27 may not be provided. In this case, a step of forming a p-type semiconductor layer for reducing an electric field and the like is not required in the existing semiconductor device having the super junction structure.
The 1 st gate electrode 71 and the 2 nd gate electrode 71b may not be directly connected. The 1 st gate electrode 71 and the 2 nd gate electrode 71b may be electrically connected. Even in this case, the same effect is achieved.
Embodiment 8
The structure of the present embodiment will be described below with reference to fig. 26 to 29. Fig. 26 is a cross-sectional view of H-H 'of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines H-H' of fig. 27. Fig. 27 is a plan view of the semiconductor device in the present embodiment. The E-E 'section of the semiconductor device in embodiment 5 shown in fig. 20 has the same structure as the H-H' section of the semiconductor device in the present embodiment shown in fig. 27.
As shown in fig. 27, the semiconductor device of the present embodiment has a2 nd trench 74b formed in the vertical direction in the n-type column layer 13 in a planar view in the same manner as embodiment 7 except for the 1 st trench 74 in a stripe shape in a planar view. Further, the 3 rd trench 74c is provided in the p-type column layer 14 (a portion surrounded by a broken line in fig. 27) on the extension of the 2 nd trench 74b. The 3 rd groove 74c is provided in a direction perpendicular to the 1 st groove 74 in a plan view. A3 rd side insulating layer 35c is provided on the side surface inside the 3 rd trench 74 c. A3 rd bottom insulating layer, not shown, is provided on the bottom surface of the 3 rd trench 74 c. In the 3 rd trench 74c, a3 rd gate electrode 71c is provided so as to face the 2 nd well layer 26 and the 2 nd source layer 27a through the 3 rd side insulating layer 35c. The 1 st groove 74 is connected with the 2 nd groove 74b in a plan view. The 3 rd groove 74c is connected to the 2 nd groove 74b in plan view.
Fig. 28 and 29 are cross-sectional views of the semiconductor device according to the present embodiment, and are cross-sectional views of portions connecting the auxiliary lines I-I' of fig. 27. Wherein fig. 28 is an I-I' sectional view from above the paper surface of fig. 27. Fig. 29 is a sectional view of I-I' from below the paper surface of fig. 27. According to fig. 28 and 29, the 3 rd gate electrode 71c is provided so as to face the 2 nd well layer 26 through the 3 rd side insulating layer 35c and the 3 rd bottom insulating layer 36 c.
Referring to fig. 28 and 29, in the on state of the semiconductor device, the region of the 2 nd well layer 26 in contact with the 1 st side insulating layer 35 and the 3 rd side insulating layer 35c is inverted to form a channel. As a result, as shown in fig. 28, a positive voltage is applied to the drain electrode 92, and a current flows in the direction of an arrow 503. That is, the channel width density can be increased. Therefore, in the semiconductor device according to this embodiment, the channel resistance on the 2 nd well layer 26 side is reduced, and the on-resistance of the semiconductor device is reduced, as compared with the semiconductor device according to embodiment 7.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. The method of manufacturing the semiconductor device in this embodiment is the same as the method of manufacturing the semiconductor device in embodiment 7 except that the 3 rd trench 74c is formed. The 3 rd trench 74c can be manufactured by the same manufacturing method as the 1 st trench 74 and the 2 nd trench 74 b.
As described above, in the semiconductor device according to the present embodiment, the 3 rd trench 74c is formed in the p-type column layer 14 in the direction perpendicular to the 1 st trench 74, in addition to the 1 st trench 74 and the 2 nd trench 74 b. Accordingly, the channel width density is larger than that of the semiconductor device in embodiment 7 in correspondence with the amount of the 3 rd trench 74c. As a result, the channel resistance of the semiconductor device is further reduced.
The 3 rd gate electrode 71c may not be directly connected to the 1 st gate electrode 71 and the 2 nd gate electrode 71 b. The 3 rd gate electrode 71c may be electrically connected to the 1 st gate electrode 71 and the 2 nd gate electrode 71 b. Even in this case, the same effect is achieved.
The semiconductor device in this embodiment may not include the 2 nd trench 74b. Even in this case, the channel width density is larger than that of the semiconductor device in embodiment 5 in correspondence with the amount of the 3 rd trench 74 c. As a result, the channel resistance of the semiconductor device is further reduced.
Embodiment 9
The structure of the present embodiment will be described below with reference to fig. 30 to 31. Fig. 30 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines J-J' of fig. 31. Fig. 31 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. Most of the semiconductor device of this embodiment is common to embodiment 5, and only differences from the semiconductor device of embodiment 5 will be described.
As shown in fig. 30, the semiconductor device of the present embodiment includes a2 nd trench 74d in the n-type column layer 13 in addition to the 1 st trench 74. As shown in fig. 31, the 2 nd groove 74d is provided in parallel with the 1 st groove 74. On the side surface inside the 2 nd trench 74d, a2 nd side surface insulating layer 35d is provided. On the bottom surface of the 2 nd trench 74d, a2 nd bottom surface insulating layer 36d is provided. In the 2 nd trench, a2 nd gate electrode 71d is provided so as to face the 1 st well layer 21 and the 1 st source layer 22 through a2 nd side insulating layer 35d.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. The method of manufacturing the semiconductor device in this embodiment is the same as the method of manufacturing the semiconductor device in embodiment 5 except that the 2 nd trench 74d is formed. The 2 nd trench 74d can be manufactured by the same manufacturing method as the 1 st trench 74.
As described above, the semiconductor device in the present embodiment is provided with the 2 nd trench 74d on the n-type column layer 13 in addition to the 1 st trench 74 and in the direction parallel to the 1 st trench 74. Accordingly, the channel width density is larger than that of the semiconductor device in embodiment mode 5 in correspondence with the amount of the 2 nd trench 74d. As a result, the channel resistance of the semiconductor device is further reduced.
Embodiment 10
The structure of the present embodiment will be described below with reference to fig. 32 to 33. Fig. 32 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines K-K' of fig. 33. Fig. 33 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. The J-J 'section of the semiconductor device in embodiment 9 shown in fig. 30 has the same structure as the K-K' section of the semiconductor device in this embodiment shown in fig. 32. Most of the semiconductor device of this embodiment is common to embodiment 9, and only differences from the semiconductor device of embodiment 9 will be described.
As shown in fig. 33, the semiconductor device according to the present embodiment includes a2 nd trench 74b (a portion surrounded by a one-dot chain line in fig. 33) in a vertical direction in a planar view with respect to the 1 st trench 74 and the 2 nd trench 74d in a stripe shape in planar view. The 2 nd trench 74b is provided in the n-type column layer 13. Inside the 2 nd trench 74b, a2 nd gate electrode 71b is provided. The 2 nd gate electrode 71b is provided so as to face the 1 st well layer 21 and the 1 st source layer 22 through the 2 nd side insulating layer 35 b. The 2 nd groove 74b is connected to the 1 st groove 74 in plan view. The 2 nd groove 74b is connected to the 2 nd groove 74d in plan view.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. The method of manufacturing the semiconductor device in this embodiment is the same as the method of manufacturing the semiconductor device in embodiment 9 except that the 2 nd trench 74b is formed. The 2 nd trench 74b can be manufactured by the same manufacturing method as the 1 st trench 74 and the 2 nd trench 74 d.
As described above, the semiconductor device according to the present embodiment has the 2 nd trench 74b formed in the vertical direction in a planar view with respect to the 1 st trench 74 and the 2 nd trench 74d in a stripe shape in planar view. Accordingly, the channel width density is larger than that of the semiconductor device in embodiment 9 in correspondence with the amount of the 2 nd trench 74b. As a result, the channel resistance of the semiconductor device is further reduced.
The 1 st gate electrode 71, the 2 nd gate electrode 71d, and the 2 nd gate electrode 71b may not be directly connected. The 1 st gate electrode 71, the 2 nd gate electrode 71d, and the 2 nd gate electrode 71b may be electrically connected. Even in this case, the same effect is achieved.
Embodiment 11
The structure of the present embodiment will be described below with reference to fig. 34 to 37. Fig. 34 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines L-L' of fig. 35. Fig. 35 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. Most of the semiconductor device of this embodiment is common to embodiment 10, and only differences from the semiconductor device of embodiment 10 will be described.
As shown in fig. 34, the semiconductor device of the present embodiment includes a 4 th trench 74e (a portion surrounded by a one-dot chain line in fig. 35) in the p-type column layer 14 in addition to the 1 st trench 74 and the 2 nd trench 74 d. As shown in fig. 35, the 4 th groove 74e is provided parallel to the 1 st groove 74 and the 2 nd groove 74d in a plan view. In the 4 th trench 74e, a 4 th gate electrode 71e is provided. A 4 th side insulating layer 35e is provided on the side surface inside the 4 th trench 74 e. The 4 th side insulating layer 35e on both sides in the 4 th trench 74e is connected to the 2 nd well layer and the 2 nd source layer. On the bottom surface of the 4 th trench 74e, a 4 th bottom surface insulating layer 36e is provided. Inside the 4 th trench 74e, a 4 th gate electrode 71e is provided so as to face the 2 nd well layer 26 and the 2 nd source layer 27a through the 4 th side insulating layer 35e.
As shown in fig. 35, the semiconductor device according to the present embodiment has the 1 st trench 74 having a stripe shape in a planar view, and the 2 nd trench 74b is provided in the n-type column layer 13 in a vertical direction in a planar view, as in embodiment 10. Further, the extension of the 2 nd trench 74b is provided in the 3 rd trench 74c. The 3 rd trench 74c is disposed within the p-type pillar layer 14. Inside the 3 rd trench 74c, a 3 rd gate electrode 71c is provided.
Further, as shown in fig. 35, the semiconductor device according to the present embodiment includes the 2 nd trench 74d in the parallel direction in a planar view, as in embodiment 10, with respect to the 1 st trench 74 in a stripe shape in a planar view. The 2 nd trench 74d is provided in the n-type column layer 13. The 1 st groove 74 having a stripe shape in plan view is provided with the 4 th groove 74e in a parallel direction in plan view. The 4 th trench 74e is disposed within the p-type pillar layer 14.
Fig. 36 and 37 are cross-sectional views of the semiconductor device according to the present embodiment, and are cross-sectional views of portions connecting the auxiliary lines M-M' of fig. 35. Wherein fig. 36 is a cross-sectional view of M-M' viewed from above the paper surface of fig. 35. Fig. 37 is a cross-sectional view of M-M' from below the paper surface of fig. 35. According to fig. 37 and 38, the 3 rd gate electrode 71c is provided so as to face the 2 nd well layer 26 through the 3 rd side insulating layer 35c and the 3 rd bottom insulating layer 36 c.
According to fig. 36 and 37, in the on state of the semiconductor device, the portions of the 2 nd well layer 26 in contact with the 1 st side insulating layer 35, the 3 rd side insulating layer 35c, and the 4 th side insulating layer 35e are inverted to form channels. As a result, as shown in fig. 36, a positive voltage is applied to the drain electrode 92, and a current flows in the direction of an arrow 504. That is, the channel width density can be increased. Therefore, in the semiconductor device according to the present embodiment, the channel resistance on the 2 nd well layer 26 side is reduced, and the on-resistance of the semiconductor device is reduced, as compared with the semiconductor device according to embodiment 10.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. The method of manufacturing the semiconductor device in this embodiment is the same as the method of manufacturing the semiconductor device in embodiment 10, except that the 3 rd trench 74c and the 4 th trench 74e are formed. The 3 rd trench 74c and the 4 th trench 74e can be manufactured by the same manufacturing method as the 1 st trench 74, the 2 nd trench 74b and the 2 nd trench 74 d.
As described above, in the semiconductor device according to the present embodiment, the 3 rd trench 74c is formed in addition to the 1 st trench 74 and the 2 nd trench 74b in plan view, on the extension of the 2 nd trench 74 b. Further, the 4 th groove 74e is formed in a parallel direction in a plan view with respect to the 1 st groove 74 having a stripe shape in a plan view. Accordingly, the channel width density is larger than that of the semiconductor device in embodiment 10 in correspondence with the amount of the 3 rd trench 74c and the 4 th trench 74e. As a result, the channel resistance of the semiconductor device is further reduced.
The 3 rd gate electrode 71c and the 4 th gate electrode 71e may not be directly connected to the 1 st gate electrode 71, the 2 nd gate electrode 71b, and the 2 nd gate electrode 71 d. The 3 rd gate electrode 71c and the 4 th gate electrode 71e may be electrically connected to the 1 st gate electrode 71, the 2 nd gate electrode 71b, and the 2 nd gate electrode 71 d. Even in this case, the same effect is achieved.
The semiconductor device in this embodiment may not include the 2 nd trench 74b and the 2 nd trench 74d. Even in this case, the channel width density is larger than that of the semiconductor device in embodiment 5 in correspondence with the amount of the 3 rd trench 74c and the 4 th trench 74 e. As a result, the channel resistance of the semiconductor device is further reduced.
Embodiment 12
The structure of the present embodiment will be described below with reference to fig. 38 to 39. Fig. 38 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines N-N' of fig. 39. Fig. 39 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. The E-E 'cross section of the semiconductor device in embodiment 5 shown in fig. 20 has the same structure as the N-N' cross section of the semiconductor device in the present embodiment shown in fig. 38. Most of the semiconductor device of this embodiment is common to embodiment 7, and only differences from the semiconductor device of embodiment 7 will be described.
As shown in fig. 38, the semiconductor device of the present embodiment includes a super junction layer 15a instead of the super junction layer 15. The super junction layer 15a has an n-type pillar layer 13a instead of the n-type pillar layer 13. The super junction layer 15a has a p-type pillar layer 14a instead of the p-type pillar layer 14. The n-type pillar layer 13a is arranged to have a lattice shape in a plan view. The p-type pillar layer 14a is formed in a dot shape in a divided region of the n-type pillar layer 13a having a lattice shape in a plan view.
The 1 st trench 74 is provided at the boundary between the n-type column layer 13a and the p-type column layer 14 a. The 1 st trench 74 is entirely within the p-type cylinder layer 14 a. As shown in fig. 39, the 1 st groove 74 is constituted by a1 st groove 74f and a1 st groove 74 g.
As shown in fig. 39, the 1 st trench 74f is provided at the boundary (a portion surrounded by a broken line in fig. 39) between the n-type column layer 13a and the p-type column layer 14 a. The 1 st trench 74f is entirely within the p-type cylinder layer 14 a. The 1 st groove 74f has a side surface and a bottom surface. The bottom surface of the 1 st trench 74f is formed deeper than the 1 st well layer 21.
A 1 st side insulating layer 35f including silicon dioxide is formed on the entire side surface of the 1 st trench 74 f. A 1 st bottom insulating layer, not shown, including silicon dioxide is formed on the entire bottom surface of the 1 st trench 74 f. The 1 st side insulating layer 35f is provided so as to be in contact with the 1 st well layer 21 and the 1 st source layer 22. The 1 st bottom insulating layer, not shown, is provided so as to contact the p-type column layer 14 a. The 1 st gate electrode 71f is disposed in the 1 st trench 74 f. The 1 st gate electrode 71f faces the 1 st well layer 21 and the 1 st source layer 22 through the 1 st side insulating layer 35f. The 1 st gate electrode 71f faces the p-type column layer 14a through a 1 st bottom insulating layer not shown. Doped polysilicon is used as a material of the 1 st gate electrode 71f, for example.
As shown in fig. 39, the 1 st trench 74g is provided at the boundary between the n-type column layer 13a and the p-type column layer 14a (a portion surrounded by a one-dot chain line in fig. 39). The 1 st trench 74g is entirely within the p-type cylinder layer 14 a. The 1 st groove 74g has a side surface and a bottom surface. The bottom surface of the 1 st trench 74g is formed deeper than the 1 st well layer 21. As shown in fig. 39, the 1 st groove 74g is provided in a direction perpendicular to the 1 st groove 74f in a plan view. The 1 st trench 74f and the 1 st trench 74g are connected to each other and are provided so as to surround the outer periphery of the p-type column layer 14a having a dot shape in a plan view.
A1 st side insulating layer 35g including silicon dioxide is formed on the entire side surface of the 1 st trench 74 g. A1 st bottom insulating layer 36g including silicon dioxide is formed on the entire bottom surface of the 1 st trench 74 g. The 1 st side insulating layer 35g is provided so as to be in contact with the 1 st well layer 21 and the 1 st source layer 22. The 1 st bottom insulating layer 36g is provided so as to contact the p-type column layer 14 a. The 1 st gate electrode 71g is disposed in the 1 st trench 74 g. The 1 st gate electrode 71g faces the 1 st well layer 21 and the 1 st source layer 22 through the 1 st side insulating layer 35g. The 1 st gate electrode 71g faces the p-type column layer 14a through the 1 st bottom insulating layer 36g. Doped polysilicon is used as a material of the 1 st gate electrode 71g, for example.
As shown in fig. 39, a2 nd trench 74h (a portion surrounded by a double-dashed line in fig. 39) is provided in the n-type column layer 13 a. The 2 nd groove 74h is provided in the extension of the 1 st groove 74f in plan view. The 2 nd groove 74h is provided in a direction perpendicular to the 1 st groove 74g in plan view. On the side surface inside the 2 nd trench 74h, a2 nd side surface insulating layer 35h is provided. A2 nd bottom insulating layer, not shown, is provided on the bottom surface of the 2 nd trench 74 h. In the 2 nd trench 74h, a2 nd gate electrode 71h is provided so as to face the 1 st well layer 21 and the 1 st source layer 22 through the 2 nd side insulating layer 35h. As shown in fig. 39, the 2 nd groove 74h is connected to the 1 st groove 74g in plan view.
As shown in fig. 39, the 2 nd trench 74i (the portion surrounded by the double solid line in fig. 39) is provided in the n-type column layer 13 a. The 2 nd groove 74i is provided in the extension of the 1 st groove 74g in plan view. The 2 nd trench 74i is provided in a direction perpendicular to the 1 st trench 74f in plan view. On the side surface inside the 2 nd trench 74i, a2 nd side surface insulating layer 35i is provided. A2 nd bottom insulating layer, not shown, is provided on the bottom surface of the 2 nd trench 74 i. In the 2 nd trench 74i, a2 nd gate electrode 71i is provided so as to face the 1 st well layer 21 and the 1 st source layer 22 through the 2 nd side insulating layer 35i. As shown in fig. 39, the 2 nd groove 74i is connected to the 1 st groove 74g in plan view. The 1 st trench 74f, the 1 st trench 74g, the 2 nd trench 74h, and the 2 nd trench 74i are formed so as to have a lattice shape in a plan view.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. The method of manufacturing a semiconductor device according to the present embodiment is similar to the method of manufacturing a semiconductor device according to embodiment 7 in that the n-type pillar layer 13a is formed in a lattice shape, and the p-type pillar layer 14a is formed in a dot shape in a closed region of the n-type pillar layer 13 a. The 1 st trench 74f and the 1 st trench 74g may be formed so as to extend around the p-type column layer 14a formed in a dot shape, and the 1 st trench 74f, the 1 st trench 74g, the 2 nd trench 74h, and the 2 nd trench 74i may be formed so as to have a lattice shape in a plan view.
As described above, the semiconductor device according to the present embodiment includes: a 1 st bottom insulating layer, not shown, provided on the bottom surface of the 1 st trench 74 f; and a 1 st gate electrode 71f provided in the 1 st trench 74f and facing the 1 st well layer 21 and the 1 st source layer 22 through the 1 st side insulating layer 35f, and facing the p-type column layer 14a formed in a dot shape through a 1 st bottom insulating layer not shown. As a result, as in the semiconductor device of embodiment 1, the electric field applied to the 1 st bottom insulating layer 36f by the p-type column layer 14a depleted in the off state of the semiconductor device of this embodiment is reduced. As a result, a highly reliable semiconductor device can be obtained.
The present invention further includes: a 1 st bottom insulating layer 36g provided on the bottom surface of the 1 st trench 74 g; and a 1 st gate electrode 71g provided in the 1 st trench 74g and facing the 1 st well layer 21 and the 1 st source layer 22 through the 1 st side insulating layer 35g, and facing the p-type column layer 14a formed in a dot shape through the 1 st bottom insulating layer 36 g. As a result, as in the semiconductor device of embodiment 1, the electric field applied to the 1 st bottom insulating layer 36g by the p-type column layer 14a depleted in the off state of the semiconductor device of this embodiment is reduced. As a result, a highly reliable semiconductor device can be obtained.
In the semiconductor device according to the present embodiment, the 1 st trench 74f is provided at the boundary between the n-type column layer 13a and the p-type column layer 14a in addition to the 1 st trench 74g, the 2 nd trench 74h, and the 2 nd trench 74 i. The 1 st groove 74f is provided in a direction perpendicular to the 1 st groove 74g in a plan view. The 1 st trench 74f is entirely within the p-type cylinder layer 14 a. Accordingly, the channel width density is larger than that of the semiconductor device in embodiment 7 in accordance with the amount of the 1 st trench 74f. As a result, the channel resistance of the semiconductor device is further reduced.
The 2 nd gate electrode 71h and the 2 nd gate electrode 71i may not be directly connected to the 1 st gate electrode 71 g. The 2 nd gate electrode 71h and the 2 nd gate electrode 71i may be electrically connected to the 1 st gate electrode 71 g. Even in this case, the same effect is achieved.
The semiconductor device in this embodiment may not include the 2 nd trench 74h and the 2 nd trench 74i. Even in this case, as in embodiment 1, the electric field applied to the 1 st bottom insulating layer 36g and the 1 st trench 74f, which are not shown, by the p-type column layer 14a depleted in the off state of the semiconductor device in this embodiment is reduced. As a result, a highly reliable semiconductor device can be obtained.
In the p-type column layer 14a in the present embodiment, the 2 nd well layer 26 and the 2 nd source layer 27 may not be provided. In this case, as in embodiment 1, a step of forming a p-type semiconductor layer or the like for reducing an electric field is not required in the existing semiconductor device having the super junction structure.
Embodiment 13
The structure of the present embodiment will be described below with reference to fig. 40 to 41. Fig. 40 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion of the auxiliary line connecting O-O' in fig. 41. Fig. 41 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. Most of the semiconductor device of this embodiment is common to embodiment 12, and only differences from the semiconductor device of embodiment 12 will be described.
As shown in fig. 40, the semiconductor device according to the present embodiment is provided with a2 nd trench 74d in the n-type pillar layer 13 in addition to the 1 st trench 74, as compared with the semiconductor device according to embodiment 12.
As shown in fig. 41, the semiconductor device in the present embodiment is provided with a2 nd trench 74d (a portion surrounded by a one-dot chain line in fig. 41) between the 1 st trench 74g and between the 2 nd trenches 74i in plan view, in addition to the semiconductor device in embodiment 12. The 2 nd groove 74d is provided parallel to the 1 st groove 74g in plan view. The 2 nd groove 74d is provided parallel to the 2 nd groove 74i in plan view. In fig. 41, the number of 2 nd grooves 74d provided between the 1 st grooves 74g and between the 2 nd grooves 74i in plan view is 1, but may be plural.
As shown in fig. 41, the 2 nd grooves 74b (portions surrounded by broken lines in fig. 41) are further provided between the 1 st grooves 74f and between the 2 nd grooves 74h in plan view. The 2 nd groove 74b is provided parallel to the 1 st groove 74f in plan view. The 2 nd groove 74b is provided parallel to the 2 nd groove 74h in plan view. In fig. 41, the number of 2 nd grooves 74b provided between the 1 st grooves 74f and between the 2 nd grooves 74h in plan view is 1, but may be plural. As shown in fig. 41, the 2 nd groove 74b and the 2 nd groove 74d are connected in a plan view. The 2 nd trench 74b is connected to the 1 st trench 74g or the 2 nd trench 74i in a plan view.
As shown in fig. 40 and 41, 4 2p+ -type layers 52 are provided in the 2 nd well layer 26 so as to contact the front ohmic electrode 81. The number of the 2p+ -type layers 52 is described as 4, but the number is not limited.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. In the method for manufacturing a semiconductor device according to the present embodiment, the 2 nd trench 74d may be provided between the 1 st trenches 74g and between the 2 nd trenches 74i in a plan view, as compared with the method for manufacturing a semiconductor device according to embodiment 12. Further, the 2 nd grooves 74b may be provided between the 1 st grooves 74f and between the 2 nd grooves 74h in a plan view.
As described above, the semiconductor device in this embodiment mode is provided with the 2 nd trench 74d between the 1 st trench 74g and between the 2 nd trenches 74i in plan view, in addition to the semiconductor device in embodiment mode 12. The 2 nd grooves 74d provided between the 1 st grooves 74 are provided parallel to the 1 st grooves 74 in a plan view. Further, the 2 nd grooves 74b are provided between the 1 st grooves 74f and between the 2 nd grooves 74h in plan view. As a result, the channel width density is greater than that of the semiconductor device in embodiment 12. As a result, the channel resistance of the semiconductor device is further reduced.
The 2 nd gate electrode 71b may not be directly connected to the 2 nd gate electrode 71d, the 1 st gate electrode 71g, and the 2 nd gate electrode 71 i. The 2 nd gate electrode 71b may be electrically connected to the 2 nd gate electrode 71d, the 1 st gate electrode 71g, and the 2 nd gate electrode 71 i. Even in this case, the same effect is achieved.
Embodiment 14
The structure of the present embodiment will be described below with reference to fig. 42 to 43. Fig. 42 is a cross-sectional view of the semiconductor device according to the present embodiment, and is a cross-sectional view of a portion connecting the auxiliary lines P-P' in fig. 43. Fig. 43 is a plan view showing the upper surface of the semiconductor region in the semiconductor device of the present embodiment. Most of the semiconductor device of this embodiment is common to embodiment 5, and only differences from the semiconductor device of embodiment 5 will be described.
As shown in fig. 42, the semiconductor device of the present embodiment includes a super junction layer 15b instead of the super junction layer 15. The super junction layer 15b has an n-type pillar layer 13b instead of the n-type pillar layer 13. The width of the n-type pillar layer 13b is smaller than the p-type pillar layer 14. That is, the spacing of the p-type pillar layers 14 is less than the spacing of the n-type pillar layers.
Next, a method for manufacturing a semiconductor device according to this embodiment will be described. The method of manufacturing the semiconductor device in this embodiment is the same as that in embodiment 5, except that the width of the n-type pillar layer 13b is made smaller than the width of the p-type pillar layer 14.
As described above, in the semiconductor device in the present embodiment, the width of the n-type pillar layer 13b is smaller than the width of the p-type pillar layer 14. That is, the spacing of the p-type pillar layers 14 is less than the spacing of the n-type pillar layers. Accordingly, the channel width density of the semiconductor device increases by an amount corresponding to the small width of the n-type pillar layer 13 b. As a result, the channel resistance of the semiconductor device is further reduced.
In addition, in the semiconductor device of the present embodiment, the n-type pillar layer 13b may have a lattice shape in a plan view, and the p-type pillar layer 14 may have a dot shape in a closed region of the n-type pillar layer 13b having a lattice shape in a plan view, similarly to the embodiments 12 and 13. Even in this case, the channel width density of the semiconductor device increases by an amount corresponding to the smaller width of the n-type pillar layer 13 b. As a result, the same effect as in the present embodiment is obtained in which the channel resistance of the semiconductor device is reduced.
Embodiment 15
The power conversion device in this embodiment is a device to which the semiconductor devices in embodiments 1 to 14 are applied. In the power conversion device according to the present embodiment, a case where the present invention is applied to a 3-phase inverter will be described.
Fig. 44 is a functional configuration diagram showing a configuration of a power conversion device 301 to which the power conversion device according to the present embodiment is applied. The power source 321 and the load 331 are connected to the power conversion device 301 shown in fig. 44. The power source 321 is, for example, a power source that converts commercial AC power into DC power by an AC/DC converter, and supplies the DC power to the power conversion device 301.
The power conversion device 301 is a 3-phase inverter connected between the power source 321 and the load 331. The power conversion device 301 converts dc power supplied from the power source 321 into ac power, and supplies the ac power to the load 331. As shown in fig. 44, the power conversion device 301 includes a main conversion unit 311 that converts dc power into ac power and outputs the ac power, a driving unit 312 that outputs a driving signal that drives a switching element that constitutes the main conversion unit 311, and a control unit 313 that outputs a control signal that controls the driving unit 312 to the driving unit 312. The load 331 is a 3-phase motor driven by ac power supplied from the power conversion device 301.
The main converter 311 uses the dc power supplied from the power source 321 as input power. The main converter 311 includes a switching element and a flywheel diode. The main converter 311 converts input power into ac power by switching with a switching element, and supplies the ac power to the load 331. There are various examples of specific circuit configurations of the main conversion unit 311. For example, the main converter 311 according to the present embodiment is a 2-level 3-phase full-bridge circuit. The main converter 311 according to the present embodiment may be configured of 6 switching elements and 6 flywheel diodes connected in antiparallel to the respective switching elements.
Each switching element of the main converter 311 is the semiconductor device 314 described in any of embodiments 1 to 14. The 6 switching elements are connected in series for every 2 switching elements to constitute upper and lower branches, and each of the upper and lower branches constitutes a U-phase, a V-phase, and a W-phase of the full bridge circuit. The load 331 is connected to the output terminals of the upper and lower branches, that is, to 3 output terminals of the main converter 311.
The driving unit 312 generates a driving signal for driving the switching element of the main converting unit 311, and outputs the driving signal to the control electrode of the switching element of the main converting unit 311. Specifically, in accordance with the control signal output from the control unit 313, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
The control unit 313 controls the switching element of the main conversion unit 311 so as to supply desired electric power to the load 331. Specifically, for example, when the main converter 311 is operated by PWM (Pulse Width Modulation ) control, a switching pattern of the switching element is calculated from the electric power to be supplied to the load 331, and a control signal for realizing the switching pattern is output to the driver 312. The driving unit 312 outputs an on signal or an off signal as a driving signal to the control electrode of each switching element in accordance with the control signal.
In the power conversion device according to the present embodiment, the semiconductor devices according to embodiments 1 to 14 are provided as the switching elements constituting the main conversion unit 311, and therefore, the power conversion device having a small loss and capable of performing a high-speed switching operation is provided.
In the present embodiment, the power supply is described as a power supply for converting a commercial AC power supply into a DC power supply by an AC/DC converter, but other types of power supplies may be used. For example, the power supply may be a commercial DC power supply, a solar battery, a storage battery, a rectifier circuit connected to an AC power supply, an output of an AC/DC converter, an output of a DC/DC converter, or the like.
In the semiconductor devices according to embodiments 1 to 14, the semiconductor substrate is described as the silicon carbide substrate 11, but the silicon carbide substrate is not necessarily required, and may be, for example, silicon, diamond, another wide band gap semiconductor, a compound semiconductor, an oxide semiconductor, or the like.
In the semiconductor devices of embodiments 1 to 14, the 1 st main surface of the silicon carbide substrate 11 is inclined by 4 ° with respect to the (0001) plane in the [11-20] direction, but for example, other crystal planes such as the (000-1) plane may be used, and the off angle may be other angles such as 0 ° to 8 °. The polytype of silicon carbide is 4H, but may be other polytypes such as 3C and 6H.
In the semiconductor devices according to embodiments 1 to 14, the description has been given with the 1 st conductivity type being n-type and the 2 nd conductivity type being p-type, but the 1 st conductivity type may be p-type and the 2 nd conductivity type may be n-type.
In the semiconductor devices according to embodiments 1 to 14, al is described as an example of the p-type impurity, but other group III elements such as boron (B) and gallium (Ga) may be used. N is described As an example of the N-type impurity, but other V group elements such As phosphorus (P) and arsenic (As) may be used.
In the semiconductor devices according to embodiments 1 to 14, ion implantation is used in forming the 1 st well layer 21, but for example, after epitaxially growing a p-type semiconductor layer, n-type impurities may be implanted into a semiconductor region other than the 1 st well layer 21, which is to be n-type. The other semiconductor region formed by ion implantation may be formed by epitaxial growth as long as it is formed as a manufacturing process.
In the semiconductor devices according to embodiments 1 to 14, silicon dioxide is used as the material of the 1 st side surface insulating layer 35, the 1 st bottom surface insulating layer 36a, the 2 nd side surface insulating layer 35b, the 2 nd bottom surface insulating layer 36b, the 3 rd side surface insulating layer 35c, the 3 rd bottom surface insulating layer 36c, the 2 nd side surface insulating layer 35d, the 2 nd bottom surface insulating layer 36d, the 4 th side surface insulating layer 35e, the 4 th bottom surface insulating layer 36e, the 1 st side surface insulating layer 35f, the 1 st bottom surface insulating layer not shown in the 1 st trench 74f, the 1 st side surface insulating layer 35g, the 1 st bottom surface insulating layer 36g, the 2 nd side surface insulating layer 35h, the 2 nd bottom surface insulating layer not shown in the 2 nd trench 74h, the 2 nd side surface insulating layer 35i, and the 2 nd bottom surface insulating layer not shown in the 2 nd trench 74i, but may be a thermal oxide film formed by a thermal oxidation method or a deposited film formed by a CVD method. Further, an insulating layer other than silicon dioxide such as silicon nitride, aluminum oxide, or a high dielectric constant insulating layer may be used.
In addition, in the semiconductor devices according to embodiments 1 to 14, doped polysilicon is used as a material of the 1st gate electrode 71, the 2 nd gate electrode 71b, the 3 rd gate electrode 71c, the 2 nd gate electrode 71d, the 4 th gate electrode 71e, the 1st gate electrode 71f, the 1st gate electrode 71g, the 2 nd gate electrode 71h, and the 2 nd gate electrode 71i, but the conductivity type thereof may be n-type or p-type, and aluminum, an aluminum alloy, other metals, a metal silicide film, or a laminate thereof may be used instead of doped polysilicon.
In the semiconductor devices according to embodiments 1 to 14, the source electrode 82 is made of aluminum, but may be made of other metals, alloys, or a laminate thereof.
In the semiconductor devices according to embodiments 1 to 14, the n-type column layer 13 and the p-type column layer 14 are formed in a stripe shape, and the 11p+ type layer 23 and the 2p+ type layer 52 are formed in a stripe shape. The 1st p+ type layer 23 and the 2nd p+ type layer 52 may overlap the p-type semiconductor region below at least at 1 part in a plan view. However, in the case where the number of contact points with the underlying p-type semiconductor region is small, there are cases where problems such as an increase in switching loss and deterioration in reliability occur.
The semiconductor devices in embodiments 1 to 11 and 14 are arranged in a stripe shape in a plan view in the n-type pillar layer 13 or in the n-type pillar layer 13b and the p-type pillar layer 14. However, the n-type pillar layer 13 or the n-type pillar layer 13b and the p-type pillar layer 14 may be arranged in a stripe shape in a plan view to be an active region. In the terminal region, the n-type pillar layer 13 or the n-type pillar layer 13b and the p-type pillar layer 14 need not necessarily be arranged in a stripe shape in a plan view.
The semiconductor devices in embodiments 12 to 13 are arranged such that the n-type pillar layer 13a has a lattice shape in a plan view, and the p-type pillar layer 14a has a dot shape divided by the n-type pillar layer 13a in a plan view. However, the n-type column layer 13a may be arranged in a lattice shape in a plan view, and the p-type column layer 14a may be arranged in a dot shape divided by the n-type column layer 13a in a plan view. In the terminal region, the n-type column layer 13a is not required to be arranged in a lattice shape in a plan view, and the p-type column layer 14a is not required to be arranged in a dot shape divided by the n-type column layer 13a in a plan view.
The dimensions, the formation method, the conditions of the heat treatment, and the like of the respective constituent elements of the semiconductor devices in embodiments 1 to 14 are described using specific examples, but these are not limited to the presented examples and may be appropriately modified.
Further, as long as the semiconductor device has the structure of the semiconductor device in embodiments 1 to 14, the effect of the present invention can be obtained even when manufactured by another manufacturing method, regardless of the manufacturing method.
In the semiconductor devices according to embodiments 2 to 14, the 2 nd well layer 26 is further included in the p-type column layer 14 and the 2 nd conductive type region in the p-type column layer 14 a. The impurity concentration of the 2 nd conductivity type of the 2 nd well layer 26 may be the same as the impurity concentration of the 2 nd conductivity type in the region other than the 2 nd well layer 26 in the 2 nd conductivity type region in the p-type cylinder layer 14 and in the p-type cylinder layer 14 a. That is, the 2 nd well layer 26 may be omitted.
The present invention is not limited to embodiments 1 to 15. Some of these can be changed, omitted, or the like within the scope of the technical idea of the present invention.
Industrial applicability
The present invention can be applied to a power semiconductor device having a super junction structure.

Claims (20)

1. A semiconductor device includes a semiconductor region having a1 st main surface and a 2 nd main surface on the opposite side of the 1 st main surface, wherein,
The semiconductor region includes:
a1 st column layer of the 1 st conductivity type and a2 nd column layer of the 2 nd conductivity type alternately arranged along the 1 st main surface;
a1 st well layer of the 2 nd conductive type, which is arranged in the 1 st column layer and on the upper surface of the 1 st column layer;
a1 st source layer of 1 st conductivity type disposed within the 1 st well layer and on an upper surface of the 1 st well layer;
a1 st side insulating layer provided on a side surface of the 1 st trench provided at a boundary between the 1 st pillar layer and the 2 nd pillar layer, and connected to the 1 st well layer and the 1 st source layer;
The 1 st bottom surface insulating layer is arranged on the bottom surface in the 1 st groove, and at least one part of the 1 st bottom surface insulating layer is connected with the 2 nd column layer; and
A 1 st gate electrode disposed in the 1 st trench and facing the 1 st well layer and the 1 st source layer through the 1 st side insulating layer and facing the 2 nd column layer through the 1 st bottom insulating layer,
The 2 nd pillar layer has a2 nd source layer of 1 st conductivity type disposed within the 2 nd pillar layer and on an upper surface of the 2 nd pillar layer,
The 1 st side insulating layer is arranged on two sides in the 1 st groove and is connected with the 2 nd conductive type region in the 2 nd column layer and the 2 nd source layer,
The 1 st bottom insulating layer is connected with the 2 nd conductive type region in the 2 nd column layer,
The bottom surface of the 2 nd source layer is closer to the 2 nd main surface than the bottom surface of the 1 st source layer.
2. The semiconductor device according to claim 1, wherein,
The 2 nd pillar layer includes a2 nd well layer of a2 nd conductivity type provided in the 2 nd pillar layer and on an upper surface of the 2 nd pillar layer,
The 2 nd source layer is arranged in the 2 nd well layer and on the upper surface of the 2 nd well layer.
3. The semiconductor device according to claim 1, wherein,
The thickness of the 1 st bottom insulating layer is smaller than that of the 1 st side insulating layer.
4. The semiconductor device according to claim 2, wherein,
The thickness of the 1 st bottom insulating layer is smaller than that of the 1 st side insulating layer.
5. The semiconductor device according to any one of claims 1 to 4, wherein,
The 1 st bottom surface insulating layer is connected with the 2 nd column layer and the 1 st column layer.
6. The semiconductor device according to any one of claims 1 to 4, comprising:
A 3 rd side insulating layer provided on a side surface in a 3 rd trench provided in the 2 nd column layer in a direction perpendicular to the 1 st trench in a plan view;
the 3 rd bottom surface insulating layer is arranged on the bottom surface of the 3 rd groove; and
And a 3 rd gate electrode disposed in the 3 rd trench and facing the 2 nd conductive type region and the 2 nd source layer in the 2 nd column layer through the 3 rd side insulating layer.
7. The semiconductor device according to claim 6, wherein,
The 3 rd gate electrode is connected with the 1 st gate electrode.
8. The semiconductor device according to any one of claims 1 to 4, comprising:
a4 th side insulating layer provided on a side surface in the 4 th trench provided in the 2 nd column layer in a direction parallel to the 1 st trench in a plan view, both side surfaces being in contact with the 2 nd conductivity type region in the 2 nd column layer and the 2 nd source layer;
the 4 th bottom surface insulating layer is arranged on the bottom surface of the 4 th groove; and
And a4 th gate electrode disposed in the 4 th trench and facing the 2 nd conductive type region in the 2 nd column layer and the 2 nd source layer through the 4 th side insulating layer.
9. The semiconductor device according to any one of claims 1 to 4, comprising:
a2 nd side insulating layer provided on a side surface in the 2 nd trench provided in the 1 st column layer;
the 2 nd bottom surface insulating layer is arranged on the bottom surface in the 2 nd groove; and
And a2 nd gate electrode disposed in the 2 nd trench and facing the 1 st well layer and the 1 st source layer through the 2 nd side insulating layer.
10. The semiconductor device according to claim 9, wherein,
The 2 nd groove is provided in a direction parallel to the 1 st groove in a plan view.
11. The semiconductor device according to claim 9, wherein,
The 2 nd gate electrode is connected with the 1 st gate electrode.
12. The semiconductor device according to claim 10, wherein,
The 2 nd gate electrode is connected with the 1 st gate electrode.
13. The semiconductor device according to any one of claims 1 to 4, wherein,
In the active region, the 1 st pillar layer and the 2 nd pillar layer are arranged in a stripe shape in a plan view.
14. The semiconductor device according to any one of claims 1 to 4, wherein,
In the active region, the 1 st pillar layer is arranged in a lattice shape in a plan view, and the 2 nd pillar layer is arranged in a dot shape divided by the 1 st pillar layer in a plan view.
15. The semiconductor device of claim 13, wherein,
The spacing of the 2 nd column layers is smaller than the spacing of the 1 st column layers.
16. The semiconductor device of claim 14, wherein,
The spacing of the 2 nd column layers is smaller than the spacing of the 1 st column layers.
17. The semiconductor device of claim 13, wherein,
The interval of the 1 st column layer is constant, and the interval of the 2 nd column layer is constant.
18. The semiconductor device of claim 14, wherein,
The interval of the 1 st column layer is constant, and the interval of the 2 nd column layer is constant.
19. The semiconductor device according to any one of claims 1 to 4, wherein,
The semiconductor region includes silicon carbide.
20. A power conversion device is provided with:
a main conversion unit configured to convert input power using the semiconductor device according to any one of claims 1 to 19 as a switching element;
A driving unit that outputs a driving signal for driving the semiconductor device to the semiconductor device; and
And a control unit configured to output a control signal for controlling the driving unit to the driving unit.
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