CN112912743B - Calculation force control method, device, equipment and storage medium - Google Patents
Calculation force control method, device, equipment and storage medium Download PDFInfo
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Abstract
A method, a device, equipment and a storage medium for controlling calculation force, the method comprises the following steps: according to a frequency sweep command issued by a control host, controlling a target chip to perform frequency sweep operation, and determining a first calculation force value (101) of the target chip; the first calculation value is configured to the target chip (102). The first calculation force value of the target chip is determined through the scanning operation of the chip, and the chip is configured according to the determined first calculation force value of the target chip, so that the actual calculation force of the chip in the computing device can be improved, the calculation force of the computing device is improved, and the flexibility of calculation force configuration of the computing device is improved.
Description
Technical Field
The present application relates to the technical field of computing devices, and for example, to a method, an apparatus, a device, and a storage medium for controlling computing power.
Background
Computing devices play an important role in blockchain applications. With the increase of the full network computing power, various low-power consumption high-computing power computing devices are layered endlessly. Computing power is an important index for representing the capability and value of computing equipment.
In the existing computing equipment implementation scheme, after different production processes such as chip flow and chip mounting, the theoretical calculation force of the chips is reduced by a certain value, the descending values of different chips are different, an acceptable minimum calculation force value is usually set as a good product, and after the good product chips are assembled, all chips in the whole machine are set as the minimum calculation force capable of working, so that all chips can work normally.
However, the solutions of the prior art result in waste of the computing power of the chip higher than the lowest computing power, so how to effectively control the computing power of different chips is a technical problem to be solved.
Disclosure of Invention
The embodiment of the disclosure provides a calculation force control method, a calculation force control device, calculation force control equipment and a storage medium, which are used for controlling calculation force of a chip in a computing device so as to solve the problems of calculation force waste and the like of the computing device in the prior art.
A first aspect of an embodiment of the present disclosure provides a method for controlling a computing force, including:
according to a frequency sweep command issued by a control host, controlling a target chip to perform frequency sweep operation, and determining a first calculation force value of the target chip;
the first calculation value is configured to the target chip.
A second aspect of the disclosed embodiments provides a force control device, including:
the control module is used for controlling the target chip to carry out sweep frequency operation according to the sweep frequency command issued by the control host, and determining a first calculation value of the target chip;
and the configuration module is used for configuring the first calculation force value to the target chip.
A third aspect of an embodiment of the present disclosure provides a computing device including the computing force control apparatus provided in the second aspect.
A fourth aspect of the disclosed embodiments provides a computer-readable storage medium storing computer-executable instructions configured to perform the method of controlling computing power provided in the first aspect described above.
A fifth aspect of the disclosed embodiments provides a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the method of controlling the computational power provided in the first aspect described above.
A sixth aspect of the disclosed embodiments provides an electronic device, including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor, which when executed by the at least one processor, cause the at least one processor to perform the method of controlling computing power provided in the first aspect above.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:
FIG. 1 is a flow chart of a method for controlling computing power of a map according to an embodiment of the present application;
FIG. 2 is a flow chart of a method for controlling computing power according to another embodiment of the present application;
FIG. 3 is a schematic diagram of a complete machine workflow including frequency sweep according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a power calculation control device according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a power calculation control device according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the application.
Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. These drawings and the written description are not intended to limit the scope of the disclosed concept in any way, but to illustrate the inventive concept to those skilled in the art by reference to specific embodiments.
Detailed Description
So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
First, the terms involved in the present application will be explained:
EFUSE: is one-time programmable memory in the chip.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. In the following description of the embodiments, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
The first embodiment of the disclosure provides a method for controlling the calculation force of a chip. The execution subject of the calculation force control method is a calculation force control device, and the calculation force control device can be arranged in a computing device. Fig. 1 is a flow chart of a method for controlling computing power according to the present embodiment. The method comprises the following steps:
and step 101, controlling a target chip to perform sweep operation according to a sweep frequency command issued by a control host, and determining a first calculation force value of the target chip.
Step 102, configuring the first calculation force value to the target chip.
Specifically, in the whole machine working process or the whole machine function verification process of the computing device, first, the basic devices such as an initialization CPU, DDR, UART are required to be initialized, after the initialization, information can be read from EFUSE of each chip on the computing device, whether a static calculation force value is stored or not is judged, if the static calculation force value is not stored, a minimum operable calculation force value is configured for the chip, the chip is firstly operated with the minimum operable calculation force, and an operation algorithm is initialized, the operation algorithm can be a currency algorithm, and the initialization currency algorithm refers to determining a corresponding currency algorithm according to different currencies. And a monitoring interface is arranged to monitor a command sent by the control host, the command issued by the control host can comprise a frequency sweep command, an operation task command and the like, the operation task command refers to a task which is issued by the control host and needs to be decrypted, and an answer is obtained through operation by the power board and is returned to the control host. Wherein, a plurality of chips are arranged on the power calculating plate.
When the command issued by the control host is monitored to be a frequency sweep command, the target chip is controlled to perform frequency sweep operation according to the frequency sweep command issued by the control host, and a first calculation value of the target chip is determined. The sweep command may be a command word conforming to a protocol, and the sweep command may include information such as sweep identification, sweep type, sweep range, and the like. For example, a frequency sweep identification bit 3 in the command represents a frequency sweep command; the sweep frequency type comprises a static state and a dynamic state, for example, 0 represents the static state and 1 represents the dynamic state; the sweep frequency range is 700-500H/S (calculated force value), and the calculated force value refers to how many times the chip can calculate the hash value in 1 second. The power configuration of the chip may be controlled or otherwise configured by controlling the operating frequency of the chip, such as where the operating frequency of the chip has a correspondence to its power. The computational power of the chip is configured by setting the operating frequency of the chip. Specifically, how to configure the chip to operate with the calculated force value after determining the calculated force value of the chip is the prior art, which is not limited in this embodiment.
Optionally, the control host issues the sweep frequency command once after the computing device is powered up each time, or once after the chip is out of operation, and the calculated force value of the chip is redetermined.
The sweep frequency operation refers to that the chip performs encryption operation under different frequencies according to a sweep frequency range included in a sweep frequency command, and compares the encryption operation with a preset answer, and determines a maximum calculation force value of the chip operation or a calculation force value of the chip operation from the sweep frequency range.
The sweep frequency range is 700-500H/s, the chip starts encryption operation from 700 and compares with the preset answer, if the sweep frequency range is inconsistent with the preset answer, the chip performs encryption operation under 650H/s, and if the sweep frequency range is consistent with the preset answer, the chip can work under 650H/s, and the maximum calculation force value of the chip can be considered to be 650H/s. And so on, try from 700 down in sequence until the calculated force value that the chip can work is found as the maximum calculated force value of the chip. The number of encryption operations tried in the sweep frequency range can be set according to actual requirements, for example, according to a certain arithmetic sequence, 700-650-600-550-500, or can be determined according to other rules, which is not limited in this embodiment.
Alternatively, the sweep range may be swept, and one of the calculated force values that can be used by the target chip is selected as the first calculated force value of the target chip, or the first calculated force value of the target chip is determined according to a certain calculation, such as an average value, according to the calculated force value that can be used by the target chip. The embodiment is not limited.
After the first calculation force value of the target chip is determined, the first calculation force value is configured to the target chip so that the target chip can calculate with the calculation force of the first calculation force value. The method of configuring the first calculation force value to the target chip is that the effectiveness of the first calculation force value is effective only before the next sweep frequency command is issued to the target chip to reconfigure the calculation force value in the working process after the power-up, and the chip fails after the power-up. The next power up, the minimum operational force value or the sweep operation is required to be configured to determine the operational force value (which may be referred to as a second operational force value) of the target chip.
Alternatively, the target chip may be one or more. Plural means two or more.
According to the calculation force control method provided by the embodiment of the disclosure, the first calculation force value of the target chip is determined through the scanning operation of the chip, and the chip is configured according to the determined first calculation force value of the target chip, so that the actual calculation force of the chip in the computing device can be improved, the calculation force of the computing device is improved, and the flexibility of calculation force configuration of the computing device is improved.
The second embodiment of the disclosure further supplements the method for controlling the calculation force provided by the foregoing embodiment.
Fig. 2 is a flow chart of a method for controlling computing power according to the present embodiment.
As an implementation manner, on the basis of the foregoing embodiment, optionally, before the target chip is controlled to perform the sweep operation according to the sweep command issued by the control host, and the first calculation value of the target chip is determined, the method further includes:
step 201, monitoring whether the control host issues a frequency sweep command through a monitoring interface, wherein the frequency sweep command comprises a frequency sweep identifier, a frequency sweep type and a frequency sweep range.
Specifically, the control host computer can send the sweep frequency command once after the computing device is powered on each time, or can send the sweep frequency command once after the chip is out of work, and the calculated force value of the chip is redetermined. The monitoring interface can be set to monitor the command sent by the control host, the command issued by the control host can comprise a sweep frequency command, an operation task command and the like, the operation task command refers to a task which is issued by the control host and needs to be decrypted, and the power board obtains an answer through operation and returns the answer to the control host. Wherein, a plurality of chips are arranged on the power calculating plate.
When the command issued by the control host is monitored to be a frequency sweep command, the target chip is controlled to perform frequency sweep operation according to the frequency sweep command issued by the control host, and a first calculation value of the target chip is determined. The sweep command may be a command word conforming to a protocol, and the sweep command may include information such as sweep identification, sweep type, sweep range, and the like. For example, a frequency sweep identification bit 3 in the command represents a frequency sweep command; the sweep frequency type comprises a static state and a dynamic state, for example, 0 represents the static state and 1 represents the dynamic state; the sweep frequency range is 700-500H/S (calculated force value), and the calculated force value refers to how many times the chip can calculate the hash value in 1 second.
As another implementation manner, on the basis of the foregoing embodiment, optionally, after the target chip is controlled to perform the sweep operation according to the sweep command issued by the control host, the method further includes:
and step 2021, judging the frequency sweep type according to the frequency sweep command.
In step 2022, if the sweep type is a static sweep, the first calculation value is written into the memory EFUSE of the target chip.
Specifically, the sweep command may include information such as sweep identification, sweep type, sweep range, and the like. For example, a frequency sweep identification bit 3 in the command represents a frequency sweep command; the sweep frequency type comprises a static state and a dynamic state, for example, 0 represents the static state and 1 represents the dynamic state; the sweep frequency range is 700-500H/S. After monitoring the frequency sweep command, the frequency sweep type can be judged according to the frequency sweep command, if the frequency sweep type is static frequency sweep, the first calculated force value can be written into the EFUSE of the target chip, namely the static calculated force value of the target chip is stored into the EFUSE, and after the next power-on, the static calculated force value can be read from the EFUSE to configure the target chip, so that the chip operates according to the calculated force of the static calculated force value.
Optionally, if the determined first calculation force value is the maximum calculation force value of the target chip, writing the first calculation force value into the EFUSE, so that the target chip can perform subsequent calculation according to the maximum calculation force, thereby improving the calculation force of the computing device.
Optionally, if the sweep type is dynamic sweep, the first calculation value does not need to be written into the EFUSE of the target chip, and the first calculation value fails after the chip is powered down. The next power-on can carry out sweep frequency operation again to determine the calculation power value of the target chip again so as to configure the target chip.
As another implementation manner, based on the foregoing embodiment, optionally, according to a sweep frequency command issued by the control host, the control target chip performs a sweep frequency operation, and determining the first calculation force value of the target chip may specifically include:
step 2031, controlling the target chip to perform encryption operation under different frequencies according to the sweep frequency range included in the sweep frequency command, so as to obtain an operation result.
Step 2032, obtaining a first calculation force value of the target chip according to each calculation result and the corresponding preset result.
Specifically, after receiving a sweep frequency command issued by a control host, the target chip may be controlled to perform encryption operation under different frequencies according to a sweep frequency range included in the sweep frequency command, so as to obtain operation results, and a first calculation force value of the target chip is obtained according to each operation result and a corresponding preset result.
The sweep frequency operation refers to that the chip performs encryption operation under different frequencies according to a sweep frequency range included in a sweep frequency command, and compares the encryption operation with a preset answer, and determines a maximum calculation force value of the chip operation or a calculation force value of the chip operation from the sweep frequency range.
The sweep frequency range is 700-500H/s, the chip starts encryption operation from 700 and compares with the preset answer, if the sweep frequency range is inconsistent with the preset answer, the chip performs encryption operation under 650H/s, and if the sweep frequency range is consistent with the preset answer, the chip can work under 650H/s, and the maximum calculation force value of the chip can be considered to be 650H/s. And so on, try from 700 down in sequence until the calculated force value that the chip can work is found as the maximum calculated force value of the chip. The number of encryption operations tried in the sweep frequency range can be set according to actual requirements, for example, according to a certain arithmetic sequence, 700-650-600-550-500, or can be determined according to other rules, which is not limited in this embodiment.
Alternatively, the sweep range may be swept, and one of the calculated force values that can be used by the target chip is selected as the first calculated force value of the target chip, or the first calculated force value of the target chip is determined according to a certain calculation, such as an average value, according to the calculated force value that can be used by the target chip. The embodiment is not limited.
After the first calculation force value of the target chip is determined, the first calculation force value is configured to the target chip so that the target chip can calculate with the calculation force of the first calculation force value.
Optionally, according to each operation result and a corresponding preset result, obtaining a first calculation force value of the target chip includes:
and obtaining the maximum calculation force value of the target chip as the first calculation force value according to each calculation result and the corresponding preset result.
The sweep frequency range is 700-500H/s, the chip starts encryption operation from 700 and compares with the preset answer, if the sweep frequency range is inconsistent with the preset answer, the chip performs encryption operation under 650H/s, and if the sweep frequency range is consistent with the preset answer, the chip can work under 650H/s, and the maximum calculation force value of the chip can be considered to be 650H/s. The subsequent sweep operation can be omitted, and the maximum calculated force value 650H/s of the target chip is used as a first calculated force value and is configured to the target chip.
As another implementation manner, on the basis of the foregoing embodiment, optionally, the method may further include:
step 204, judging whether a static calculation value is stored in EFUSE of the target chip;
and step 205, if yes, configuring the static calculation force value to the target chip so that the target chip performs operation by using the calculation force corresponding to the static calculation force value.
After each power-on and initialization is completed, whether the static calculation force value is stored in the EFUSE of the target chip can be judged, and if the static calculation force value is stored, the static calculation force value can be firstly configured into the target chip, so that the target chip can firstly calculate by the calculation force of the static calculation force value.
For example, in the previous power-on process, sweep frequency operation is performed, and the first calculated force value of the target chip is written into the EFUSE of the target chip, so that the static calculated force value of the target chip can be read from the EFUSE during the power-on operation, and the static calculated force value can be directly configured to the target chip.
Optionally, for each chip, the static calculation force value of the chip can be set according to actual requirements, for example, the computing device is provided with a display screen, the display screen displays the calculation force value of each chip, and the user can input and set the calculation force value of each chip through the interaction interface according to the actual conditions of the user.
Alternatively, the static calculation value may also be written into EFUSE at the time of complete machine production.
By means of the frequency sweeping mode, the computing power of the computing equipment can be maximized, and the cost performance of the computing equipment is improved.
For example, a machine (computing device) with a previous computing force value of 1800H/s is integrated with 6 chips with a theoretical computing force value of 400H/s, and the computing force of the whole machine is fixed at 1800H/s due to the fact that each chip is provided with the smallest workable computing force value of 300H/s. Through the sweep frequency mode, the chip with the calculated force value more than 300H/s can exert the maximum calculated force, if the optimal chip calculated force can reach 400H/s, the total calculated force can reach 1800H+ (0-100 H.6) =1800H/s-2400H/s after the sweep frequency.
As an exemplary implementation manner, as shown in fig. 3, a schematic diagram of a complete machine workflow including frequency sweeping is provided in this embodiment, where the complete machine workflow is as follows:
and 1, powering up the whole machine.
Step 2, initializing CPU, DDR, UART and other basic devices.
And step 3, reading EFUSE, and judging whether a static calculation force value exists. If yes, turning to step 4, and if no, turning to step 5.
And step 4, if the static calculation force value exists, acquiring the static calculation force value and configuring the static calculation force value to the chip.
And 5, if the minimum working force value does not exist, setting the minimum working force value and configuring the minimum working force value to the chip.
And step 6, initializing a currency algorithm and setting a monitoring interface.
And 7, monitoring a sweep frequency command issued by the control host.
And 8, judging whether a frequency sweep command is received. Yes go to step 9, no go to step 12.
After receiving the frequency sweep command, the chip is controlled to carry out frequency sweep operation according to the frequency sweep command, and a first calculation force value of the chip is determined.
And 9, judging the frequency sweep type. The dynamic sweep frequency conversion step 10 is the static sweep frequency conversion step 11.
And 10, configuring a first calculated force value determined by the frequency sweep to a chip, and invalidating the chip after power-down.
And 11, writing the first calculated force value determined by the sweep frequency into the EFUSE and configuring the first calculated force value to the chip.
And step 12, calculating a currency algorithm.
If the frequency sweep command is not received, the currency algorithm is operated according to the configured calculating force of the static calculating force value (when the static calculating force value exists in EFUSE) or the minimum operable calculating force value (when the static calculating force value does not exist in EFUSE), and if the frequency sweep command is received, the currency algorithm is operated according to the calculating force of the first calculating force value determined by the frequency sweep.
According to the calculation force control method provided by the embodiment, the first calculation force value of the target chip is determined through the scanning operation of the chip, and the chip is configured according to the determined first calculation force value of the target chip, so that the actual calculation force of the chip in the computing device can be improved, the calculation force of the computing device is improved, and the flexibility of calculation force configuration of the computing device is improved.
The third embodiment of the present disclosure further provides a device for controlling the calculation force, which is configured to execute the method for controlling the calculation force provided in the first embodiment.
As shown in fig. 4, a schematic structural diagram of the power calculation control device according to the present embodiment is provided. The force calculation control device 30 includes: a control module 31 and a configuration module 32.
The control module 31 is configured to control the target chip to perform a sweep operation according to a sweep command issued by the control host, and determine a first calculation value of the target chip; the configuration module 32 is configured to configure the first calculation value to the target chip.
The specific manner in which the individual modules perform the operations of the apparatus of this embodiment has been described in detail in connection with embodiments of the method and will not be described in detail herein.
According to the computing power control device provided by the embodiment, the first computing power value of the target chip is determined through the scanning operation of the chip, and the chip is configured according to the determined first computing power value of the target chip, so that the actual computing power of the chip in the computing equipment can be improved, the computing power of the computing equipment is improved, and the flexibility of computing power configuration of the computing equipment is improved.
The fourth embodiment of the present disclosure further provides a supplementary explanation of the apparatus provided in the third embodiment, so as to execute the method provided in the second embodiment.
As shown in fig. 5, a schematic structural diagram of the power calculation control device according to the present embodiment is shown.
As an implementation manner, on the basis of the third embodiment, optionally, the apparatus further includes: a listening module 33.
The monitoring module 33 is configured to monitor, through a monitoring interface, whether the control host issues a frequency sweep command, where the frequency sweep command includes a frequency sweep identifier, a frequency sweep type, and a frequency sweep range.
As another implementation manner, on the basis of the third embodiment, optionally, the apparatus further includes: a processing module 34.
Wherein, the processing module 34 is configured to determine a frequency sweep type according to the frequency sweep command; the configuration module 32 is further configured to write the first calculation value into the memory EFUSE of the target chip if the sweep type is a static sweep.
Optionally, if the sweep type is dynamic sweep, the first calculation value is not written into EFUSE of the target chip.
As another implementation manner, on the basis of the third embodiment, optionally, the control module includes: a first control sub-module and a second control sub-module.
The first control submodule is used for controlling the target chip to carry out encryption operation under different frequencies according to the sweep frequency range included in the sweep frequency command to obtain an operation result; and the second control sub-module is used for acquiring a first calculation force value of the target chip according to each calculation result and the corresponding preset result.
Optionally, the second control submodule is specifically configured to:
and obtaining the maximum calculation force value of the target chip as the first calculation force value according to each calculation result and the corresponding preset result.
As another implementation manner, on the basis of the third embodiment, optionally, the apparatus further includes: a judgment module 35.
The judging module is used for judging whether the EFUSE of the target chip stores a static calculation force value or not; and the configuration module is also used for configuring the static calculation force value to the target chip if the static calculation force value is the same, so that the target chip performs calculation work by using the calculation force corresponding to the static calculation force value.
The specific manner in which the individual modules perform the operations of the apparatus of this embodiment has been described in detail in connection with embodiments of the method and will not be described in detail herein.
It should be noted that, in this embodiment, each of the possible embodiments may be implemented separately, or may be implemented in any combination without conflict, and the embodiment of the present application is not limited thereto.
According to the computing power control device provided by the embodiment, the first computing power value of the target chip is determined through the scanning operation of the chip, and the chip is configured according to the determined first computing power value of the target chip, so that the actual computing power of the chip in the computing equipment can be improved, the computing power of the computing equipment is improved, and the flexibility of computing power configuration of the computing equipment is improved.
The embodiment of the disclosure also provides a computing device, which comprises the computing force control device provided by any embodiment.
According to the computing device provided by the embodiment, the first computing force value of the target chip is determined through the scanning operation of the chip, and the chip is configured according to the determined first computing force value of the target chip, so that the actual computing force of the chip in the computing device can be improved, the computing force of the computing device is improved, and the flexibility of computing force configuration of the computing device is improved.
The disclosed embodiments also provide a computer-readable storage medium storing computer-executable instructions configured to perform the method of controlling computing power provided by any of the above embodiments.
According to the computer readable storage medium provided by the embodiment, the first calculation force value of the target chip is determined through the scanning operation of the chip, and the chip is configured according to the determined first calculation force value of the target chip, so that the actual calculation force of the chip in the computing device can be improved, the calculation force of the computing device is improved, and the flexibility of calculation force configuration of the computing device is improved.
The disclosed embodiments also provide a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the method of controlling the computing power provided by any of the embodiments above.
The computer readable storage medium may be a transitory computer readable storage medium or a non-transitory computer readable storage medium.
The embodiment of the disclosure also provides an electronic device, as shown in fig. 6, which is a schematic structural diagram of the electronic device provided in the embodiment. The electronic device 50 includes:
at least one processor (processor) 51, one processor 51 being exemplified in fig. 6; and a memory (memory) 52, which may also include a communication interface (Communication Interface) and a bus. The processor, the communication interface and the memory can complete communication with each other through the bus. The communication interface may be used for information transfer. The processor may call logic instructions in the memory to perform the power control method of the above-described embodiments.
Further, the logic instructions in the memory described above may be implemented in the form of software functional units and stored in a computer-readable storage medium when sold or used as a stand-alone product.
The memory is used as a computer readable storage medium for storing a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor executes the functional applications and data processing by running the software programs, instructions and modules stored in the memory, i.e. the method for controlling the computing power in the above-described method embodiments.
The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the terminal device, etc. Further, the memory may include a high-speed random access memory, and may also include a nonvolatile memory.
Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium including: a plurality of media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or a transitory storage medium.
When used in the present application, although the terms "first," "second," etc. may be used in the present application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without changing the meaning of the description, so long as all occurrences of the "first element" are renamed consistently and all occurrences of the "second element" are renamed consistently. The first element and the second element are both elements, but may not be the same element.
The terminology used in the present application is used for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this disclosure is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in the present disclosure, the terms "comprises," "comprising," and/or variations thereof, mean that the recited features, integers, steps, operations, elements, and/or components are present, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The aspects, implementations, or features of the described embodiments can be used alone or in any combination. Aspects of the described embodiments may be implemented in software, hardware, or a combination of software and hardware. The described embodiments may also be embodied by a computer-readable medium having stored thereon computer-readable code comprising instructions executable by at least one computing device. The computer readable medium may be associated with any data storage device that can store data which can be thereafter read by a computer system. Computer readable media for example may include read-only memory, random-access memory, CD-ROM, HDD, DVD, magnetic tape, optical data storage devices, and the like. The computer readable medium can also be distributed over a network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
The technical description above refers to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration implementations in accordance with the described embodiments. While these embodiments are described in sufficient detail to enable those skilled in the art to practice them, these embodiments are non-limiting; other embodiments may be used, and changes may be made without departing from the scope of the described embodiments. For example, the order of operations described in the flowcharts is non-limiting, and thus the order of two or more operations illustrated in the flowcharts and described in accordance with the flowcharts may be changed in accordance with several embodiments. As another example, in several embodiments, one or more operations illustrated in the flowcharts and described in accordance with the flowcharts are optional or may be deleted. In addition, certain steps or functions may be added to the disclosed embodiments or more than two of the step sequences may be substituted. All such variations are considered to be encompassed by the disclosed embodiments and the claims.
Additionally, terminology is used in the above technical description to provide a thorough understanding of the described embodiments. However, no overly detailed details are required to implement the described embodiments. Accordingly, the foregoing description of the embodiments has been presented for purposes of illustration and description. The embodiments presented in the foregoing description and examples disclosed in accordance with these embodiments are provided separately to add context and aid in the understanding of the described embodiments. The foregoing description is not intended to be exhaustive or to limit the described embodiments to the precise form disclosed. Several modifications, alternative adaptations and variations are possible in light of the above teachings. In some instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the described embodiments.
Claims (9)
1. A method for controlling computing power applied to a computing device, comprising:
according to the sweep frequency range included in the sweep frequency command issued by the control host, the target chip is controlled to carry out encryption operation under different frequencies, and an operation result is obtained; the target chip is disposed on the computing device;
according to each operation result and the corresponding preset result, obtaining the maximum calculation force value of the target chip as a first calculation force value of the target chip;
judging the frequency sweep type according to the frequency sweep command;
if the sweep frequency type is static sweep frequency, writing the first calculated force value into a memory EFUSE of the target chip;
configuring the first calculation value to the target chip;
the method further comprises the steps of:
judging whether a static calculation force value is stored in EFUSE of the target chip;
if yes, the static calculation force value is configured to the target chip, so that the target chip carries out calculation work by using the calculation force corresponding to the static calculation force value.
2. The method of claim 1, wherein prior to controlling the target chip to perform the sweep operation in accordance with the sweep command issued by the control host, determining the first power value of the target chip, the method further comprises:
monitoring whether the control host issues a frequency sweep command through a monitoring interface, wherein the frequency sweep command comprises a frequency sweep identifier, a frequency sweep type and a frequency sweep range.
3. The method of claim 1, wherein if the sweep type is a dynamic sweep, not writing the first calculated force value into EFUSE of the target chip.
4. A computing force control apparatus for use with a computing device, comprising:
the control module is used for controlling the target chip to carry out sweep frequency operation according to the sweep frequency command issued by the control host, and determining a first calculation value of the target chip;
a configuration module for configuring the first calculation force value to the target chip; the target chip is disposed on the computing device;
the control module comprises:
the first control submodule is used for controlling the target chip to carry out encryption operation under different frequencies according to the sweep frequency range included in the sweep frequency command to obtain an operation result;
the second control sub-module is used for acquiring the maximum calculation force value of the target chip as the first calculation force value according to each calculation result and the corresponding preset result;
the processing module is used for judging the frequency sweep type according to the frequency sweep command;
the configuration module is further configured to write the first calculation value into a memory EFUSE of the target chip if the sweep type is a static sweep;
the judging module is used for judging whether the EFUSE of the target chip stores a static calculation force value or not;
the configuration module is further configured to configure the static calculation value to the target chip if it is determined that the EFUSE of the target chip stores the static calculation value, so that the target chip performs operation with the calculation force corresponding to the static calculation value.
5. The apparatus as recited in claim 4, further comprising:
and the monitoring module is used for monitoring whether the control host computer issues a frequency sweep command through the monitoring interface, wherein the frequency sweep command comprises a frequency sweep identifier, a frequency sweep type and a frequency sweep range.
6. The apparatus of claim 4, wherein if the sweep type is a dynamic sweep, the first calculated force value is not written to EFUSE of the target chip.
7. A computing device comprising the apparatus of any one of claims 4-6.
8. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor, which when executed by the at least one processor, cause the at least one processor to perform the method of any of claims 1-3.
9. A computer readable storage medium, characterized in that computer executable instructions are stored, said computer executable instructions being arranged to perform the method of any of claims 1-3.
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2018/119806 WO2020113562A1 (en) | 2018-12-07 | 2018-12-07 | Computing power control method, apparatus and device, and storage medium |
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| CN112084029A (en) * | 2020-09-08 | 2020-12-15 | 周旻 | Distributed computing system and operation method thereof |
| CN116070240B (en) * | 2023-02-03 | 2024-03-08 | 广州万协通信息技术有限公司 | Data encryption processing method and device of multi-chip calling mechanism |
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| WO2020113562A1 (en) | 2020-06-11 |
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