WO2020113562A1

WO2020113562A1 - Computing power control method, apparatus and device, and storage medium

Info

Publication number: WO2020113562A1
Application number: PCT/CN2018/119806
Authority: WO
Inventors: 胡强; 杨鑫; 王虓
Original assignee: 北京比特大陆科技有限公司
Priority date: 2018-12-07
Filing date: 2018-12-07
Publication date: 2020-06-11
Also published as: CN112912743B; CN112912743A

Abstract

Disclosed are a computing power control method, apparatus and device, and a storage medium. The method comprises: controlling, according to a frequency sweeping command issued by a control host, a target chip to perform a frequency sweeping operation so as to determine a first computing power value of the target chip (101); and configuring the first computing power value to the target chip (102). A first computing power value of a target chip is determined by means of a scanning operation of the chip, and the chip is configured by means of the determined first computing power value of the target chip, so that the actual computing power of the chip in a computing device can be improved, thereby improving the computing power of the computing device, and improving the flexibility of computing power configuration of the computing device.

Description

Computing power control method, device, equipment and storage medium

Technical field

The present application relates to the technical field of computing equipment, for example, to a computing power control method, device, equipment, and storage medium.

Background technique

Computing equipment plays an important role in the application of blockchain. With the improvement of the computing power of the entire network, various computing devices with low power consumption and high computing power are emerging one after another. Computing power is also an important indicator that reflects the capabilities and value of computing equipment.

In the existing implementation of computing equipment, after different production processes such as chip tape and patch, the theoretical computing power of the chip will drop by a certain value, and the drop value of different chips is also different, usually set a The acceptable minimum computing power value is regarded as good product. After assembling these good product patches, all chips in the whole machine will be set to the minimum working computing power, so that all chips can work normally.

However, the prior art solution results in a waste of computing power of chips higher than the minimum computing power. Therefore, how to effectively control the computing power of different chips has become an urgent technical problem to be solved.

Summary of the invention

Embodiments of the present disclosure provide a computing power control method, device, device, and storage medium, which are used to control the computing power of a chip in a computing device, so as to solve the problem of wasting computing power of a computing device in the prior art.

A first aspect of an embodiment of the present disclosure provides a method for controlling computing power, including:

According to the frequency sweep command issued by the control host, control the target chip to perform a frequency sweep operation to determine the first computing power value of the target chip;

The first computing power value is configured to the target chip.

A second aspect of an embodiment of the present disclosure provides a computing power control device, including:

The control module is used to control the target chip to perform the frequency scan operation according to the frequency sweep command issued by the control host to determine the first computing power value of the target chip;

The configuration module is configured to configure the first computing power value to the target chip.

A third aspect of the embodiments of the present disclosure provides a computing device including the computing power control device provided in the second aspect above.

A fourth aspect of the embodiments of the present disclosure provides a computer-readable storage medium that stores computer-executable instructions, and the computer-executable instructions are configured to execute the computing power control method provided in the first aspect above.

A fifth aspect of an embodiment of the present disclosure provides a computer program product. The computer program product includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer , The computer is caused to execute the computing power control method provided in the first aspect above.

A sixth aspect of the embodiments of the present disclosure provides an electronic device, including:

At least one processor; and

A memory communicatively connected to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, causes the at least one processor to execute the computing power control method provided in the first aspect above .

BRIEF DESCRIPTION

One or more embodiments are exemplified by the corresponding drawings. These exemplary descriptions and the drawings do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a proportional limitation, and among them:

1 is a schematic flowchart of a method for controlling computing power of a map provided by an embodiment of the present application;

2 is a schematic flowchart of a method for controlling computing power provided by another embodiment of the present application;

FIG. 3 is a schematic diagram of a working process of a whole machine including frequency sweep provided by an embodiment of the present application;

4 is a schematic structural diagram of a computing power control device according to an embodiment of the application;

5 is a schematic structural diagram of a computing power control device according to another embodiment of the present application;

6 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

Through the above drawings, a clear embodiment of the present application has been shown, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the concept of the present disclosure in any way, but to explain the concepts of the present application to those skilled in the art by referring to specific embodiments.

detailed description

In order to understand the features and technical contents of the embodiments of the present disclosure in more detail, the following describes the implementation of the embodiments of the present disclosure in detail with reference to the drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure. In the following technical description, for convenience of explanation, various details are provided to provide a sufficient understanding of the disclosed embodiments. However, without these details, one or more embodiments can still be implemented. In other cases, to simplify the drawings, well-known structures and devices can be simplified.

First explain the terms involved in this application:

EFUSE: is a one-time programmable memory in the chip.

In addition, the terms "first", "second", etc. are for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. In the description of the following embodiments, "multiple" means more than two, unless otherwise specifically limited.

The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 of the present disclosure provides a computing power control method for controlling the computing power of a chip. The execution subject of the computing power control method is a computing power control device, and the computing power control device may be provided in a computing device. As shown in FIG. 1, it is a schematic flowchart of a method for controlling computing power provided by this embodiment. The method includes:

Step 101: According to a frequency sweep command issued by the control host, control the target chip to perform frequency sweep operation to determine the first computing power value of the target chip.

Step 102: Configure the first computing power value to the target chip.

Specifically, in the whole working process of the computing device or the function verification process of the whole device, it is necessary to initialize first, such as initializing basic devices such as CPU, DDR, UART, etc. After initialization, you can choose from the EFUSE of each chip on the computing device Read the information to determine whether there is a static computing power value stored. If no static computing power value is stored, configure the chip with the minimum operable computing power value, first make the chip operate with the minimum operable computing power, and initialize the computing algorithm, The arithmetic algorithm may be a currency algorithm, and initializing the currency algorithm refers to determining the corresponding currency algorithm according to different currencies. And set the monitoring interface to monitor the commands sent by the control host. The commands issued by the control host can include frequency sweep commands and calculation task commands. The calculation task commands refer to the tasks that need to be decrypted by the control host. The answer is returned to the control panel. Among them, multiple chips are provided on the computing power board.

When it is detected that the command issued by the control host is a frequency sweep command, according to the frequency sweep command issued by the control host, the target chip is controlled to perform a frequency sweep operation to determine the first computing power value of the target chip. The frequency sweep command may be a command word conforming to a certain protocol, and the frequency sweep command may include information such as frequency sweep identifier, frequency sweep type, frequency sweep range, and so on. For example, the sweep flag bit 3 in the command indicates the sweep command; the sweep type includes static and dynamic, such as 0 for static and 1 for dynamic; the sweep range is 700-500H/S (which is the calculation value). The force value refers to how many times the chip can calculate the hash value in 1 second. The computing power configuration of the chip can be controlled by controlling the operating frequency of the chip or configured in other ways, for example, the operating frequency of the chip has a corresponding relationship with its computing power. Configure the chip's computing power by setting the chip's operating frequency. Specifically, after determining the computing power value of the chip, how to configure the chip to calculate the computing power value as the prior art is not limited in this embodiment.

Optionally, the frequency sweep command issued by the control host may be sent once every time the computing device is powered on, or may be sent once when the chip fails to work, to re-determine the computing power value of the chip.

Frequency sweep operation refers to that the chip performs encryption operations at different frequencies according to the frequency sweep range included in the frequency sweep command, and compares it with the preset answer to determine the maximum computing power value of the chip from the frequency sweep range, or determine The computing power value of the chip can work and so on.

Exemplarily, the frequency sweep range is 700-500H/s. The chip starts the encryption operation from 700 and compares it with the preset answer. If it is inconsistent, the encryption operation is performed at 650H/s again, compared with the preset answer. If it is consistent with the preset answer, it proves that the chip can work under 650H/s, and it can be considered that the maximum computing power value of the chip is 650H/s. By analogy, try from 700 to the next until you find the computing power value of the chip as the maximum computing power value of the chip. The number of encryption operations to be tried within the frequency sweep range can be set according to actual needs, for example, according to a certain equidistance sequence, 700-650-600-550-500, or it can be determined according to other rules. This embodiment does not Be limited.

Optionally, the frequency sweep range can also be scanned, and one of the computing power values of the target chip can be selected as the first computing power value of the target chip, or according to a certain calculation, such as an average value, according to the target chip energy The working computing power value determines the first computing power value of the target chip. The specific mode is not limited in this embodiment.

After the first computing power value of the target chip is determined, the first computing power value is allocated to the target chip, so that the target chip can perform calculation with the computing power of the first computing power value. The method of configuring the first computing power value to the target chip, the validity of the first computing power value is only in the work process after this power-on until the next frequency sweep command is issued before the target chip is reconfigured the computing power value Effective, the chip will be invalid after power off. The next time you power on, you also need to configure the minimum working hashrate or re-scan the frequency to determine the hashrate of the target chip (which can be called the second hashrate).

Alternatively, there may be one or more target chips. Multiple refers to two or more.

The computing power control method provided by the embodiment of the present disclosure determines the first computing power value of the target chip through the scanning operation of the chip, and configures the chip to determine the first computing power value of the target chip, which can improve the chip's computing power The actual computing power in the device, thereby increasing the computing power of the computing device, and increasing the flexibility of computing power configuration of the computing device.

Embodiment 2 of the present disclosure further supplements the method for controlling the computing power provided by the foregoing embodiment.

As shown in FIG. 2, it is a schematic flowchart of a method for controlling computing power provided by this embodiment.

As an implementable manner, on the basis of the foregoing embodiment, optionally, based on the frequency sweep command issued by the control host, the target chip is controlled to perform a frequency sweep operation to determine the first computing power value of the target chip Previously, the method also included:

Step 201: Monitor whether the control host issues a frequency sweep command through a monitoring interface. The frequency sweep command includes a frequency sweep identifier, a frequency sweep type, and a frequency sweep range.

Specifically, the frequency sweep command issued by the control host may be sent once every time the computing device is powered on, or it may be sent once after a chip fails to work, to re-determine the computing power value of the chip. The monitoring interface can be set to monitor the commands sent by the control host. The commands issued by the control host can include frequency sweep commands and calculation task commands. The calculation task commands refer to the tasks issued by the control host that need to be decrypted. The answer is returned to the control panel. Among them, multiple chips are provided on the computing power board.

When it is detected that the command issued by the control host is a frequency sweep command, according to the frequency sweep command issued by the control host, the target chip is controlled to perform a frequency sweep operation to determine the first computing power value of the target chip. The frequency sweep command may be a command word conforming to a certain protocol, and the frequency sweep command may include information such as frequency sweep identifier, frequency sweep type, frequency sweep range, and so on. For example, the sweep flag bit 3 in the command indicates the sweep command; the sweep type includes static and dynamic, such as 0 for static and 1 for dynamic; the sweep frequency range is 700-500H/S (which is the computing power value). The force value refers to how many times the chip can calculate the hash value in 1 second.

As another implementable manner, on the basis of the foregoing embodiment, optionally, based on the frequency sweep command issued by the control host, the target chip is controlled to perform a frequency sweep operation to determine the first computing power of the target chip After the value, the method also includes:

Step 2021: Determine the frequency sweep type according to the frequency sweep command.

Step 2022, if the frequency sweep type is static frequency sweep, the first computing power value is written into the memory EFUSE of the target chip.

Specifically, the frequency sweep command may include information such as frequency sweep identifier, frequency sweep type, frequency sweep range, and so on. For example, the sweep flag bit 3 in the command indicates the sweep command; the sweep types include static and dynamic, such as 0 for static and 1 for dynamic; the sweep range is 700-500H/S. After listening to the frequency sweep command, you can determine the frequency sweep type according to the frequency sweep command. If the frequency sweep type is static frequency sweep, you can also write the first calculation value into the target chip's EFUSE, which is the static state of the target chip. The computing power value is stored in EFUSE. After the next power-on, the static computing power value can be read from EFUSE to configure the target chip so that the chip operates according to the computing power of the static computing power value.

Optionally, if the determined first computing power value is the maximum computing power value of the target chip, writing the first computing power value into EFUSE can implement the target chip to perform subsequent operations according to the maximum computing power, thereby improving the computing device’s Computing power.

Optionally, if the frequency sweep type is dynamic frequency sweep, there is no need to write the first computing power value into the EFUSE of the target chip, and the first computing power value is invalid after the chip is powered off. The next time the power is turned on, the frequency sweep operation can be performed again to re-determine the calculation value of the target chip and configure the target chip.

As another implementable manner, on the basis of the foregoing embodiment, optionally, according to a frequency sweep command issued by the control host, the target chip is controlled to perform a frequency sweep operation to determine the first computing power value of the target chip , Which can include:

Step 2031: Control the target chip to perform encryption operations at different frequencies according to the frequency sweep range included in the frequency sweep command to obtain an operation result.

Step 2032: Acquire the first computing power value of the target chip according to each calculation result and the corresponding preset result.

Specifically, after receiving the frequency sweep command issued by the control host, the target chip may be controlled to perform encryption operations at different frequencies according to the frequency sweep range included in the frequency sweep command to obtain the operation result, and according to each The calculation result and the corresponding preset result obtain the first computing power value of the target chip.

Exemplarily, the frequency sweep range is 700-500H/s. The chip starts the encryption operation from 700 and compares it with the preset answer. If it is inconsistent, the encryption operation is performed at 650H/s again, compared with the preset answer. If it is consistent with the preset answer, it proves that the chip can work under 650H/s, and the maximum computing power value of the chip can be regarded as 650H/s. By analogy, try from 700 to the next until you find the computing power value of the chip as the maximum computing power value of the chip. The number of encryption operations to be tried within the frequency sweep range can be set according to actual needs, for example, according to a certain equidistance sequence, 700-650-600-550-500, or it can be determined according to other rules. This embodiment does not Be limited.

After the first computing power value of the target chip is determined, the first computing power value is allocated to the target chip, so that the target chip can perform calculation with the computing power of the first computing power value.

Optionally, obtaining the first computing power value of the target chip according to each of the calculation results and the corresponding preset results includes:

According to each of the calculation results and the corresponding preset results, the maximum computing power value of the target chip is obtained as the first computing power value.

Exemplarily, the frequency sweep range is 700-500H/s. The chip starts the encryption operation from 700 and compares it with the preset answer. If it is inconsistent, the encryption operation is then performed at 650H/s and compared with the preset answer. If it is consistent with the preset answer, it proves that the chip can work under 650H/s, and it can be considered that the maximum computing power value of the chip is 650H/s. It is no longer necessary to perform the subsequent frequency sweep operation, and the maximum computing power value of the target chip is 650H/s as the first computing power value, and it is configured to the target chip.

As another implementable manner, based on the foregoing embodiment, optionally, the method may further include:

Step 204: Determine whether a static computing power value is stored in the EFUSE of the target chip;

In step 205, if yes, the static computing power value is allocated to the target chip, so that the target chip performs computing work with the computing power corresponding to the static computing power value.

After each power-on and initialization, you can determine whether the static hashrate value is stored in the EFUSE of the target chip. If the static hashrate value is stored, you can first configure the static hashrate value in the target chip to make the target chip Calculate first with the computing power of the static computing power value.

For example, during the previous power-on operation, a frequency sweep operation was performed, and the first computing power value of the target chip was written into the target chip's EFUSE. Then, during this power-up operation, it can be read from EFUSE After obtaining the static computing power value of the target chip, the static computing power value can be directly configured to the target chip.

Optionally, for each chip, the static computing power value can also be set according to actual needs. For example, the computing device has a display screen, and the display screen shows the computing power value of each chip. The user can interact according to his actual situation. The interface input sets the computing power value of each chip.

Optionally, the static computing power value can also be written into EFUSE when the whole machine is produced.

Through frequency sweeping, the computing power of the computing device can be maximized, and the cost performance of the computing device can be improved.

Exemplarily, a machine (computing device) with a previous computing power value of 1800H/s is integrated with 6 theoretical computing power values of 400H/s chips, because each chip is set with a minimum working computing power value of 300H /s, resulting in the fixed computing power of 1800H/s. Through the frequency sweeping method, among the 6 chips, a chip with a computing power value of more than 300H/s will exert its maximum computing power. If the optimal chip computing power can reach 400H/s, then the overall computing power after the frequency sweep It can reach 1800H+(0～100H*6)=1800H/s～2400H/s.

As an implementable manner, for example, as shown in FIG. 3, it is a schematic diagram of a whole machine workflow including frequency sweep provided by this embodiment. The whole machine workflow is as follows:

Step 1. Power on the whole machine.

Step 2. Initialize basic devices such as CPU, DDR, and UART.

Step 3. Read EFUSE to determine whether there is a static computing power value. If there is a step 4, go to step 5.

Step 4. If it exists, obtain the static computing power value and configure it to the chip.

Step 5. If it does not exist, set the minimum working computing power value and configure it to the chip.

Step 6. Initialize the currency algorithm and set the listening interface.

Step 7. Monitor the frequency sweep command issued by the control host.

Step 8. Determine whether the frequency sweep command is received. If yes, go to step 9. If no, go to step 12.

After receiving the frequency sweep command, the chip needs to be controlled to perform a frequency sweep operation according to the frequency sweep command to determine the first computing power value of the chip.

Step 9. Determine the type of frequency sweep. It is step 10 for dynamic frequency conversion and step 11 for static frequency conversion.

Step 10: Configure the first computing power value determined by the frequency sweep to the chip, and it will be invalid after power off.

Step 11. Write the first computing power value determined by the frequency sweep to EFUSE and configure it to the chip.

Step 12. Calculate the currency algorithm.

If no frequency sweep command is received, the calculation power according to the configured static calculation value (when there is a static calculation value in EFUSE) or the minimum working calculation value (when there is no static calculation value in EFUSE) The arithmetic currency algorithm, if a frequency sweep command is received, calculates the monetary algorithm according to the hashrate of the first hashrate value determined by the frequency sweep.

The method for controlling the computing power provided by this embodiment determines the first computing power value of the target chip through the scanning operation of the chip, and configures the chip to determine the first computing power value of the target chip, which can improve the chip in the computing device Actual computing power in order to increase the computing power of the computing device and increase the flexibility of computing power configuration of the computing device.

Embodiment 3 of the present disclosure also provides a computing power control device, which is used to execute the computing power control method provided in Embodiment 1 above.

As shown in FIG. 4, it is a schematic structural diagram of a computing power control device provided in this embodiment. The computing power control device 30 includes a control module 31 and a configuration module 32.

The control module 31 is used to control the target chip to perform a frequency scan operation according to the frequency sweep command issued by the control host to determine the first computing power value of the target chip; the configuration module 32 is used to convert the first computing power value Configure to the target chip.

Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

According to the computing power control device provided in this embodiment, the first computing power value of the target chip is determined through the scanning operation of the chip, and the chip is configured to determine the first computing power value of the target chip, which can improve the chip in computing The actual computing power in the device, thereby increasing the computing power of the computing device, and increasing the flexibility of computing power configuration of the computing device.

Embodiment 4 of the present disclosure further supplements the apparatus provided in Embodiment 3 to perform the method provided in Embodiment 2 above.

As shown in FIG. 5, it is a schematic structural diagram of a computing power control device provided in this embodiment.

As an implementable manner, on the basis of the foregoing third embodiment, optionally, the device further includes: a listening module 33.

Wherein, the monitoring module 33 is used to monitor whether the control host issues a frequency sweep command through the monitoring interface, and the frequency sweep command includes a frequency sweep identifier, a frequency sweep type and a frequency sweep range.

As another implementable manner, on the basis of the foregoing third embodiment, optionally, the device further includes: a processing module 34.

Wherein, the processing module 34 is used to determine the frequency sweep type according to the frequency sweep command; the configuration module 32 is also used to write the first computing power value to the target chip if the frequency sweep type is a static frequency sweep Memory EFUSE.

Optionally, if the frequency sweep type is dynamic frequency sweep, the first computing power value is not written into the EFUSE of the target chip.

As another implementable manner, on the basis of the foregoing third embodiment, optionally, the control module includes: a first control submodule and a second control submodule.

Among them, the first control sub-module is used to control the target chip to perform encryption operation at different frequencies according to the frequency sweep range included in the frequency sweep command to obtain the operation result; the second control sub-module is used to The calculation result and the corresponding preset result obtain the first computing power value of the target chip.

Optionally, the second control sub-module is specifically used for:

As another implementable manner, on the basis of the foregoing third embodiment, optionally, the device further includes: a judgment module 35.

Wherein, the judgment module is used to judge whether a static computing power value is stored in the EFUSE of the target chip; the configuration module is also used to configure the static computing power value to the target chip if yes, so that The target chip performs calculation work with the calculation power corresponding to the static calculation power value.

It should be noted that each implementable manner in this embodiment may be implemented separately, or may be combined and implemented in any combination without conflict, and the embodiments of this application are not limited.

An embodiment of the present disclosure also provides a computing device, including the computing power control device provided by any of the foregoing embodiments.

According to the computing device provided in this embodiment, the first computing power value of the target chip is determined through the scanning operation of the chip, and the chip is configured to determine the first computing power value of the target chip, which can improve the chip's computing power in the computing device Actual computing power, thereby increasing the computing power of the computing device, and increasing the flexibility of computing power configuration of the computing device.

An embodiment of the present disclosure also provides a computer-readable storage medium that stores computer-executable instructions, and the computer-executable instructions are configured to execute the computing power control method provided by any of the foregoing embodiments.

According to the computer-readable storage medium provided in this embodiment, the first computing power value of the target chip is determined through the scanning operation of the chip, and the chip is configured to determine the first computing power value of the target chip, which can improve the chip's computing power. The actual computing power in the device, thereby increasing the computing power of the computing device, and increasing the flexibility of computing power configuration of the computing device.

An embodiment of the present disclosure also provides a computer program product. The computer program product includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the The computer executes the computing power control method provided by any of the above embodiments.

The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

An embodiment of the present disclosure also provides an electronic device. As shown in FIG. 6, it is a schematic structural diagram of the electronic device provided by this embodiment. The electronic device 50 includes:

At least one processor (processor) 51, one processor 51 is taken as an example in FIG. 6; and the memory (memory) 52 may further include a communication interface (Interface) and a bus. Among them, the processor, communication interface, and memory can complete communication with each other through the bus. The communication interface can be used for information transmission. The processor may call logical instructions in the memory to execute the control method of the computing power in the above embodiment.

In addition, the logic instructions in the aforementioned memory can be implemented in the form of software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium.

The memory as a computer-readable storage medium can be used to store software programs and computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor executes functional applications and data processing by running software programs, instructions, and modules stored in the memory, that is, implementing the computing power control method in the foregoing method embodiments.

The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system and application programs required by at least one function; the storage data area may store data created according to the use of a terminal device, and the like. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory.

The technical solutions of the embodiments of the present disclosure may be embodied in the form of software products, which are stored in a storage medium and include one or more instructions to make a computer device (which may be a personal computer, server, or network) Equipment, etc.) to perform all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, including: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc. A medium that can store program codes may also be a transient storage medium.

When used in this application, although the terms "first", "second", etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without changing the meaning of the description, the first element can be called the second element, and likewise, the second element can be called the first element, as long as all occurrences of the "first element" are consistently renamed and all occurrences of The "second component" can be renamed consistently. The first element and the second element are both elements, but they may not be the same element.

The terms used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "said" are intended to include plural forms as well . Similarly, the term "and/or" as used in this application is meant to include any and all possible combinations of one or more associated lists. In addition, when used in this application, the term "comprise" and its variations "comprises" and/or includes etc. refer to the stated features, wholes, steps, operations, elements, and/or The presence of components does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and/or groups of these.

The various aspects, implementations, implementations or features in the described embodiments can be used alone or in any combination. Various aspects in the described embodiments may be implemented by software, hardware, or a combination of software and hardware. The described embodiments may also be embodied by a computer-readable medium that stores computer-readable code including instructions executable by at least one computing device. The computer-readable medium can be associated with any data storage device capable of storing data, which can be read by a computer system. Computer-readable media used for examples may include read-only memory, random access memory, CD-ROM, HDD, DVD, magnetic tape, optical data storage devices, and the like. The computer-readable medium may also be distributed in computer systems connected through a network, so that computer-readable codes can be stored and executed in a distributed manner.

The above technical description may refer to the accompanying drawings, which form a part of the present application, and the description shows an implementation according to the described embodiments in the drawings. Although these embodiments are described in sufficient detail to enable those skilled in the art to implement these embodiments, these embodiments are non-limiting; so that other embodiments can be used without departing from the scope of the described embodiments Changes can also be made under circumstances. For example, the sequence of operations described in the flowchart is non-limiting, so the sequence of two or more operations explained in the flowchart and described according to the flowchart may be changed according to several embodiments. As another example, in several embodiments, one or more operations illustrated in the flowchart and described in accordance with the flowchart are optional or may be deleted. In addition, certain steps or functions may be added to the disclosed embodiments, or two or more steps may be replaced in sequence. All these changes are considered to be included in the disclosed embodiments and claims.

In addition, terminology is used in the above technical description to provide a thorough understanding of the described embodiments. However, no excessively detailed details are required to implement the described embodiments. Therefore, the above description of the embodiments is presented for explanation and description. The embodiments presented in the above description and the examples disclosed according to these embodiments are provided separately to add context and help to understand the described embodiments. The above description is not intended to be without omission or to limit the described embodiments to the precise form of this disclosure. Based on the above teachings, several modifications, choices and changes are possible. In some cases, well-known processing steps are not described in detail to avoid unnecessarily affecting the described embodiments.

Claims

A computing power control method, which is characterized by including:

According to the frequency sweep command issued by the control host, control the target chip to perform a frequency sweep operation to determine the first computing power value of the target chip;

The first computing power value is configured to the target chip.
The method according to claim 1, wherein before controlling the target chip to perform a frequency scan operation according to a frequency sweep command issued by a control host, the method further comprises: :

Through the monitoring interface, monitor whether the control host issues a frequency sweep command. The frequency sweep command includes a frequency sweep identifier, a frequency sweep type, and a frequency sweep range.
The method according to claim 1, characterized in that after controlling the target chip to perform a frequency scan operation according to the frequency sweep command issued by the control host, and determining the first computing power value of the target chip, the method further comprises :

Determine the type of frequency sweep according to the frequency sweep command;

If the frequency sweep type is static frequency sweep, the first computing power value is written into the memory EFUSE of the target chip.
The method according to claim 3, wherein if the frequency sweep type is dynamic frequency sweep, the first computing power value is not written into the EFUSE of the target chip.
The method according to claim 1, characterized in that, according to a frequency sweep command issued by the control host, controlling the target chip to perform a frequency sweep operation to determine the first computing power value of the target chip includes:

According to the frequency sweep range included in the frequency sweep command, controlling the target chip to perform encryption operations at different frequencies to obtain operation results;

Obtain the first computing power value of the target chip according to each calculation result and the corresponding preset result.
The method according to claim 5, wherein obtaining the first computing power value of the target chip based on each of the calculation results and the corresponding preset results includes:

According to each of the calculation results and the corresponding preset results, the maximum computing power value of the target chip is obtained as the first computing power value.
The method according to any one of claims 1-6, wherein the method further comprises:

Determine whether a static computing power value is stored in the EFUSE of the target chip;

If yes, the static computing power value is allocated to the target chip, so that the target chip performs computing work with the computing power corresponding to the static computing power value.
A computing power control device, characterized in that it includes:

The control module is used to control the target chip to perform the frequency scan operation according to the frequency sweep command issued by the control host to determine the first computing power value of the target chip;

The configuration module is configured to configure the first computing power value to the target chip.
The device according to claim 8, further comprising:

The monitoring module is configured to monitor whether the control host issues a frequency sweep command through a monitoring interface, and the frequency sweep command includes a frequency sweep identifier, a frequency sweep type and a frequency sweep range.
The device according to claim 8, wherein the device further comprises:

A processing module, used to determine the type of frequency sweep according to the frequency sweep command;

The configuration module is further configured to write the first computing power value into the memory EFUSE of the target chip if the frequency sweep type is static frequency sweep.
The apparatus according to claim 10, wherein if the frequency sweep type is dynamic frequency sweep, the first computing power value is not written into the EFUSE of the target chip.
The device according to claim 8, wherein the control module comprises:

A first control submodule, configured to control the target chip to perform encryption operations at different frequencies according to the frequency sweep range included in the frequency sweep command to obtain an operation result;

The second control submodule is configured to obtain the first computing power value of the target chip according to each of the calculation results and the corresponding preset results.
The device according to claim 12, wherein the second control submodule is specifically used for:

According to each of the calculation results and the corresponding preset results, the maximum computing power value of the target chip is obtained as the first computing power value.
The device according to any one of claims 8 to 13, wherein the device further comprises:

The judgment module is used to judge whether a static computing power value is stored in the EFUSE of the target chip;

The configuration module is further configured to, if it is, configure the static computing power value to the target chip, so that the target chip performs computing work with the computing power corresponding to the static computing power value.
A computing device, characterized by comprising the device according to any one of claims 8-14.
An electronic device, characterized in that it includes:

At least one processor; and

A memory communicatively connected to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, causes the at least one processor to perform the method of any one of claims 1-7 .
A computer-readable storage medium, characterized in that computer-executable instructions are stored, and the computer-executable instructions are configured to perform the method of any one of claims 1-7.
A computer program product, characterized in that the computer program product includes a computer program stored on a computer-readable storage medium, the computer program includes program instructions, and when the program instructions are executed by a computer, the computer Performing the method of any one of claims 1-7.