CN105513648B - The adaptive method and device for generating the configuration of chip optimum performance - Google Patents
The adaptive method and device for generating the configuration of chip optimum performance Download PDFInfo
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- CN105513648B CN105513648B CN201610014821.XA CN201610014821A CN105513648B CN 105513648 B CN105513648 B CN 105513648B CN 201610014821 A CN201610014821 A CN 201610014821A CN 105513648 B CN105513648 B CN 105513648B
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
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- G—PHYSICS
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- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56016—Apparatus features
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Abstract
The present invention provides a kind of adaptive method and apparatus for generating the configuration of chip optimum performance, after circuit starting up, sets the corresponding frequency configuration of test target frequency automatically；After the clock stable to be output to chip storage unit, proceed by the EMA scanned with EMA and train flow；After the completion of EMA trains flow, internal EEPROM can have been stored to be configured when EMA Configuration Values best under the frequency are worked normally for chip and used.The present invention makes equipment that can train the optimum performance for searching chip automatically once being switched on, not only training algorithm is optional for it, it according to the SRAM test results adjust automatically EMA Configuration Values of each chip and can also be recorded, different EMA can be carried out according to the different SRAM performances of each chip to be configured, the SRAM performances of each chip are maximized simultaneously on the basis of by training, have apparent advantage compared to current technology.
Description
Technical field
The present invention relates to a kind of design of chip, more particularly to a kind of adaptive method for generating the configuration of chip optimum performance
And device.
Background technology
SRAM memory cell in chip is the circuit very sensitive to manufacturing process, due in chip manufacturing proces, often
The chip of different location may have different performances due to the deviation of manufacturing process in one batch and each wafer.It is and current
Measuring technology be all to technique worst in the deviation of all manufacturing process as test setting, it is as much as possible to ensure
Chip can work normally and then SRAM usually and be the bottleneck of limiting frequency, so the running frequency of SRAM is excessively pessimistic, often
Often limit the performance of chip entirety.And although the overclocking behavior of individual subscriber can promote chip performance, overclocking range
It has no basis, it is easy to which set of frequency is excessively high and damages chip, so technology has no idea to find each chip respectively most at present
A test method and configuration method for good performance.
In the design of recent SRAM, a kind of configuration of EMA (Extra Margin Adjustment) port is increased, this
There are 3 bit in port, the performance of SRAM and the balance of error probability can be adjusted from design and current design method is usual
It is that the configuration of a centre is obtained according to the historical manufacturing data of wafer fabrication, then EMA ports is connected in circuit and are changed
Data in the hope of yield and the balance of performance, have the disadvantages that：
1st, current design method is typically to obtain the configuration of a centre according to the historical manufacturing data of wafer fabrication,
The otherness between chip is had ignored, makes the chip that acquisition higher performance can be configured by EMA originally that can only obtain relatively low
Performance, while part can be configured by EMA and reduce performance and by the chip of test be judged as waste paper；
2nd, cannot SRAM adjusting performances be carried out to different chips automatically.
Invention content
The technical problem to be solved in the present invention, be to provide a kind of adaptive method for generating the configuration of chip optimum performance and
Device can train the optimum performance for searching chip automatically once being switched on.
What the adaptive method for generating the configuration of chip optimum performance of the present invention was realized in：A kind of adaptive generation core
The method of piece optimum performance configuration, after circuit starting up, sets the corresponding frequency configuration of test target frequency automatically；Deng
After clock stable to be output to chip storage unit, proceed by the EMA scanned with EMA and train flow；Flow is trained in EMA
After the completion, internal EEPROM can have been stored to be configured when EMA Configuration Values best under the frequency are worked normally for chip and used.
Further, EMA training flow include the write operation sweep test carried out successively, read operation sweep test and
Read and write mixed sweep test；
The write operation sweep test is specially：
11) EMA is configured to 111, EMAW is configured to 11, EMAS is configured to 1, behaviour is write into the detection of bist algorithms selections
The algorithm of work；
12) excitation that action is write in special detection is carried out to memory to be measured to pour into, export the response results of memory to be measured；
13) response results of memory to be measured and expected result are compared, then by memory to be measured whether special
The response obtained under the excitation of action is write in detection and expection is consistent, and the result for detecting and passing through is exported if comparison is consistent, no
Then export the result of test errors and write operation mistake；
If 14) test errors, the previous relevant configuration of writing shown has been highest configuration, then EMAW values is added 1
It is used when being worked normally in write-in EEPROM as the best EMAW values of this chip for chip, then starts to go to read operation scanning
Test；
If test passes through, EMAW has been configured into 0 still through then EMAW values 0 are written in EEPROM as this core
The best EMAW values of piece, are then transferred to read operation sweep test；Otherwise EMAW values are reduced by 1, returns to step 12)；
The read operation sweep test is specially：
21) bist algorithms are changed to the algorithm of selection detection reading action, EMAW values no longer change, and EMAS first is configured to 0
Carry out a wheel test；
22) excitation that special detection reading action is carried out to memory to be measured pours into, and exports the response results of memory to be measured；
23) response results of memory to be measured and expected result are compared, then by memory to be measured whether special
The response obtained under the excitation of item detection reading action is consistent with expection, and the result for detecting and passing through is exported if consistent, otherwise defeated
Go out the result of test errors and read operation mistake；
If 24) test errors, the previous reading relevant configuration shown has been highest configuration, then writes EMAS values 1
Enter in EEPROM as the best EMAS values of this chip, EMAS values 0 are written in EEPROM if if test and are used as this core
The best EMAS values of piece；Then start to read and write mixed sweep test；
The read-write mixed sweep, which is tested, is specially：
31) bist algorithms are changed to the algorithm of selection detection read-write mixing action, EMAW and EMAS values no longer change, will
EMA configurations subtract 1 and start to test；
32) excitation that read-write motion is detected to memory to be measured pours into, and then exports the response knot of memory to be measured
Fruit；
33) response results of memory to be measured and expected result are compared, then whether is examining memory to be measured
It is consistent with expection to survey the response obtained under the excitation of read-write motion, the result that detection passes through is exported if consistent, is otherwise exported
The result of test errors；
It is 34) if that test passes through as a result, then subtracting 1 by EMA values and return to step 32) continues test next time,
Until test errors or EMA is had reached as 0；
If the result of test errors, the previous reading relevant configuration shown has been highest configuration, then will test
The EMA values of mistake add in 1 write-in EEPROM as the best EMA values of this chip；Or EMA has been configured into 0 still through then
EMA values 0 are written in EEPROM as the best EMA values of this chip；The test of this EMA best configuration is terminated.
Wherein, in the step 14) if first time write operation test with regard to test errors, show chip under lowest term
Mem all can not work normally, be directly labeled as unqualified defective chips in EEPROM, and the EMA of first time is configured
Value is write in the EMA best configurations of EEPROM.
What the adaptive device for generating the configuration of chip optimum performance of the present invention was realized in：A kind of adaptive generation core
The method of piece optimum performance configuration, it is characterised in that：It is generated including EMA Training Controls unit, frequency configuration unit, clock single
Member, algorithms selection unit, BIST algorithms storage unit, BIST controller, defect diagonsis unit, EMA configuration scanning element,
EEPROM and path selection unit；
The EMA Training Controls unit pass sequentially through the frequency configuration unit, the clock generating unit connection it is to be measured
Memory；The EMA Training Controls unit also passes sequentially through the algorithms selection unit, BIST controller connects storage to be measured
Device；And the algorithms selection unit is also connected with the BIST algorithms storage unit；The BIST controller also passes through the defect
Diagnosis unit connects the EMA Training Controls unit and EMA configuration scanning elements；The EMA Training Controls unit is also logical
It crosses the EMA configurations scanning element and connects the path selection unit；The EMA configurations scanning element is also connected by EEPROM
The path selection unit；The path selection unit is also connected with memory to be measured；
After circuit starting up, the frequency configuration unit is set test target by the EMA Training Controls unit
The corresponding frequency configuration of frequency；Then after the output clock stable for waiting for the clock generating unit, the EMA Training Controls list
Member controls the algorithms selection unit and EMA configurations scanning element to proceed by the EMA scanned with EMA and train flow；
After the completion of EMA training flows, when internal EEPROM can store EMA Configuration Values best under the frequency for chip normal work
Configuration uses.
Wherein, the EMA training flow includes the write operation sweep test, read operation sweep test and the read-write that carry out successively
Mixed sweep is tested；
The write operation sweep test is specially：
11) EMA is configured to 111 by the EMA configurations scanning element, and EMAW is configured to 11, EMAS is configured to 1, institute
Algorithms selection unit is stated by the algorithm of bist algorithms selections detection write operation；
12) excitation that the BIST controller writes action to the special detection of memory to be measured progress pours into, and output is to be measured to deposit
The response results of reservoir are to the defect diagonsis unit；
13) the defect diagonsis unit compares the response results of memory to be measured and expected result, then will treat
It is consistent with expection to survey the response whether memory obtains under the special excitation for detecting and writing action, inspection is exported if comparison is consistent
It surveys the result that passes through and scanning element is configured to the EMA, otherwise export the result of test errors and write operation mistake to described
Scanning element is configured in EMA；
If 14) result that the EMA configurations scanning element is connected to is test errors, the previous correlation of writing shown is matched
It has been highest configuration to put, then adds in 1 write-in EEPROM EMAW values and supply the normal work of chip as the best EMAW values of this chip
Then use when making starts to go to read operation sweep test；
If the result that EMA configuration scanning element is connected to passes through for test, EMAW be configured into 0 still through,
Then EMAW values 0 are written in EEPROM as the best EMAW values of this chip, are then transferred to read operation sweep test；Otherwise will
EMAW values reduce by 1, return to step 12)；
The read operation sweep test is specially：
21) bist algorithms are changed to the algorithm of selection detection reading action by the algorithms selection unit, and EMAW values no longer change,
EMAS is first configured to 0 carry out one and takes turns test；
22) to memory to be measured progress, the excitation of special detection reading action pours into the BIST controller, and output is to be measured to deposit
The response results of reservoir are to the defect diagonsis unit；
23) the defect diagonsis unit compares the response results of memory to be measured and expected result, then will treat
It is consistent with expection to survey the response whether memory obtains under the excitation of special detection reading action, it is logical that detection is exported if consistent
Scanning element is configured to the EMA in the result crossed, and otherwise exports test errors and the result of read operation mistake is matched to the EMA
Put scanning element；
24) scanning element is configured after the testing and diagnosing result of defect diagonsis unit is connected in the EMA, if testing and diagnosing
As a result it is test errors, the previous reading relevant configuration shown has been highest configuration, then EMAS values 1 is written in EEPROM
Best EMAS values as this chip；
It is to test that EMAS values 0 are written in EEPROM to the best EMAS for being used as this chip if if testing and diagnosing result
Value；Then start to read and write mixed sweep test；
The read-write mixed sweep, which is tested, is specially：
31) the algorithms selection unit by bist algorithms be changed to selection detection read-write mixing action algorithm, EMAW and
EMAS values no longer change, and subtracting 1 by EMA configurations starts to test；
32) BIST controller is detected memory to be measured the excitation of read-write motion and pours into, and then exports to be measured
The response results of memory are to the defect diagonsis unit；
33) the defect diagonsis unit compares the response results of memory to be measured and expected result, then will treat
Surveying memory, whether the response obtained under the excitation of detection read-write motion is consistent with expection, and exporting detection if consistent passes through
Result to the EMA be configured scanning element, otherwise export test errors result to EMA configuration scanning element；
34) scanning element is configured after the testing and diagnosing result of defect diagonsis unit is connected in the EMA,
If that test passes through as a result, then subtracting 1 by EMA values and return to step 32) continues test next time, until
Test errors have reached EMA as 0；
If test errors as a result, show it is previous reading relevant configuration be highest configuration, then will test
The EMA values of mistake add in 1 write-in EEPROM as the best EMA values of this chip；Or EMA has been configured into 0 still through then
EMA values 0 are written in EEPROM as the best EMA values of this chip；The test of this EMA best configuration is terminated.
The invention has the advantages that：The present invention makes equipment that can train the optimum performance for searching chip automatically once being switched on,
Not only training algorithm is optional for it, according to the SRAM test results adjust automatically EMA Configuration Values of each chip and can also be recorded,
Different EMA can be carried out according to the different SRAM performances of each chip to be configured, it simultaneously will be every on the basis of by training
The SRAM performances of a chip maximize, and have apparent advantage compared to current technology.
Description of the drawings
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the structure diagram of test device of the present invention.
Fig. 2 is the concrete structure block diagram that scanning element is configured in EMA in test device of the present invention.
Fig. 3 is the write operation sweep test flow diagram in the present invention.
Fig. 4 is the read operation sweep test flow diagram in the present invention.
Fig. 5 is the read-write mixed sweep testing process schematic diagram in the present invention.
Specific embodiment
The adaptive method for generating the configuration of chip optimum performance of the present invention, it is automatic to set after circuit starting up
The corresponding frequency configuration of good test target frequency；After the clock stable to be output to chip storage unit, band EMA is proceeded by
The EMA training flows of scanning；After the completion of EMA trains flow, internal EEPROM can store EMA best under the frequency and match
It puts to be configured when value is worked normally for chip and use.
The adaptive method for generating the configuration of chip optimum performance of the present invention can be tested in specific implementation by the present invention
Device is realized.
As depicted in figs. 1 and 2, the adaptive device 100 for generating the configuration of chip optimum performance of the invention is matched including frequency
Put unit 101, clock generating unit 102, EMA Training Controls unit 103, algorithms selection unit 104, BIST algorithm storage units
105th, BIST controller 106, defect diagonsis unit 107, EMA configurations scanning element 109, EEPROM and path selection unit
110；
The EMA Training Controls unit 103 passes sequentially through the frequency configuration unit 101, the clock generating unit 102
Connect memory 200 to be measured；The EMA Training Controls unit 103 also passes sequentially through the algorithms selection unit 104, BIST controls
Device 106 processed connects memory 200 to be measured；And the algorithms selection unit 104 is also connected with the BIST algorithms storage unit 105,
The BIST algorithms storage unit 105 is used to store the write operation sweep test algorithm for needing to use in bist testing process, reads behaviour
Make sweep test algorithm and read-write mixed sweep testing algorithm is called for algorithms selection unit 104；The BIST controller 106 is also
The EMA Training Controls unit 103 is connected by the defect diagonsis unit 107 and scanning element 109 is configured in the EMA；Institute
It states EMA Training Controls unit 103 and the path selection unit 110 is also connected by EMA configurations scanning element 109；It is described
EMA configurations scanning element 109 also connects the path selection unit 110 by EEPROM；The path selection unit 110 also connects
Memory 200 is surveyed in reception；
After circuit starting up, the frequency configuration unit 101 is set survey by the EMA Training Controls unit 103
Try the corresponding frequency configuration of target frequency；
Then after the output clock stable for waiting for the clock generating unit 102, the EMA Training Controls unit 103 is controlled
It makes the algorithms selection unit 104 and EMA configurations scanning element 109 proceeds by the EMA scanned with EMA and trains flow；
After the completion of EMA trains flow, internal EEPROM can store EMA Configuration Values best under the frequency for chip
It is configured and uses during normal work.
When chip enters normal mode of operation, it can use and be found most in the test process stored in internal EEPROM
Good EMA Configuration Values are configured and are worked to storage unit, to obtain best working performance.
It is main as shown in Fig. 2, the EMA configurations scanning element 109 further comprise EMA configurations control unit 1091,
EMAW Configuration Values storage unit 1092, EMAS Configuration Values storage unit 1093 and EMA Configuration Values storage unit 1094, it is described
EMA configurations control unit 1091 connects the EMAW Configuration Values storage unit 1092, the EMAS Configuration Values storage unit respectively
1093rd, the EMA Configuration Values storage unit 1094 and the EEPROM；It is the EMAW Configuration Values storage unit 1092, described
EMAS Configuration Values storage unit 1093 and the EMA Configuration Values storage unit 1094 pass through the path selection unit 110
Connect memory to be measured；
EMA configuration control unit 1091 be responsible for according to the defect diagonsis unit 107 export whether storage unit
The result for malfunctioning and misreading or wrongly writing is single the EMAW Configuration Values storage unit 1092, the EMAS Configuration Values to be controlled to store
Member 1093 and the EMA Configuration Values storage unit 1094 complete EMA configuration scanning behaviors and are sent to best EMA Configuration Values
EEPROM cell is stored.
Wherein, the EMA training flow includes the write operation sweep test, read operation sweep test and the read-write that carry out successively
Mixed sweep is tested；
As shown in figure 3, the write operation sweep test is specially：
11) control unit 1091 is configured to the EMAW Configuration Values by the EMA in the EMA configuration scanning elements 109
Storage unit 1092, EMAS Configuration Values storage unit 1093 and EMA Configuration Values storage unit 1094 are configured, and EMA is matched
111 are set to, EMAW is configured to 11, EMAS is configured to 1；Wherein：
EMA can control the additional access time for increasing memory, and Configuration Values are bigger, and the time is longer, access slower, setting
000 is most fast, device can normal risk highest, 111 access of setting are most slow, device can normally risk it is minimum；
EMAW individually controls the delay of write cycles, and Configuration Values are bigger, and the time is longer, and write access is slower (to be configured to 11 most
Slowly), device can normally risk it is lower；
EMAS controls can control the length for extending memory inside enable signals, and 0 is normal enable time spans,
1 is to extend enable time spans to extend that access speed after enable is slack-off but device reliability enhances；
Bist algorithms selections are detected the algorithm of write operation by the algorithms selection unit 104；
12) BIST controller 106 carries out memory 200 to be measured the excitation that action is write in special detection and pours into, and exports
The response results of memory 200 to be measured are to the defect diagonsis unit 107；
13) the defect diagonsis unit 107 compares the response results of memory 200 to be measured and expected result, so
The response that whether memory 200 to be measured is obtained under the special excitation for detecting and writing action afterwards is consistent with expection, if comparison one
It causes then to export and scanning element 109 is configured described in the result to EMA that detection passes through, otherwise export test errors and write operation mistake
Result to the EMA be configured scanning element 109；
14) scanning element 109 is configured after the testing and diagnosing result of defect diagonsis unit 107 is connected in the EMA, if surveyed
Examination diagnostic result is test errors, and the previous relevant configuration of writing shown has been highest configuration, then the EMAW is configured
EMAW values in value storage unit 1092 add in 1 write-in EEPROM as the best EMAW values of this chip for chip normal work when
It uses, then starts to go to read operation sweep test and (if first time write operation is tested with regard to test errors, then show lowest term
The mem of lower chip can not work normally, then is screened out directly as bad piece)；
If the result that the EMA configurations scanning element 109 is connected to passes through for test, it is still logical that EMAW has been configured into 0
It crosses, then EMAW values 0 is written in EEPROM as the best EMAW values of this chip, is then transferred to read operation sweep test；Otherwise
EMAW values are reduced by 1, step 12) is returned to, until test errors, then the EMAW values of test errors is added in 1 write-in EEPROM and are made
The best EMAW values of chip thus；
As shown in figure 4, the read operation sweep test is specially：
21) bist algorithms are changed to the algorithm of selection detection reading action by the algorithms selection unit 104, and EMAW values no longer become
Change, EMAS is first configured to 0 carry out one and takes turns test；
22) BIST controller 106 carries out memory 200 to be measured the excitation of special detection reading action and pours into, and exports
The response results of memory 200 to be measured are to the defect diagonsis unit 107；
23) the defect diagonsis unit 107 compares the response results of memory 200 to be measured and expected result, so
The response that whether memory 200 to be measured is obtained under the excitation of special detection reading action afterwards is consistent with expection, if consistent
Scanning element is configured to the EMA in the result that output detection passes through, otherwise 109 export the knot of test errors and read operation mistake
Scanning element 109 is configured to the EMA in fruit；
24) scanning element 109 is configured after the testing and diagnosing result of defect diagonsis unit 107 is connected in the EMA, if surveyed
Examination diagnostic result is test errors, and the previous reading relevant configuration shown has been highest configuration, then the EMAW is configured
It is worth the best EMAS values as this chip in the write-in of EMAS values 1 EEPROM in storage unit 1092；
It is to write the EMAS values 0 in the EMAS Configuration Values storage unit 1093 if test passes through if testing and diagnosing result
Enter in EEPROM as the best EMAS values of this chip；Then start to read and write mixed sweep test；
As shown in figure 5, the read-write mixed sweep test is specially：
31) the algorithms selection unit 104 by bist algorithms be changed to selection detection read-write mixing action algorithm, EMAW and
EMAS values no longer change, and subtracting 1 by EMA configurations starts to test；
32) excitation that 106 memory 200 to be measured of BIST controller is detected read-write motion pours into, and then exports
The response results of memory 200 to be measured are to the defect diagonsis unit 107；
33) the defect diagonsis unit 107 compares the response results of memory 200 to be measured and expected result, so
By memory 200 to be measured, whether the response obtained under the excitation of detection read-write motion is consistent with expection afterwards, defeated if consistent
Go out the result that detection passes through and scanning element 109 is configured to the EMA, it is single to EMA configuration scannings otherwise to export test errors result
Member 109；
34) scanning element 109 is configured after the testing and diagnosing result of defect diagonsis unit 107 is connected in the EMA, if
Test passing through as a result, then subtracting 1 by EMA values and return to step 32) continues test next time, until test errors or
It is 0 through reaching EMA；
If the result of test errors, the previous reading relevant configuration shown has been highest configuration, then matches EMA
The EMA values for putting the test errors in value storage unit 1094 add in 1 write-in EEPROM as the best EMA values of this chip；Or
EMA has been configured into 0 still through then EMA values 0 are written in EEPROM as the best EMA values of this chip；With regard to this EMA most
Good configuration testing terminates.
Finally, after chip switches back into normal mode of operation from test pattern, the routing path of the path selection unit 110
Diameter is changed to three EMA configurations of EEPROM, and chip is enable to be operated under oneself specific best EMA value, obtains best storage
The equalization point of device performance and stability.
Although specific embodiments of the present invention have been described above, those familiar with the art should manage
Solution, our described specific embodiments are merely exemplary rather than for the restriction to the scope of the present invention, are familiar with this
The equivalent modification and variation that the technical staff in field is made in the spirit according to the present invention, should all cover the present invention's
In scope of the claimed protection.
Claims (3)
- A kind of 1. adaptive method for generating the configuration of chip optimum performance, it is characterised in that：After circuit starting up, the corresponding frequency configuration of test target frequency is set automatically；After the clock stable to be output to chip storage unit, proceed by the EMA scanned with EMA and train flow；After the completion of EMA trains flow, it is normal for chip that internal EEPROM can store EMA Configuration Values best under the frequency It is configured and uses during work；The EMA training flow includes the write operation sweep test carried out successively, read operation sweep test and read-write mixed sweep Test；The write operation sweep test is specially：11) EMA is configured to 111, EMAW is configured to 11, EMAS is configured to 1, by bist algorithms selections detection write operation Algorithm；12) excitation that action is write in special detection is carried out to memory to be measured to pour into, export the response results of memory to be measured；13) response results of memory to be measured and expected result are compared, sees that memory to be measured writes action in special project detection Excitation under obtained response and expection it is whether consistent, the result that detection passes through is exported if comparison is consistent, otherwise output is surveyed Trial and error misses and the result of write operation mistake；If 14) test errors, the previous relevant configuration of writing shown has been highest configuration, then EMAW values is added 1 write-in It is used when being worked normally in EEPROM as the best EMAW values of this chip for chip, then starts to go to read operation scanning survey Examination；If test passes through, EMAW has been configured into 0 still through then EMAW values 0 are written in EEPROM as this chip Best EMAW values, are then transferred to read operation sweep test；Otherwise EMAW values are reduced by 1, returns to step 12)；The read operation sweep test is specially：21) bist algorithms are changed to the algorithm of selection detection reading action, EMAW values no longer change, and EMAS first is configured to 0 progress One wheel test；22) excitation that special detection reading action is carried out to memory to be measured pours into, and exports the response results of memory to be measured；23) response results of memory to be measured and expected result are compared, sees memory to be measured in special project detection reading action Excitation under obtained response and expection it is whether consistent, the result that detection passes through is exported if consistent, otherwise output test is wrong The result of mistake and read operation mistake；If 24) test errors, the previous reading relevant configuration shown has been highest configuration, then EMAS values 1 is written As the best EMAS values of this chip in EEPROM, EMAS values 0 are written in EEPROM if if test and are used as this chip Best EMAS values；Then start to read and write mixed sweep test；The read-write mixed sweep, which is tested, is specially：31) bist algorithms are changed to the algorithm of selection detection read-write mixing action, EMAW and EMAS values no longer change, EMA is matched It puts and subtracts 1 and start to test；32) excitation that read-write motion is detected to memory to be measured pours into, and then exports the response results of memory to be measured；33) response results of memory to be measured and expected result are compared, sees memory to be measured in detection read-write motion Whether the response obtained under excitation and expection are consistent, and the result that detection passes through is exported if consistent, otherwise exports test errors Result；34) it is if that test passes through as a result, then subtracting 1 by EMA values and return to step 32) continues test next time, until Test errors have reached EMA as 0；If the result of test errors, the previous read-write relevant configuration shown has been highest configuration, then will test mistake EMA values accidentally add in 1 write-in EEPROM as the best EMA values of this chip；Or EMA be configured into 0 still through, then will The best EMA values as this chip in EEPROM are written in EMA values 0；The test of this EMA best configuration is terminated.
- 2. the adaptive method for generating the configuration of chip optimum performance according to claim 1, it is characterised in that：The step 14) if first time write operation is tested with regard to test errors in, then show that the mem of chip under lowest term can not work normally, Unqualified defective chips are directly labeled as in EEPROM, and the EMA that the EMA Configuration Values of first time are write to EEPROM is best In configuration.
- 3. a kind of adaptive device for generating the configuration of chip optimum performance, it is characterised in that：Including EMA Training Controls unit, frequency Rate dispensing unit, clock generating unit, algorithms selection unit, BIST algorithms storage unit, BIST controller, defect diagonsis list Member, EMA configurations scanning element, EEPROM and path selection unit；The EMA Training Controls unit passes sequentially through the frequency configuration unit, the clock generating unit connects storage to be measured Device；The EMA Training Controls unit also passes sequentially through the algorithms selection unit, BIST controller connects memory to be measured；And The algorithms selection unit is also connected with the BIST algorithms storage unit；The BIST controller also passes through the defect diagonsis list Member connects the EMA Training Controls unit and EMA configuration scanning elements；The EMA Training Controls unit is also by described EMA configuration scanning elements connect the path selection unit；The EMA configurations scanning element is also connected described logical by EEPROM Road selecting unit；The path selection unit is also connected with memory to be measured；After circuit starting up, the frequency configuration unit is set test target frequency by the EMA Training Controls unit Corresponding frequency configuration；Then after the output clock stable for waiting for the clock generating unit, the EMA Training Controls unit control It makes the algorithms selection unit and EMA configurations scanning element proceeds by the EMA scanned with EMA and trains flow；It is instructed in EMA After the completion of practicing flow, internal EEPROM can store EMA Configuration Values best under the frequency for being configured during chip normal work It uses；The EMA training flow includes the write operation sweep test carried out successively, read operation sweep test and read-write mixed sweep Test；The write operation sweep test is specially：11) EMA is configured to 111 by the EMA configurations scanning element, and EMAW is configured to 11, EMAS is configured to 1, the calculation Bist algorithms selections are detected the algorithm of write operation by method selecting unit；12) excitation that the BIST controller writes action to the special detection of memory to be measured progress pours into, and exports memory to be measured Response results to the defect diagonsis unit；13) the defect diagonsis unit compares the response results of memory to be measured and expected result, sees memory to be measured Whether the response and expection obtained under the excitation for writing action in special detection be consistent, exports what detection passed through if comparison is consistent As a result scanning element is configured to the EMA, result to the EMA configurations for otherwise exporting test errors and write operation mistake are swept Retouch unit；If 14), result that EMA configuration scanning element is connected to is test errors, and what is shown previous has write relevant configuration Through be highest configuration, then using EMAW values add in 1 write-in EEPROM as the best EMAW values of this chip for chip work normally when It uses, then starts to go to read operation sweep test；If the result that EMA configuration scanning element is connected to passes through for test, EMAW has been configured into 0 still through then The best EMAW values as this chip in EEPROM are written in EMAW values 0, are then transferred to read operation sweep test；Otherwise by EMAW values 1 is reduced, returns to step 12)；The read operation sweep test is specially：21) bist algorithms are changed to the algorithm of selection detection reading action by the algorithms selection unit, and EMAW values no longer change, and first will EMAS is configured to 0 carry out one wheel test；22) to memory to be measured progress, the excitation of special detection reading action pours into the BIST controller, exports memory to be measured Response results to the defect diagonsis unit；23) the defect diagonsis unit compares the response results of memory to be measured and expected result, sees memory to be measured Whether the response and expection obtained under the excitation of special detection reading action be consistent, and the result that detection passes through is exported if consistent Scanning element is configured to the EMA, scanning list is configured to the EMA in the result for otherwise exporting test errors and read operation mistake Member；24) scanning element is configured after the testing and diagnosing result of defect diagonsis unit is connected in the EMA, if testing and diagnosing result For test errors, the previous reading relevant configuration shown has been highest configuration, then using EMAS values 1 be written in EEPROM as The best EMAS values of this chip；It is to test that EMAS values 0 are written in EEPROM to the best EMAS values for being used as this chip if if testing and diagnosing result； Then start to read and write mixed sweep test；The read-write mixed sweep, which is tested, is specially：31) bist algorithms are changed to the algorithm of selection detection read-write mixing action, EMAW and EMAS values by the algorithms selection unit No longer change, subtracting 1 by EMA configurations starts to test；32) BIST controller is detected memory to be measured the excitation of read-write motion and pours into, and then exports storage to be measured The response results of device are to the defect diagonsis unit；33) the defect diagonsis unit compares the response results of memory to be measured and expected result, sees memory to be measured Whether the response obtained under the excitation of detection read-write motion and expection are consistent, and the result that detection passes through is exported if consistent and is arrived Scanning element is configured in the EMA, and scanning element is configured to EMA in the result for otherwise exporting test errors；34) scanning element is configured after the testing and diagnosing result of defect diagonsis unit is connected in the EMA,It is if that test passes through as a result, then subtracting 1 by EMA values and return to step 32) continues test next time, until test Mistake has reached EMA as 0；If the result of test errors, the previous read-write relevant configuration shown has been highest configuration, then will test mistake EMA values accidentally add in 1 write-in EEPROM as the best EMA values of this chip；Or EMA be configured into 0 still through, then will The best EMA values as this chip in EEPROM are written in EMA values 0；The test of this EMA best configuration is terminated.
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