CN112909094B - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN112909094B
CN112909094B CN202110079912.2A CN202110079912A CN112909094B CN 112909094 B CN112909094 B CN 112909094B CN 202110079912 A CN202110079912 A CN 202110079912A CN 112909094 B CN112909094 B CN 112909094B
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葛薇薇
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Joulwatt Technology Co Ltd
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Abstract

公开了一种半导体器件，包括横向分布在所述半导体器件表面的阱区和漂移区，在阱区和漂移区中分别设置有源端掺杂区和漏端掺杂区，分别形成源端和漏端，栅极结构覆盖在阱区和漂移区之间，场板结构覆盖在漂移区上表面，用于辅助耗尽漂移区，其中，在漂移区上表面的位于场板结构与栅极结构之间的区域中设置有掺杂类型与漂移区的掺杂类型相反的表面掺杂区，该表面掺杂区电引出与场板结构电连接。本发明的半导体器件可使场板结构上表面的电位略低于场板结构下表面的电位，提升了场板结构对漂移区的辅助耗尽效果，提升半导体器件的击穿电压。

Description

半导体器件
技术领域
本发明涉及半导体技术领域，具体地，涉及半导体器件。
背景技术
为了提升功率LDMOS(laterally-diffused metal-oxide semiconductor，横向扩散金属氧化物半导体)的电学特性，通常需要提升其击穿电压 (BV)，并降低其比导通电阻。
常见的应用技术有场板技术、降低表面电场(resurf)技术、超结器件。其中，场板技术是一种被大量广泛应用的技术，其可以有效调节漂移区电场，提升器件的BV，并且可以在耐压状态下，辅助耗尽漂移区，在相同的耐压条件下可以有更大的掺杂浓度，更低的导通电阻。
发明内容
鉴于上述问题，本发明的目的在于提供一种半导体器件，从而提升场板结构对漂移区的辅助耗尽效果，进一步提升半导体器件的击穿电压，提升电学特性。
根据本发明的一方面，提供一种半导体器件，包括：
横向分布在所述半导体器件表面的阱区和漂移区，在所述阱区的远离所述漂移区的一端和所述漂移区的远离所述阱区的一端分别设置有源端掺杂区和漏端掺杂区；
栅极结构，覆盖在所述阱区和所述漂移区之间；
场板结构，覆盖在所述漂移区上表面，位于所述栅极结构与所述第二掺杂区之间，其中，
所述漂移区上表面还包括掺杂类型与所述漂移区的掺杂类型相反的表面掺杂区，所述表面掺杂区位于所述栅极结构与所述场板结构之间，所述表面掺杂区电引出与所述场板结构电连接。
可选地，所述场板结构包括横向间隔分布的多段。
可选地，所述阱区为通过所述栅极结构自对准形成的。
可选地，所述场板结构和所述栅极结构为采用同一块掩膜版为掩膜同时刻蚀形成。
可选地，还包括外延层，所述外延层位于衬底上，所述阱区和所述漂移区位于在所述外延层上表面且间隔分布。
可选地，所述漂移区为N型掺杂区；
所述阱区为P型掺杂区；
所述第一掺杂区包括横向连接的P型掺杂区和N型掺杂区，且所述第一掺杂区的P型掺杂区较N型掺杂区远离所述漂移区；
所述第二掺杂区为N型掺杂区。
可选地，所述表面掺杂区为P型掺杂区，所述表面掺杂区上表面还包括P型掺杂的电引出区，所述电引出区与所述场板结构电连接。
可选地，所述漂移区为P型掺杂区；
所述阱区为N型掺杂区；
所述第一掺杂区包括横向连接的N型掺杂区和P型掺杂区，且所述第一掺杂区的N型掺杂区较P型掺杂区远离所述漂移区；
所述第二掺杂区为P型掺杂区。
可选地，所述表面掺杂区为N型掺杂区，所述表面掺杂区上表面还包括N型掺杂的电引出区，所述电引出区与所述场板结构电连接。
可选地，所述漂移区中还设置有浅沟槽隔离结构和局部硅氧化隔离结构中的至少一种，所述浅沟槽隔离结构和所述局部氧化硅隔离结构中的至少一种设置在所述表面掺杂区、所述场板结构和所述漏端掺杂区的相邻的两个之间。
本发明提供的半导体器件包括横向分布在所述半导体器件表面的阱区和漂移区，在阱区和漂移区中分别设置有源端掺杂区和漏端掺杂区，分别形成源端和漏端，栅极结构覆盖在阱区和漂移区之间，场板结构覆盖在漂移区上表面，用于辅助耗尽漂移区，其中，在漂移区上表面的位于场板结构与栅极结构之间的区域中设置有掺杂类型与漂移区的掺杂类型相反的表面掺杂区，该表面掺杂区电引出与场板结构电连接，可使场板结构上表面的电位略低于场板结构下表面的电位，提升了场板结构对漂移区的辅助耗尽效果，提升半导体器件的击穿电压。且可在不增加场板结构的介质层厚度的情况下降低场板结构的介质层的击穿风险，保障了场板结构的电场调节能力。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示出了根据本发明实施例的半导体器件的整体结构示意图；
图2至图6示出了根据本发明实施例的半导体器件的部分制造工艺流程示意图。
具体实施方式
以下将参照附图更详细地描述本发明的各种实施例。在各个附图中，相同的元件采用相同或类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。
图1示出了根据本发明实施例的半导体器件的整体结构示意图。
如图1所示，本发明实施例的半导体器件100包括设置在衬底110 上的外延层120，外延层120的上表面(对应半导体器件100的上表面) 包括横向间隔分布的阱区140和漂移区130，阱区140的远离漂移区130 的一端的上表面包括横向连接分布的构成第一掺杂区的第一导电类型掺杂区141和第二导电类型掺杂区142，第一掺杂区对应源端掺杂区，形成源极S，漂移区130的远离阱区140的一端的上表面包括第二掺杂区 131，第二掺杂区131为第二导电类型掺杂，第二掺杂区131对应漏端掺杂区，形成漏极D，栅极结构151覆盖在半导体器件100的上表面，与阱区140的第二导电类型掺杂区142和漂移区130的接触连接，在栅极结构151的下表面形成沟道区。
在本实施中，阱区140和漂移区130间隔分布，在可选实施例中，阱区140和漂移区130接触设置。
其中，在栅极结构151和第二掺杂区131之间的漂移区130的上表面上还覆盖设置有场板结构152，漂移区130的上表面还包括表面掺杂区101，该表面掺杂区101的掺杂类型与漂移区130的掺杂类型相反，位于场板结构152和栅极结构151之间，且该表面掺杂区101的上表面还包括电引出区102，该电引出区102与场板结构152电连接至调节端 N1，接入场板调节电压输入，使得场板结构152的上表面的电位略低于其下表面的电位，提升场板结构152对漂移区130的辅助耗尽功效，同时还可有效地防止场板结构152下层的介质层的击穿。其中，表面掺杂区101中设置电引出区102，可提高电引出效果，提升对漂移区130的辅助耗尽功效。
在一种可选实施例中，半导体器件100为N型LDMOS，漂移区130 为N型掺杂区，阱区140为P型掺杂区，第一导电类型掺杂区141为P 型掺杂区，第二导电类型掺杂区142为N型掺杂区，第二掺杂区131为 N型掺杂区，表面掺杂区101为P型掺杂区，电引出区102为P型掺杂区。
在另一种可选实施例中，半导体器件100为P型LDMOS，漂移区 130为P型掺杂区，阱区140为N型掺杂区，第一导电类型掺杂区141 为N型掺杂区，第二导电类型掺杂区142为P型掺杂区，第二掺杂区131 为P型掺杂区，表面掺杂区101为N型掺杂区，电引出区102为N型掺杂区。
图2至图6示出了根据本发明实施例的半导体器件的部分制造工艺流程示意图。
参照图2至图6，本发明实施例的半导体器件100首先在衬底110 上生长外延层120，形成如图2所示的结构。其中，衬底110为材质锗、硅、硅锗、碳化硅、绝缘体上的硅或绝缘体上的锗等。对应N型LDMOS，外延层120为N型外延层，其中掺杂N型掺杂杂质离子，包括磷离子、砷离子或锑离子中的一种或几种，本发明对此不做特别限定。
然后在外延层120上表面进行漂移区130的注入，形成如图3所示的结构。设置外延层120，可提高半导体器件100的耐压，提升性能。其中，对应N型LDMOS，漂移区130为通过阱注入N型杂质离子形成的。
漂移区130注入后，在漂移区130上表面相应位置注入形成表面掺杂区101，形成如图4所示的结构。表面掺杂区101的掺杂类型与漂移区130的掺杂类型相反，对应N型LDMOS的N型掺杂的漂移区130，其表面掺杂区101为P型掺杂。
然后在外延层120和漂移区130的上表面热氧化形成栅氧化层，并在该栅氧化层上淀积多晶硅，然后刻蚀获得栅极结构151和场板结构152，形成如图5所示的结构。同时制作栅极结构151和场板结构152，可降低刻蚀的掩膜版的消耗，降低成本。
形成栅极结构151后，以栅极结构151为掩膜，自对准注入形成阱区140，形成如图6所示的结构。其中，对应N型LDMOS，阱区140 的注入杂质离子为P型杂质离子。
在本实施例中，阱区140为采用栅极结构151为掩膜自对准形成的，对位准确，阱区140与栅极结构151下表面形成的沟道区的的连接效果好。在可选实施例中，阱区140在制作栅极结构151之前注入形成，例如在形成漂移区130后，采用相应的掩膜板为掩膜进行注入形成，然后在外延层120、阱区140和漂移区130的上表面依次制作栅氧化层和多晶硅层，然后刻蚀形成栅极结构151和场板结构152。
然后在阱区140、表面掺杂区101和漂移区130的上表面的相应位置注入形成第一导电类型掺杂区141、第二导电类型掺杂区142、电引出区102和第二掺杂区131，并引出电极，即可形成如图1所示的本发明实施例的半导体器件100。其中，对应N型LDMOS，第一导电类型掺杂区141为P型杂质离子掺杂，第二导电类型掺杂区142为N型杂质离子掺杂，电引出区102为P型杂质离子掺杂，第二掺杂区131为N 型杂质离子掺杂，第一导电类型掺杂区141和第二导电类型掺杂区142 引出互连形成源极S，电引出区102与场板结构152电连接引出，连接场板电压输入，第二掺杂区131电引出形成漏极D，栅极结构151电引出为栅极G。
其中，场板结构152还可以是分段式场板，横向间隔分布在表面掺杂区101与第二掺杂区131之间。
本发明实施例的半导体器件100的漂移区130中可设置浅沟槽隔离结构和局部硅氧化隔离结构中的至少一种，设置在场板结构152与表面掺杂区101之间和场板结构152与第二掺杂区131之间，可保障场板结构152与第二掺杂区131之间的隔离性能，进一步提高半导体器件100 的击穿电压。
本发明的半导体器件在漂移区中形成位于源端与场板结构之间的表面掺杂区，该表面掺杂区电引出与场板结构电连接，可使场板结构上表面的电位略低于场板结构下表面的电位，提升了场板结构对漂移区的复制耗尽功效，同时又有效地防止了场板结构下表面的介质层在电场下的击穿，提升了半导体器件的击穿电压，提升本发明的半导体器件的电学特性。且在不增加场板结构的介质层厚度的情况下提升了场板结构的耐压，保障了场板结构对电场的调节能力。
利用栅极结构自对准注入形成阱区，提高阱区与栅极结构下表面的沟道区的对位准确度，提升了沟道性能，降低了比导通电阻，提升了半导体器件的电学性能。
阱区和漂移区设置在外延层中，可提高耐压。
对N型LDMOS和P型LDMOS均适用，实用性高。
表面掺杂区上表面还设置电引出区与场板结构电连接，提高表面掺杂区的电引出效果，可提升对场板结构的辅助效果，提升对漂移区的辅助耗尽效果，提升半导体器件的击穿电压，提升半导体器件的电学特性。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (10)

1.一种半导体器件，包括：
横向分布在所述半导体器件表面的阱区和漂移区，在所述阱区的远离所述漂移区的一端和所述漂移区的远离所述阱区的一端分别设置有源端掺杂区和漏端掺杂区；
栅极结构，覆盖在所述阱区和所述漂移区之间；
场板结构，覆盖在所述漂移区上表面，位于所述栅极结构与所述漏端掺杂区之间，且所述场板结构的介质层具有均匀的厚度，其中，
所述漂移区上表面还包括掺杂类型与所述漂移区的掺杂类型相反的表面掺杂区，所述表面掺杂区位于所述栅极结构与所述场板结构之间并与所述场板结构间隔一定距离，所述表面掺杂区电引出与所述场板结构的上表面电连接。
2.根据权利要求1所述的半导体器件，其中，
所述场板结构包括横向间隔分布的多段。
3.根据权利要求1所述的半导体器件，其中，
所述阱区为通过所述栅极结构自对准形成的。
4.根据权利要求1所述的半导体器件，其中，
所述场板结构和所述栅极结构为采用同一块掩膜版为掩膜同时刻蚀形成。
5.根据权利要求1所述的半导体器件，其中，
还包括外延层，所述外延层位于衬底上，所述阱区和所述漂移区位于在所述外延层上表面且间隔分布。
6.根据权利要求1所述的半导体器件，其中，
所述漂移区为N型掺杂区；
所述阱区为P型掺杂区；
所述源端掺杂区包括横向连接的P型掺杂区和N型掺杂区，且所述源端掺杂区的P型掺杂区较N型掺杂区远离所述漂移区；
所述漏端掺杂区为N型掺杂区。
7.根据权利要求6所述的半导体器件，其中，
所述表面掺杂区为P型掺杂区，所述表面掺杂区上表面还包括P型掺杂的电引出区，所述电引出区与所述场板结构电连接。
8.根据权利要求1所述的半导体器件，其中，
所述漂移区为P型掺杂区；
所述阱区为N型掺杂区；
所述源端掺杂区包括横向连接的N型掺杂区和P型掺杂区，且所述源端掺杂区的N型掺杂区较P型掺杂区远离所述漂移区；
所述漏端掺杂区为P型掺杂区。
9.根据权利要求8所述的半导体器件，其中，
所述表面掺杂区为N型掺杂区，所述表面掺杂区上表面还包括N型掺杂的电引出区，所述电引出区与所述场板结构电连接。
10.根据权利要求1所述的半导体器件，其中，
所述漂移区中还设置有浅沟槽隔离结构和局部硅氧化隔离结构中的至少一种，所述浅沟槽隔离结构和所述局部氧化硅隔离结构中的至少一种设置在所述表面掺杂区、所述场板结构和所述漏端掺杂区的相邻的两个之间。
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