CN112905946B - Variable symbol rate and arbitrary path parallel input interpolation method - Google Patents

Abstract

The invention discloses a variable symbol rate and arbitrary path parallel input interpolation method, which comprises the following steps: s1: the upper computer inputs control parameters, mainly determining the parallel input path number P; s2: reading input data, and sequentially reading data of signal input x from the RAM; s3: calculating an error interval mu _m by a mu value generator; s4: sequentially extracting [ x (n-P+1), & gtx (n-2), x (n-1), x (n) ] (n is greater than or equal to P) P-bit data from data read from the RAM, and substituting the P-bit data into a formula by combining mu _nm valuesThe invention provides a variable symbol rate and arbitrary path parallel input interpolation method, which can realize modulation with a sampling rate from low to high and great change under the condition that the working clock of an FPGA system is not high.

Description

Variable symbol rate and arbitrary path parallel input interpolation method

Technical Field

The invention relates to the technical field of wireless communication synchronization, in particular to a variable symbol rate and random path parallel input interpolation method.

Background

It is often desirable in the fields of communications, radar, navigation, etc. to generate any symbol rate communication signals. More common methods for changing the symbol rate are to change the oversampling rate of the signal or to change the clock frequency, but both methods are complicated in hardware implementation, consume large amounts of hardware resources, and are therefore unsuitable for generating signals with a large range of symbol rates. The improved method is realized by combining filters, such as integer multiple interpolation and fractional multiple interpolation, FARROW and CIC, FARROW and HB, FIR and CIC, FIR and HB, and the like.

The conventional method of variable symbol rate achieves a limited range of symbol rate variation, typically from tens of Kbps to tens of Mbps. In practical engineering applications, this range of symbol rate variation is far from adequate. Because the working clock of the FPGA system is not high, the existing method needs to be innovated if the symbol change rate is from Kbps to Gbps and spans multiple orders of magnitude.

Disclosure of Invention

In order to solve the technical problems in the prior art, the invention provides a variable symbol rate interpolation method capable of inputting any paths in parallel.

The technical scheme of the invention is as follows: a variable symbol rate and arbitrary path parallel input interpolation method is characterized by comprising the following steps:

S1: the upper computer inputs control parameters, mainly determining the parallel input path number P;

S2: the input data is read and the data of the signal input x is sequentially read from the RAM. In practical application, because the input data is longer, the whole input data is stored into the RAM at one time, so that too much resources are occupied, the data is generally read in sections, and if the data is input in parallel in P paths, the data with the length of 3P-4P is stored into the RAM;

S3: the error interval mu _m is calculated by a mu value generator, mainly by the formula Wherein T _x is the transmitter signal period, T _y is the receiver signal period, μ _m ε [0, 1); when the path number P paths are input in parallel, mu _m is also the path number P paths for parallel calculation and input;

S4: sequentially extracting [ x (n-P+1), & gtx (n-2), x (n-1), x (n) ] (n is greater than or equal to P) P-bit data from data read from the RAM, and substituting the P-bit data into a formula by combining mu _nm values And calculating to obtain a corresponding output y _sum value.

Preferably, the control parameters further include a total length L of data, divided into M segments, each segment length N, an output sampling clock T _y, and an input sampling clock T _x.

Preferably, the number of paths P ranges from 1 path to 8 paths.

Preferably, the number of paths P is 4.

Preferably, the read input data is the first 16 bits of data of sequential read signal input, named x_in.

Preferably, when the path number P is 4 paths of parallel input, mu _m is also 4 paths of parallel calculation and input;

four parallel inputs of the first round mu _m, selecting corresponding 4 x_in inputs to pass through the FARROW structure and then outputting [ y (1), y (2), y (3), y (4) ] in parallel;

four parallel inputs of the second round mu _m, selecting corresponding 4 x_in inputs to pass through the FARROW structure and then outputting [ y (5), y (6), y (7), y (8) ];

When [ x_in (13), x_in (14), x_in (15), x_in (16) ] is read, the 16 data of x_in is updated, the new array retains the last 8 bits of data of the previous group, and x 8 bits of data x (17) to x (24) are sequentially supplemented, namely updated x_in= [ x (9), x (10), …, x (16), x (17), …, x (24) ].

Repeating S1-S3, and when the data of the last group x is read and the number of the residual data is smaller than 8, adding zero to the insufficient digits to x_in.

Compared with the prior art, the invention has the following beneficial effects:

Compared with the prior art, if a multiphase structure is adopted to realize sampling rate conversion, a large amount of resources can be occupied under certain conditions; most of the prior art is serial structure to realize sampling rate conversion, and has low efficiency. The invention has the following benefits: modulation with a sampling rate that varies greatly from low to high can be realized under the condition that the working clock of the FPGA system is not high.

Drawings

FIG. 1 is a system block diagram of a P-way parallel input;

FIG. 2 is a diagram of a variable symbol rate;

FIG. 3 is an original Gaussian power spectrum;

FIG. 4 is a Gaussian power spectrum after 2 times FARROW interpolation;

Fig. 5 is a graph of symbol rate versus parallel input path number.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the present invention, it should be understood that, in terms of "front", "rear", "left", "right", "upper", "lower", etc., the directions or positional relationships indicated are based on the directions or positional relationships shown in the drawings, which are merely for convenience in describing the present invention and simplifying the description, but are not meant to indicate or imply that the devices or elements to be referred to must have specific directions, be configured and operated in specific directions, and thus should not be construed as limiting the present invention, the technical solutions of the embodiments of the present invention may be combined, and the technical features of the embodiments may also be combined to form a new technical solution.

Referring to fig. 1 to 5, the present invention provides the following technical solutions: a variable symbol rate and arbitrary path parallel input interpolation method is characterized by comprising the following steps:

S1: the upper computer inputs control parameters, mainly determining the parallel input path number P;

S2: the input data is read and the data of the signal input x is sequentially read from the RAM. In practical application, because the input data is longer, the whole input data is stored into the RAM at one time, so that too much resources are occupied, the data is generally read in sections, and if the data is input in parallel in P paths, the data with the length of 3P-4P is stored into the RAM;

S3: mu _m is calculated by a mu value generator, mainly by the formula Wherein T _x is the transmitter signal period, T _y is the receiver signal period, μ _m ε [0, 1); when the path number P paths are input in parallel, mu _m is also the path number P paths for parallel calculation and input;

S4: sequentially extracting [ x (n-P+1), & gtx (n-2), x (n-1), x (n) ] (n is greater than or equal to P) P-bit data from data read from the RAM, and substituting the P-bit data into a formula by combining mu _nm values And calculating to obtain a corresponding output y _sum value.

Further, the control parameters further include a total length L of the data, a division into M segments, a length N of each segment, an output sampling clock T _y, and an input sampling clock T _x.

Further, the number of paths P ranges from 1 to 8.

Further, the number of paths P is 4.

Further, the read input data is the first 16-bit data of the sequential read signal input, and is named as x_in.

Furthermore, when the number of paths P is 4 paths of parallel input, mu _m is also 4 paths of parallel calculation and input;

four parallel inputs of the first round mu _m, selecting corresponding 4 x_in inputs to pass through the FARROW structure and then outputting [ y (1), y (2), y (3), y (4) ] in parallel;

four parallel inputs of the second round mu _m, selecting corresponding 4 x_in inputs to pass through the FARROW structure and then outputting [ y (5), y (6), y (7), y (8) ];

When [ x_in (13), x_in (14), x_in (15), x_in (16) ] is read, the 16 data of x_in is updated, the new array retains the last 8 bits of data of the previous group, and x 8 bits of data x (17) to x (24) are sequentially supplemented, namely updated x_in= [ x (9), x (10), …, x (16), x (17), …, x (24) ].

Repeating S1-S3, and when the data of the last group x is read and the number of the residual data is smaller than 8, adding zero to the insufficient digits to x_in.

Examples

Let p=4, m=20, n=267, Δμ=0.534.

The method comprises the following steps:

Step S1: reading input data

The first 16 bits of data of signal input x are sequentially read, named x_in.

Step S2: mu _m was calculated.

The calculation formula of v is as follows:

Combined (1): with known inputs, the most critical is to calculate the output, and to find the error interval μ _m.

When (when)When used, mu _m is shown in Table 1.

TABLE 1

m	1	2	3	4	5	6	7	8	9	10	11	...
													μm	0	0.534	0.068	0.602	0.136	0.670	0.204	0.738	0.272	0.806	0.340	...

Step S3: substituting the input data into a formula to calculate to obtain a corresponding output y value

In the case of four-way parallel input, mu _m is also four-way parallel calculation and input.

Four parallel inputs [0,0.534,0.068,0.602] of the first round mu _m, and selecting corresponding 4 x_in inputs to pass through the FARROW structure and then outputting [ y (1), y (2), y (3), y (4) ]';

four parallel inputs [0.136,0.670,0.204,0.738]', of the second round μ _m, select the corresponding 4 x_in inputs

Parallel output [ y (5), y (6), y (7), y (8) ] after passing through the FARROW structure;

When [ x_in (13), x_in (14), x_in (15), x_in (16) ] is read, the 16 data of x_in is updated, the new array retains the last 8 bits of data of the previous group, and x 8 bits of data x (17) to x (24) are sequentially supplemented, namely updated x_in= [ x (9), x (10), …, x (16), x (17), …, x (24) ].

Repeating the steps S1-S3, and when the data of the last group x is read and the number of the residual data is smaller than 8, adding zero to the insufficient number of bits to x_in.

The steps are operation of 4 paths of parallel time, and other parallel paths are processed in a conventional way.

Fig. 2 is a diagram of a variable symbol rate. On the basis of figure 1, n-1 paths (n paths in parallel) are combined.

Any path of parallel input and any symbol rate conversion can be realized.

Fig. 2 is a graph of noise power before and after the FARROW interpolation filter.

In this embodiment, the system operating frequency f _s =1000 Hz, and the data with the code rate of R _b =10 Kbps corresponding to the continuous variable rate digital filter processing method of the present invention is subjected to variable rate interpolation filtering processing with interpolation multiple of 2 times. The filter adopts a third-order FIR filter, and the coefficients of the FIR filter are quantized by 32 bits.

The original Gaussian power spectrum and the Gaussian power spectrum subjected to 2 times of FARROW interpolation are obtained through simulation, and the detail is shown in the accompanying drawings 3 and 4.

The principle of the invention is as follows:

The general resampling mathematical model is that the sampled signal x (nT _x) passes through the interpolator h (·) to output a signal Resampling the signal at time t=mt _y, then outputting the signalT _x is the sampling interval, m ε Z, and T _y is the sampling interval of the receiver.

According to the implementation principle of the FARROW filter, in order to make the sampling rates of the receiving and transmitting sides consistent, the sampling rate conversion must be performed, and the conversion formula is as follows:

Wherein the method comprises the steps of K _m is the interpolation base, μ _m is the error interval, determine the interpolation filter impulse response coefficient, μ _m∈[0,1),k_m ε N,

Simplifying (2) to obtain:

Let k=k _m -n, formula (3) can be expressed as:

To reduce the computation of the system function h (·) a polynomial expansion is typically used, taking the lagrangian polynomial approximation as an example, with:

Wherein, For the coefficients of the FARROW filter, l and k represent the number of rows and columns, respectively, and in combination with equation (5), equation (3) can be converted to the following expression:

simplifying (6) to obtain:

Wherein the method comprises the steps of

When P paths of parallel input are performed, the total output y _sum expression is as follows:

Wherein μ _nm represents μ _m value corresponding to the nth output, p∈n ⁺,Q∈N⁺.

The input end is provided with P paths of parallel input, each path is provided with M sections, and the length of each section is N.

To ensure continuity of the data filtering output, there is overlap between segments, the head of each segment will be connected to the last three data of the tail of the previous segment, and the first segment will be filled with three zeros at the head of the segment.

The invention can realize any path of parallel input and the symbol rate can also be transformed in a large range.

Taking 200Mhz as an example of an FPGA system working clock, if the symbol rate is to be realized from 1Kbps to 1.6Gbps, the sampling rate is from 4Kbps to 4Gbps, only 8 groups of structures are needed to operate in parallel.

When 1-path is input, the symbol rate can be up to 200Mbaud/s, when 2-path is input in parallel, the symbol rate can be up to 400Mbaud/s, when 8-path is input in parallel, the symbol rate can be up to 1.6Gbaud/s, and the coverage range is from Kbps to Gbps. A wide range of symbol rates can be covered and matched, with the correspondence shown in fig. 5.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (2)

1. A variable symbol rate and arbitrary path parallel input interpolation method is characterized by comprising the following steps:

s1: the upper computer inputs control parameters and determines the number P of paths input in parallel;

S2: reading input data, sequentially reading data of signal input x from the RAM, reading the input data in a segmented mode, and storing data with the length of 3P-4P into the RAM if the input data are input in parallel in P paths;

S3: mu _m is calculated by a mu value generator, the formula is Wherein T _x is the transmitter signal period, T _y is the receiver signal period, μ _m ε [0, 1); when the path number P paths are input in parallel, mu _m is also the path number P paths for parallel calculation and input;

S4: sequentially extracting [ x (n-P+1), & gtx (n-2), x (n-1), x (n) ] P bit data from data read from the RAM, wherein n is more than or equal to P, and substituting the n is more than or equal to P into a formula by combining mu _nm value Calculating to obtain a corresponding output y _sum value;

the number of paths P ranges from 1 path to 8 paths,

When the number of paths P is 4,

The read input data is the first 16 bits of data of the sequential read signal input, named x in,

When the number of paths P is 4, mu _m is also 4 parallel calculation and input;

four parallel inputs of the first round mu _m, selecting corresponding 4 x_in inputs to pass through the FARROW structure and then outputting [ y (1), y (2), y (3), y (4) ] in parallel;

four parallel inputs of the second round mu _m, selecting corresponding 4 x_in inputs to pass through the FARROW structure and then outputting [ y (5), y (6), y (7), y (8) ];

When [ x_in (13), x_in (14), x_in (15), x_in (16) ] is read, updating 16 data of x_in, reserving the last 8 bits of data of the previous group by the new array, and sequentially supplementing 8 bits of data x (17) -x (24) of x, namely, updated x_in= [ x (9), x (10), …, x (16), x (17), …, x (24) ];

Repeating S1-S3, and when the data of the last group x is read and the number of the residual data is smaller than 8, adding zero to the insufficient digits to x_in.

2. The method of claim 1, wherein the control parameters further include a total length L of the data, a division into M segments, a length N of each segment, a receiver signal period T _y, and a transmitter signal period T _x.