CN111930046A - FPGA-based signal interpolation method and signal acquisition and playback method - Google Patents
FPGA-based signal interpolation method and signal acquisition and playback method Download PDFInfo
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Abstract
The application relates to a signal interpolation method and a signal acquisition and playback method based on an FPGA. The signal interpolation method based on the FPGA comprises the following steps: acquiring an input digital signal; copying the input digital signal into N digital signals and inputting the N digital signals into N FPGA-based digital filtering modules, wherein N is an even number, and the N FPGA-based digital filtering modules are constructed in a manner that the filter coefficients of every two filters are symmetrically constructed; merging and carrying out difference value processing on the N filtered digital signals according to every two filters with symmetrical filter coefficients to obtain N processed digital signals; and performing parallel-to-serial conversion on the N processed digital signals to obtain interpolated digital signals. Thus, the resource consumption of the FPGA is reduced.
Description
Technical Field
The present application relates generally to the field of signal processing technology, and more particularly, to an FPGA-based signal interpolation method, an FPGA-based signal acquisition and playback method, an electronic device, and a computer-readable storage medium.
Background
An analog signal refers to information expressed as a continuously varying physical quantity, such as temperature, humidity, pressure, length, current, voltage, etc., and is often referred to as a continuous signal, which may have an infinite number of different values over a certain time period. While digital signals refer to signals that are discrete, discontinuous in value.
Various physical quantities in actual production and life, such as images shot by a camera, sounds recorded by a recorder, pressure, flow rate, rotation speed, humidity and the like recorded in a workshop control room are analog signals. The digital signal is formed by sampling, quantizing and encoding on the basis of the analog signal. Specifically, sampling is to obtain sample values at each time instant from an input analog signal at appropriate time intervals, and quantization is to represent the sampled values at each time instant by a binary code system, and coding is to arrange binary numbers generated by quantization together to form a sequential pulse sequence.
In many fields of signal processing of analog signals, a scheme of analog playback after digital acquisition and interpolation of analog signals is required, and the scheme can be implemented based on an FPGA (Field-Programmable Gate Array).
However, the existing signal interpolation method and signal acquisition and playback method based on the FPGA have the problem of large FPGA resource consumption. Accordingly, it is desirable to provide an improved FPGA-based signal interpolation method and signal acquisition and playback method.
Disclosure of Invention
The present application is proposed in order to meet the above-mentioned technical needs. The embodiment of the application provides a signal interpolation method and a signal acquisition and playback method based on an FPGA (field programmable gate array). N digital filtering modules based on the FPGA are constructed in a mode that filter coefficients of every two filters are constructed symmetrically, and N filtered digital signals are merged and subjected to difference processing according to every two filters with symmetric filter coefficients, so that the resource consumption of the FPGA is reduced.
According to an aspect of the present application, there is provided a signal interpolation method based on an FPGA, including:
acquiring an input digital signal;
copying the input digital signal into N digital signals and inputting the N digital signals into N FPGA-based digital filtering modules, wherein N is an even number, and the N FPGA-based digital filtering modules are constructed in a manner that the filter coefficients of every two filters are symmetrically constructed;
merging and carrying out difference value processing on the N filtered digital signals according to every two filters with symmetrical filter coefficients to obtain N processed digital signals; and
the N processed digital signals are parallel-to-serial converted to obtain interpolated digital signals.
In the above FPGA-based signal interpolation method, N is 4.
In the above FPGA-based signal interpolation method, a prototype filter coefficient corresponding to the input digital signal is split into a first sub-filter coefficient, a second sub-filter coefficient, a third sub-filter coefficient, and a fourth sub-filter coefficient; and the filter coefficients of the 4 FPGA-based digital filtering modules are respectively the sum of the first sub-filter coefficient and the second sub-filter coefficient, the difference between the first sub-filter coefficient and the second sub-filter coefficient, the sum of the third sub-filter coefficient and the fourth sub-filter coefficient, and the difference between the third sub-filter coefficient and the fourth sub-filter coefficient.
In the signal interpolation method based on the FPGA, the 4 FPGA-based digital filtering modules are used for obtaining a first sub-digital signal, a second sub-digital signal, a third sub-digital signal and a fourth sub-digital signal after filtering; and the 4 processed digital signals are respectively the sum of the first sub-digital signal and the second sub-digital signal divided by two, the difference between the first sub-digital signal and the second sub-digital signal divided by two, the sum of the third sub-digital signal and the fourth sub-digital signal divided by two, and the difference between the third sub-digital signal and the fourth sub-digital signal divided by two.
In the above FPGA-based signal interpolation method, a prototype filter coefficient corresponding to the input digital signal is split into a first sub-filter coefficient, a second sub-filter coefficient, a third sub-filter coefficient, and a fourth sub-filter coefficient; and the filter coefficients of the 4 FPGA-based digital filtering modules are respectively the sum of the first sub-filter coefficient and the third sub-filter coefficient, the difference between the first sub-filter coefficient and the third sub-filter coefficient, the sum of the second sub-filter coefficient and the fourth sub-filter coefficient, and the difference between the second sub-filter coefficient and the fourth sub-filter coefficient.
In the signal interpolation method based on the FPGA, the 4 FPGA-based digital filtering modules are used for obtaining a first sub-digital signal, a second sub-digital signal, a third sub-digital signal and a fourth sub-digital signal after filtering; and the 4 processed digital signals are respectively the sum of the first sub-digital signal and the second sub-digital signal divided by two, the difference between the third sub-digital signal and the fourth sub-digital signal divided by two, the difference between the first sub-digital signal and the second sub-digital signal divided by two, and the difference between the third sub-digital signal and the fourth sub-digital signal divided by two.
In the above FPGA-based signal interpolation method, a prototype filter coefficient corresponding to the input digital signal is split into a first sub-filter coefficient, a second sub-filter coefficient, a third sub-filter coefficient, and a fourth sub-filter coefficient; and the filter coefficients of the 4 FPGA-based digital filtering modules are respectively the sum of the first sub-filter coefficient and the fourth sub-filter coefficient, the difference between the first sub-filter coefficient and the fourth sub-filter coefficient, the sum of the second sub-filter coefficient and the third sub-filter coefficient, and the difference between the second sub-filter coefficient and the third sub-filter coefficient.
In the signal interpolation method based on the FPGA, the 4 FPGA-based digital filtering modules are used for obtaining a first sub-digital signal, a second sub-digital signal, a third sub-digital signal and a fourth sub-digital signal after filtering; and the 4 processed digital signals are respectively the sum of the first sub-digital signal and the second sub-digital signal divided by two, the sum of the third sub-digital signal and the fourth sub-digital signal divided by two, the difference between the third sub-digital signal and the fourth sub-digital signal divided by two, and the difference between the first sub-digital signal and the second sub-digital signal divided by two.
According to another aspect of the present application, there is provided a signal acquisition and playback method based on an FPGA, including:
collecting an analog signal and carrying out analog-to-digital conversion on the analog signal to obtain an input digital signal;
interpolating the digital signal by the FPGA-based signal interpolation method to obtain an interpolated digital signal; and
and D/A converting the interpolated digital signal to obtain an analog signal for playback.
According to still another aspect of the present application, there is provided an electronic apparatus including: a processor; and a memory having stored therein computer program instructions which, when executed by the processor, cause the processor to perform the FPGA-based signal interpolation method as described above or the FPGA-based signal acquisition and playback method as described above.
According to yet another aspect of the present application, there is provided a computer readable storage medium having stored thereon computer program instructions operable, when executed by a computing device, to perform an FPGA-based signal interpolation method as described above or an FPGA-based signal acquisition and playback method as described above.
According to the FPGA-based signal interpolation method and the signal acquisition and playback method, N FPGA-based digital filtering modules are constructed in a mode that filter coefficients of every two filters are constructed symmetrically, the N filtered digital signals are merged and subjected to difference value processing according to every two filters with symmetric filter coefficients, and resource consumption of the FPGA in a signal interpolation process can be reduced through symmetric design of the coefficients of the filters.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing in more detail embodiments of the present application with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings, like reference numbers generally represent like parts or steps.
Fig. 1 is a schematic diagram illustrating a processing architecture of a serial processing procedure of prior analog signal acquisition and playback after interpolation.
Fig. 2 is a schematic diagram illustrating a processing architecture of a parallel processing process of prior analog signal acquisition and playback after interpolation.
FIG. 3 illustrates a flow chart of a method of FPGA-based signal interpolation according to an embodiment of the present application.
Fig. 4 illustrates a schematic diagram of a processing architecture of 4-fold interpolation of an FPGA-based signal interpolation method according to an embodiment of the present application.
FIG. 5 illustrates a flow chart of an FPGA-based signal acquisition and playback method according to an embodiment of the present application.
Fig. 6 illustrates a schematic diagram of a processing architecture of N-fold interpolation for an FPGA-based signal acquisition and playback method according to an embodiment of the present application.
FIG. 7 illustrates a block diagram of an electronic device in accordance with an embodiment of the present application.
Detailed Description
Hereinafter, example embodiments according to the present application will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are merely some embodiments of the present application and not all embodiments of the present application, with the understanding that the present application is not limited to the example embodiments described herein.
Summary of the application
As described above, in the existing signal interpolation process implemented based on the FPGA, taking 4-fold interpolation as an example, the processing process of the FPGA for analog playback after analog digital signal acquisition and 4-fold interpolation is as follows:
1) inputting an analog signal a to an analog-to-digital converter;
2) the analog-to-digital converter samples the analog signal a at a sampling rate of clk _1x to obtain a digital signal b;
3) obtaining a digital signal c by digital interpolation b to 4 times of a sampling rate clk _4 x; and
4) the digital-to-analog converter converts the digital signal c to an analog signal d for output at a refresh rate of clk _4 x.
Under such processing requirements, the existing processing procedure mainly has two types, namely serial processing and parallel processing.
Fig. 1 is a schematic diagram illustrating a processing architecture of a serial processing procedure of prior analog signal acquisition and playback after interpolation. As shown in fig. 1, the processing architecture of the serial processing process includes a 4-fold digital signal interpolation module, which interpolates the input digital signal b to a sampling rate clk _4x to obtain a digital signal bu, and then digitally filters the digital signal bu using a digital filter operating at a clock frequency of clk _4x to obtain a digital signal c.
Fig. 2 is a schematic diagram illustrating a processing architecture of a parallel processing process of prior analog signal acquisition and playback after interpolation. As shown in fig. 2, the processing architecture of the parallel processing process includes N-channel digital signal copying, N-channel digital filtering and parallel-serial conversion modules, where after the digital signal b is copied, the digital signal b is subjected to digital filtering operation by N-channel digital filters operating at clk _1x clock frequency to obtain b0, b1, b2, and b3, and then the digital signal c is obtained by performing parallel-serial conversion operation on b0, b1, b2, and b 3.
However, the serial processing described above requires the FPGA to operate at 4 times clk _1x clock, whereas in the parallel processing described above, although the FPGA operates at clk _1x clock frequency, the filter resource consumption is the same as in the serial processing.
In view of the above technical problems, the basic concept of the present application is to symmetrically construct the filter coefficients of every two filters, and then combine and difference-process the digital signals filtered by the filters according to every two filters with symmetric filter coefficients.
Specifically, the FPGA-based signal interpolation method provided by the present application first obtains an input digital signal, then copies the input digital signal into N digital signals and inputs the N digital signals into N FPGA-based digital filtering modules, where N is an even number, where the N FPGA-based digital filtering modules are constructed in a manner that filter coefficients of every two filters are symmetrically constructed, then combines and performs difference processing on the N filtered digital signals according to every two filters with symmetric filter coefficients to obtain N processed digital signals, and finally performs parallel-to-serial conversion on the N processed digital signals to obtain an interpolated digital signal.
Correspondingly, the signal acquisition and playback method based on the FPGA first acquires an analog signal and performs analog-to-digital conversion on the analog signal to obtain an input digital signal, and then interpolates the digital signal by the signal interpolation method based on the FPGA to obtain an interpolated digital signal; and finally, performing digital-to-analog conversion on the interpolated digital signal to obtain an analog signal for playback.
Therefore, the FPGA-based signal interpolation method and the signal acquisition and playback method of the application are used for researching a resource optimization scheme of the FPGA for digital signal interpolation or analog signal digital acquisition and playback after interpolation aiming at the defects of the existing method, and it can be seen that the resource consumption in the interpolation process is reduced by half compared with the resource consumption in the existing method.
Having described the general principles of the present application, various non-limiting embodiments of the present application will now be described with reference to the accompanying drawings.
Exemplary method
FIG. 3 illustrates a flow chart of a method of FPGA-based signal interpolation according to an embodiment of the present application.
As shown in fig. 3, the FPGA-based signal interpolation method according to the embodiment of the present application includes the following steps.
In step S110, an input digital signal is acquired. As shown in fig. 4, an input digital signal b is obtained, but it is understood by those skilled in the art that an analog signal may be obtained first and then converted into a digital signal by analog-to-digital conversion. Here, fig. 4 illustrates a schematic diagram of a processing architecture of 4-fold interpolation of the FPGA-based signal interpolation method according to an embodiment of the present application.
Step S120, copying the input digital signal into N digital signals and inputting the N digital signals into N FPGA-based digital filtering modules, where N is an even number, and the N FPGA-based digital filtering modules are constructed in a manner that filter coefficients of every two filters are symmetrically constructed. As shown in fig. 4, the input digital signal b is copied into 4 digital signals b and input into 4 FPGA-based digital filtering modules, thereby obtaining 4 digital signals bf0, bf1, bf2 and bf3 after filtering.
In the embodiment of the application, in order to save the resource consumption of the FPGA in the interpolation process, every two filters are constructed in a symmetrical manner of filter coefficients, so that N digital filtering modules based on the FPGA are constructed. Of course, those skilled in the art can understand that if the interpolation multiple N is an odd number, N-1 filters can be constructed in a manner that the filter coefficients of every two filters are symmetrical, so as to save the resource consumption of the FPGA in the interpolation process.
Here, the symmetric design of the filter coefficients mainly involves splitting and combining the prototype filter coefficients, which will be explained in further detail below.
Step S130, combining and difference processing the N filtered digital signals according to every two filters with symmetric filter coefficients to obtain N processed digital signals. That is, since the filter coefficients of every two filters are symmetrical, the filtered digital signals obtained by the two filters are also symmetrical, so that two processed digital signals corresponding to the split prototype filter coefficients can be obtained by combining and difference-processing the two filtered digital signals, respectively. For example, as shown in fig. 4, the post-processing module shows that each two filters of the filtered 4 digital signals, which are symmetric according to the filter coefficients, are combined and subjected to difference processing, so as to obtain 4 processed digital signals b0, b1, b2 and b 3.
Specifically, the way in which the filtered N digital signals are combined and difference-processed by every two filters with symmetric filter coefficients corresponds to the symmetric design of the filter coefficients, which will also be described in further detail below.
In step S140, the N processed digital signals are parallel-to-serial converted to obtain interpolated digital signals. For example, as shown in fig. 4, 4 processed digital signals b0, b1, b2, and b3 are parallel-to-serial converted to obtain an interpolated digital signal c.
Hereinafter, a symmetric design manner of filter coefficients and combination and difference processing of filtered digital signals in the signal interpolation method according to the embodiment of the present application will be described by taking N as an example of 4.
First, assume that the prototype filter coefficient of the clock frequency clk _4x in the serial processing is h _4x, which is split into h _4x _0, h _4x _1, h _4x _2, and h _4x _3, where:
h_4x_0＝h_4x(1:4:end)；
h_4x_1＝h_4x(2:4:end)；
h_4x_2＝h_4x(3:4:end)；
h_4x_3＝h_4x(4:4:end)；
here, as can be understood by those skilled in the art, the prototype filter coefficients h _4x may be uniformly differentiated or non-uniformly split.
Then, the split filter coefficients are combined in a symmetric way to obtain the coefficients of the filters as branches, wherein:
h_1x_0＝h_4x_0+h_4x_1
h_1x_1＝h_4x_0－h_4x_1
h_1x_2＝h_4x_2+h_4x_3
h_1x_3＝h_4x_2－h_4x_3
correspondingly, the digital signals b are recorded as bf0, bf1, bf2 and bf3 after passing through the branch filters with the clock frequency clk _1x, and then the processes of combining and difference processing the bf0, bf1, bf2 and bf3 to obtain the digital signals b0, b1, b2 and b3 are as follows:
b0＝(bf0+bf1)/2
b1＝(bf0－bf1)/2
b2＝(bf2+bf3)/2
b3＝(bf2－bf3)/2
that is, in the FPGA-based signal interpolation method according to the embodiment of the present application, a prototype filter coefficient corresponding to the input digital signal is split into a first sub-filter coefficient, a second sub-filter coefficient, a third sub-filter coefficient, and a fourth sub-filter coefficient; and the filter coefficients of the 4 FPGA-based digital filtering modules are respectively the sum of the first sub-filter coefficient and the second sub-filter coefficient, the difference between the first sub-filter coefficient and the second sub-filter coefficient, the sum of the third sub-filter coefficient and the fourth sub-filter coefficient, and the difference between the third sub-filter coefficient and the fourth sub-filter coefficient.
In the FPGA-based signal interpolation method, the 4 FPGA-based digital filtering modules obtain the first sub-digital signal, the second sub-digital signal, the third sub-digital signal and the fourth sub-digital signal after filtering; and the 4 processed digital signals are respectively the sum of the first sub-digital signal and the second sub-digital signal divided by two, the difference between the first sub-digital signal and the second sub-digital signal divided by two, the sum of the third sub-digital signal and the fourth sub-digital signal divided by two, and the difference between the third sub-digital signal and the fourth sub-digital signal divided by two.
In another example, the split filter coefficients are combined in another symmetric way to get the coefficients of the filters as branches, where:
h_1x_0＝h_4x_0+h_4x_2
h_1x_1＝h_4x_0－h_4x_2
h_1x_2＝h_4x_1+h_4x_3
h_1x_3＝h_4x_1－h_4x_3
correspondingly, the digital signals b are recorded as bf0, bf1, bf2 and bf3 after passing through the branch filters with the clock frequency clk _1x, and then the processes of combining and difference processing the bf0, bf1, bf2 and bf3 to obtain the digital signals b0, b1, b2 and b3 are as follows:
b0＝(bf0+bf1)/2
b1＝(bf2+bf3)/2
b2＝(bf0－bf1)/2
b3＝(bf2－bf3)/2
that is, in the FPGA-based signal interpolation method according to the embodiment of the present application, a prototype filter coefficient corresponding to the input digital signal is split into a first sub-filter coefficient, a second sub-filter coefficient, a third sub-filter coefficient, and a fourth sub-filter coefficient; and the filter coefficients of the 4 FPGA-based digital filtering modules are respectively the sum of the first sub-filter coefficient and the third sub-filter coefficient, the difference between the first sub-filter coefficient and the third sub-filter coefficient, the sum of the second sub-filter coefficient and the fourth sub-filter coefficient, and the difference between the second sub-filter coefficient and the fourth sub-filter coefficient.
In the signal interpolation method based on the FPGA, the 4 FPGA-based digital filtering modules are used for obtaining a first sub-digital signal, a second sub-digital signal, a third sub-digital signal and a fourth sub-digital signal after filtering; and the 4 processed digital signals are respectively the sum of the first sub-digital signal and the second sub-digital signal divided by two, the difference between the third sub-digital signal and the fourth sub-digital signal divided by two, the difference between the first sub-digital signal and the second sub-digital signal divided by two, and the difference between the third sub-digital signal and the fourth sub-digital signal divided by two.
In a further example, the split filter coefficients are combined in a further symmetric way to get the coefficients of the filters as branches, wherein:
h_1x_0＝h_4x_0+h_4x_3
h_1x_1＝h_4x_0－h_4x_3
h_1x_2＝h_4x_1+h_4x_2
h_1x_3＝h_4x_1－h_4x_2
correspondingly, the digital signals b are recorded as bf0, bf1, bf2 and bf3 after passing through the branch filters with the clock frequency clk _1x, and then the processes of combining and difference processing the bf0, bf1, bf2 and bf3 to obtain the digital signals b0, b1, b2 and b3 are as follows:
b0＝(bf0+bf1)/2
b1＝(bf2+bf3)/2
b2＝(bf2－bf3)/2
b3＝(bf0－bf1)/2
that is, in the FPGA-based signal interpolation method according to the embodiment of the present application, a prototype filter coefficient corresponding to the input digital signal is split into a first sub-filter coefficient, a second sub-filter coefficient, a third sub-filter coefficient, and a fourth sub-filter coefficient; and the filter coefficients of the 4 FPGA-based digital filtering modules are respectively the sum of the first sub-filter coefficient and the fourth sub-filter coefficient, the difference between the first sub-filter coefficient and the fourth sub-filter coefficient, the sum of the second sub-filter coefficient and the third sub-filter coefficient, and the difference between the second sub-filter coefficient and the third sub-filter coefficient.
In the FPGA-based signal interpolation method, the 4 FPGA-based digital filtering modules obtain the first sub-digital signal, the second sub-digital signal, the third sub-digital signal and the fourth sub-digital signal after filtering; and the 4 processed digital signals are respectively the sum of the first sub-digital signal and the second sub-digital signal divided by two, the sum of the third sub-digital signal and the fourth sub-digital signal divided by two, the difference between the third sub-digital signal and the fourth sub-digital signal divided by two, and the difference between the first sub-digital signal and the second sub-digital signal divided by two.
Here, it can be understood by those skilled in the art that, although the FPGA-based signal interpolation method according to the embodiment of the present application is described above by taking 4-fold interpolation as an example, the present application may also be applied to other even-fold interpolation, such as 6-fold interpolation, 8-fold interpolation, etc., and only the serial-parallel conversion circuit number of the FPGA needs to be changed accordingly.
FIG. 5 illustrates a flow chart of an FPGA-based signal acquisition and playback method according to an embodiment of the present application.
As shown in fig. 5, the FPGA-based signal acquisition and playback method according to the embodiment of the present application includes: step S210, collecting analog signals and carrying out analog-to-digital conversion on the analog signals to obtain input digital signals; step S220, interpolating the digital signal by the signal interpolation method based on the FPGA to obtain an interpolated digital signal; and step S230, performing digital-to-analog conversion on the interpolated digital signal to obtain an analog signal for playback.
Also, fig. 6 illustrates a schematic diagram of a processing architecture of N-fold interpolation of the FPGA-based signal acquisition and playback method according to an embodiment of the present application.
As shown in fig. 6, an analog signal a is obtained first, then analog-to-digital conversion is performed to obtain a digital signal b, and then the digital signal b output by the analog-to-digital converter is copied by the data copying module by N;
then, the data filtering module sends the copied N parts of digital signals b to the N paths of digital filtering modules respectively to obtain digital signals bf0, bf1, … … and bfN-1;
then, the data post-processing module performs post-processing operation on bf0, bf1, … … and bfN-1 to obtain digital signals b0, b1, … … and bN-1;
then, the parallel-serial conversion module performs parallel-serial conversion on the N-channel processed signals to obtain a digital signal c, and performs digital-to-analog conversion to obtain an analog signal d.
Here, as can be understood by those skilled in the art, other details of the FPGA-based signal acquisition and playback method according to the embodiment of the present application are completely the same as those of the FPGA-based signal interpolation method according to the embodiment of the present application described previously, and are not described again to avoid redundancy.
Illustrative electronic device
Next, an electronic apparatus according to an embodiment of the present application is described with reference to fig. 7.
FIG. 7 illustrates a block diagram of an electronic device in accordance with an embodiment of the present application.
As shown in fig. 7, the electronic device 10 includes one or more processors 11 and memory 12.
The processor 11 may be a Central Processing Unit (CPU) or other form of processing unit having data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.
In one example, the electronic device 10 may further include: an input device 13 and an output device 14, which are interconnected by a bus system and/or other form of connection mechanism (not shown).
The input device 13 may be, for example, a keyboard, a mouse, or the like.
The output device 14 may output various information including an interpolated digital signal, or an analog signal for playback, or the like to the outside. The output devices 14 may include, for example, a display, speakers, a printer, and a communication network and its connected remote output devices, among others.
Of course, for simplicity, only some of the components of the electronic device 10 relevant to the present application are shown in fig. 7, and components such as buses, input/output interfaces, and the like are omitted. In addition, the electronic device 10 may include any other suitable components depending on the particular application.
Illustrative computer program product
In addition to the above-described methods and apparatus, embodiments of the present application may also be a computer program product comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps of the FPGA-based signal interpolation method and the signal acquisition and playback method according to the various embodiments of the present application described in the "exemplary methods" section above of this specification.
The computer program product may be written with program code for performing the operations of embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as "r" or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.
Furthermore, embodiments of the present application may also be a computer-readable storage medium having stored thereon computer program instructions, which, when executed by a processor, cause the processor to perform the steps of the FPGA-based signal interpolation method and the signal acquisition and playback method according to various embodiments of the present application, described in the "exemplary methods" section above in this specification.
The computer-readable storage medium may take any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The foregoing describes the general principles of the present application in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present application are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the foregoing disclosure is not intended to be exhaustive or to limit the disclosure to the precise details disclosed.
The block diagrams of devices, apparatuses, systems referred to in this application are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".
It should also be noted that in the devices, apparatuses, and methods of the present application, the components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered as equivalents of the present application.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the application to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (11)
1. A signal interpolation method based on FPGA is characterized by comprising the following steps:
acquiring an input digital signal;
copying the input digital signal into N digital signals and inputting the N digital signals into N FPGA-based digital filtering modules, wherein N is an even number, and the N FPGA-based digital filtering modules are constructed in a manner that the filter coefficients of every two filters are symmetrically constructed;
merging and carrying out difference value processing on the N filtered digital signals according to every two filters with symmetrical filter coefficients to obtain N processed digital signals; and
the N processed digital signals are parallel-to-serial converted to obtain interpolated digital signals.
2. The FPGA-based signal interpolation method of claim 1, wherein N-4.
3. The FPGA-based signal interpolation method of claim 2,
splitting a prototype filter coefficient corresponding to the input digital signal into a first sub-filter coefficient, a second sub-filter coefficient, a third sub-filter coefficient, and a fourth sub-filter coefficient; and
the filter coefficients of the 4 FPGA-based digital filtering modules are respectively the sum of the first sub-filter coefficient and the second sub-filter coefficient, the difference between the first sub-filter coefficient and the second sub-filter coefficient, the sum of the third sub-filter coefficient and the fourth sub-filter coefficient, and the difference between the third sub-filter coefficient and the fourth sub-filter coefficient.
4. The FPGA-based signal interpolation method of claim 3, wherein,
obtaining the filtered first sub-digital signal, second sub-digital signal, third sub-digital signal and fourth sub-digital signal through the 4 FPGA-based digital filtering modules; and
the 4 processed digital signals are respectively the sum of the first sub-digital signal and the second sub-digital signal divided by two, the difference between the first sub-digital signal and the second sub-digital signal divided by two, the sum of the third sub-digital signal and the fourth sub-digital signal divided by two, and the difference between the third sub-digital signal and the fourth sub-digital signal divided by two.
5. The FPGA-based signal interpolation method of claim 2,
splitting a prototype filter coefficient corresponding to the input digital signal into a first sub-filter coefficient, a second sub-filter coefficient, a third sub-filter coefficient, and a fourth sub-filter coefficient; and
the filter coefficients of the 4 FPGA-based digital filtering modules are respectively the sum of the first sub-filter coefficient and the third sub-filter coefficient, the difference between the first sub-filter coefficient and the third sub-filter coefficient, the sum of the second sub-filter coefficient and the fourth sub-filter coefficient, and the difference between the second sub-filter coefficient and the fourth sub-filter coefficient.
6. The FPGA-based signal interpolation method of claim 5, wherein,
obtaining the filtered first sub-digital signal, second sub-digital signal, third sub-digital signal and fourth sub-digital signal through the 4 FPGA-based digital filtering modules; and
the 4 processed digital signals are respectively the sum of the first sub-digital signal and the second sub-digital signal divided by two, the difference between the third sub-digital signal and the fourth sub-digital signal divided by two, the difference between the first sub-digital signal and the second sub-digital signal divided by two, and the difference between the third sub-digital signal and the fourth sub-digital signal divided by two.
7. The FPGA-based signal interpolation method of claim 2,
splitting a prototype filter coefficient corresponding to the input digital signal into a first sub-filter coefficient, a second sub-filter coefficient, a third sub-filter coefficient, and a fourth sub-filter coefficient; and
the filter coefficients of the 4 FPGA-based digital filtering modules are respectively the sum of the first sub-filter coefficient and the fourth sub-filter coefficient, the difference between the first sub-filter coefficient and the fourth sub-filter coefficient, the sum of the second sub-filter coefficient and the third sub-filter coefficient, and the difference between the second sub-filter coefficient and the third sub-filter coefficient.
8. The FPGA-based signal interpolation method of claim 7,
obtaining the filtered first sub-digital signal, second sub-digital signal, third sub-digital signal and fourth sub-digital signal through the 4 FPGA-based digital filtering modules; and
the 4 processed digital signals are respectively the sum of the first sub-digital signal and the second sub-digital signal divided by two, the sum of the third sub-digital signal and the fourth sub-digital signal divided by two, the difference between the third sub-digital signal and the fourth sub-digital signal divided by two, and the difference between the first sub-digital signal and the second sub-digital signal divided by two.
9. A signal acquisition and playback method based on FPGA is characterized by comprising the following steps:
collecting an analog signal and carrying out analog-to-digital conversion on the analog signal to obtain an input digital signal;
interpolating the digital signal by the FPGA-based signal interpolation method according to any one of claims 1 to 8 to obtain an interpolated digital signal; and
and D/A converting the interpolated digital signal to obtain an analog signal for playback.
10. An electronic device, comprising:
a processor; and the number of the first and second groups,
a memory having stored therein computer program instructions which, when executed by the processor, cause the processor to perform the FPGA-based signal interpolation method of any one of claims 1 to 8 or the FPGA-based signal acquisition and playback method of claim 9.
11. A computer readable storage medium having stored thereon computer program instructions operable, when executed by a computing device, to perform an FPGA-based signal interpolation method according to any one of claims 1 to 8 or an FPGA-based signal acquisition and playback method according to claim 9.
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