CN112885934B - LED chip preparation method for improving product yield - Google Patents
LED chip preparation method for improving product yield Download PDFInfo
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- CN112885934B CN112885934B CN201911201871.9A CN201911201871A CN112885934B CN 112885934 B CN112885934 B CN 112885934B CN 201911201871 A CN201911201871 A CN 201911201871A CN 112885934 B CN112885934 B CN 112885934B
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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Abstract
The embodiment of the invention discloses an improvementThe preparation method of the LED chip with the product yield comprises the following steps: manufacturing a GaAs epitaxial wafer; manufacturing a photoresist mask pattern on the GaAs epitaxial wafer, and corroding GaP to form an exposed region; depositing a layer of SiO on the exposed region2；SiO2Corroding; depositing a ZnO film; zn diffusion; removing the ZnO film; annealing; removal of SiO2(ii) a ITO film evaporation, P-surface metal electrode manufacturing and N-surface metal electrode manufacturing. In the preparation process of the LED chip, after Zn diffusion and RTP high-temperature treatment are carried out on the surface of the wafer, the surface of the epitaxial wafer presents a rectangular pyramid rough surface, so that the external light emitting efficiency is increased, the brightness of the product is improved, and the yield of the product is improved. The process method is simple to operate, low in cost and suitable for manufacturing the positive GaAs-based LED chip.
Description
Technical Field
The invention relates to the technical field of semiconductor light-emitting diode chip manufacturing, in particular to a method for preparing an LED chip capable of improving the yield of products.
Background
The traditional incandescent lamp has high energy consumption and short service life, is forbidden by governments of various countries to produce nowadays when global resources are in short supply, and then the substitute product is an electronic energy-saving lamp. Although the electronic energy-saving lamp improves the energy-saving effect, the electronic energy-saving lamp is contrary to the great trend of environmental protection because a plurality of heavy metal elements polluting the environment are used. With the rapid development of LED technology, LED lighting is gradually becoming a good choice for new green lighting. The LED is a semiconductor device which utilizes the composite luminescence of current carriers, and the LED chip has the advantages of low power consumption, pure chromaticity, long service life, small volume, quick response time, energy conservation, environmental protection and the like, and is widely applied to illumination, display screens, traffic signal lamps, automobile lamps and special illuminating lamps. The preferred GaAs substrate material of the AlGaInP light-emitting diode has stable chemical property, and has the advantages of good lattice matching with the AlGaInP material, good electrical conductivity and thermal conductivity, high quality of manufactured crystal, low manufacturing cost in large batch, and the like. The LED chip is typically formed by further processing the LED epitaxial wafer. The LED epitaxial wafer generally includes a base substrate and an epitaxial layer formed on the base substrate. In the process of forming the LED chip through the LED epitaxial wafer, the epitaxial layer on the LED epitaxial wafer needs to be etched to form an epitaxial layer pattern with a shape and a size required for the LED chip.
The current LED has a problem of low external quantum efficiency, so that increasing the external quantum efficiency of the LED chip becomes a problem to be solved by those skilled in the art. The traditional AlGaInP light-emitting diode with the vertical structure carries out transverse expansion by a thick P-GaP current expansion layer and then injects current into a light-emitting region, but because the P-GaP current expansion capability is limited, the current density of a region near the lower part of an electrode is higher, and the current density of a region far away from the electrode is lower, the integral current injection efficiency is lower, and the light-emitting efficiency of the light-emitting diode is reduced. The AlGaInP light-emitting diode can improve the light-emitting efficiency by adopting a bonding process, but the AlGaInP light-emitting diode has the disadvantages of complicated steps, complex process, overhigh cost and overlow yield.
The patterned AlGaInP chip surface layer can reduce total reflection of light and increase the light-emitting efficiency of the chip, and the main method at present utilizes a nano-imprint technology or focused ion beam etching to form small holes on the surface at any time so as to improve the light extraction efficiency, but the equipment investment cost is higher in the earlier stage of the process.
Disclosure of Invention
The embodiment of the invention provides a method for preparing an LED chip for improving the product yield, which aims to solve the problems of low light-emitting efficiency and high preparation cost of the conventional LED chip.
In order to solve the technical problem, the embodiment of the invention discloses the following technical scheme:
the invention provides a preparation method of an LED chip for improving the product yield, which comprises the following steps:
s1, manufacturing a GaAs epitaxial wafer;
s2, manufacturing a photoresist mask pattern on the GaAs epitaxial wafer, and corroding GaP to form an exposed area;
s3, depositing a layer of SiO on the exposed area2；
S4 in the SiO2Etching the mask patternEtching SiO2 to form exposed area;
s5, depositing a ZnO film on the surface of the epitaxial wafer obtained in the step S4;
s6, placing the epitaxial wafer deposited with the ZnO film in a furnace tube for Zn diffusion treatment;
s7, removing ZnO on the surface of the epitaxial wafer after the diffusion treatment;
s8, carrying out high-temperature annealing treatment on the epitaxial wafer with the ZnO removed;
s9, annealing the SiO on the surface of the epitaxial wafer2Removing;
s10, evaporating an ITO film on the surface of the epitaxial wafer with the SiO2 removed;
s11, manufacturing a photoresist mask pattern on the surface of the wafer on which the ITO film grows, and manufacturing a P-surface electrode through evaporation and stripping processes;
and S12, thinning the substrate, and evaporating an N-surface metal electrode on the back surface of the thinned wafer.
Further, the GaAs epitaxial wafer in step S1 includes a GaAs substrate layer, a GaAs buffer layer, an n-AlGaInP confinement layer, a multiple quantum well active layer, a p-AlGaInP confinement layer, and a dual-layer highly doped p-GaP window layer, which are sequentially disposed from bottom to top.
Further, the exposed region penetrates the first p-GaP window layer to the second p-GaP window layer in step S2.
Further, in the step S5, the deposition of the ZnO film adopts magnetron sputtering or electron beam evaporation deposition, the evaporation pressure is 2.0E-6Torr, and the operation temperature of the cavity is normal temperature; the evaporation rate of the ZnO film is 1-15 angstroms/second, and the evaporation thickness is 30-150 angstroms.
Further, the temperature of the Zn diffusion furnace tube in step S6 is 300-450 ℃, the diffusion time is 5-15min, and the nitrogen flow in the furnace tube is 2-30 sccm/min.
Further, in step S7, ZnO is removed by hydrochloric acid solution etching, and hydrochloric acid solution with a concentration of 36-38% is used, and the etching time is 5 min.
Further, the annealing temperature in step S8 is 500-1000 ℃, the annealing time is 10-60min, and the flow rate of nitrogen in the annealing furnace is 2-30 sccm.
Further, the SiO on the surface is removed by BOE solution in step S92。
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
in the preparation process of the LED chip, Zn diffusion is carried out on the surface of a wafer, and after RTP high-temperature treatment, the surface of an epitaxial wafer presents a rectangular pyramid coarsening surface, so that the external light emitting efficiency is increased, the brightness of a product is improved, and the yield of the product is improved. The process method is simple to operate, low in cost and suitable for manufacturing the positive GaAs-based LED chip.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of the production process of the present invention;
FIG. 2 is a schematic structural diagram of the GaAs epitaxial wafer of step S1 according to the present invention;
FIG. 3 is a schematic diagram of a wafer structure with a bare area formed in step S2 according to the present invention;
FIG. 4 is a schematic diagram of the structure of the wafer roughened in step S8 according to the present invention;
FIG. 5 is an SEM image of the roughened surface formed in step S8;
FIG. 6 is a schematic diagram of the wafer structure formed after step S12.
In the figure, a GaAs substrate layer 1, a GaAs buffer layer 2, a 3N-AlGaInP limiting layer, a 4 multi-quantum well active layer, a 5P-AlGaInP limiting layer, a 6 double-layer high-doped GaP window layer, a 61 exposed region, a 7 roughened surface, an 8ITO film, a 9P surface electrode and a 10N surface electrode are arranged.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
As shown in fig. 1, the method for manufacturing an LED chip of the present invention for improving the yield of products includes the following steps:
s1, manufacturing a GaAs epitaxial wafer;
s2, manufacturing a photoresist mask pattern on the GaAs epitaxial wafer, and corroding GaP to form an exposed area;
s3, depositing a layer of SiO on the exposed area2；
S4 in the SiO2Making a photoresist mask pattern, and corroding SiO2 to form an exposed area;
s5, depositing a ZnO film on the surface of the epitaxial wafer obtained in the step S4;
s6, placing the epitaxial wafer deposited with the ZnO film in a furnace tube for Zn diffusion treatment;
s7, removing ZnO on the surface of the epitaxial wafer after diffusion treatment;
s8, carrying out high-temperature annealing treatment on the epitaxial wafer with the ZnO removed;
s9, annealing the SiO on the surface of the epitaxial wafer2Removing;
s10, evaporating an ITO film on the surface of the epitaxial wafer with the SiO2 removed;
s11, forming a photoresist mask pattern on the surface of the wafer on which the ITO film grows, and forming a P-surface electrode through evaporation and stripping processes;
and S12, thinning the substrate, and evaporating an N-surface metal electrode on the back surface of the thinned wafer.
As shown in fig. 2, the GaAs epitaxial wafer in step S1 includes a GaAs substrate layer 1, a GaAs buffer layer 2, an n-AlGaInP confinement layer 3, a multiple quantum well active layer 4, a p-AlGaInP confinement layer 5, and a bilayer highly doped p-GaP window layer 6, which are sequentially distributed from bottom to top.
As shown in fig. 3, in step S2, the exposed region 61 penetrates through the first p-GaP window layer to the second p-GaP window layer.
SiO deposited in step S32The area is slightly larger than the bare area formed in step S2.
In step S5, depositing a ZnO film on the surface of the whole wafer, wherein the deposition of the ZnO film adopts magnetron sputtering or electron beam evaporation deposition, the evaporation pressure is 2.0E-6Torr, and the operation temperature of the cavity is normal temperature; the evaporation rate of the ZnO film is 1-15 angstroms/second, and the evaporation thickness is 30-150 angstroms.
In step S6, the temperature of the Zn diffusion furnace is 300-450 ℃, the diffusion time is 5-15min, and the nitrogen flow in the furnace is 2-30 sccm/min. The Zn diffusion furnace tube adopts RTP 329-SA. At high temperature, metal atoms move to actively fill the material gaps. The nitrogen mainly plays a role in protection, prevents oxygen from entering the oxygen to oxidize metal at high temperature to form metal oxide, and reduces the conductivity.
In step S7, ZnO is removed by hydrochloric acid solution corrosion, hydrochloric acid solution with concentration of 36-38% is adopted, and the corrosion time is 5 min.
As shown in fig. 4 and 5, after steps S5-S8, a rectangular pyramid roughened surface 7 is formed on the wafer surface. Due to the SiO deposited in step S32The area is slightly larger than the bare area formed in step S2. Thus, in FIG. 4, there is a portion of the dual highly doped p-GaP window layer 6 that is not roughened. Step S8 is carried out in an RTP annealing furnace, wherein the annealing temperature is 500-1000 ℃, the annealing time is 10-60min, and the flow rate of nitrogen in the annealing furnace is 2-30 sccm.
In step S9, SiO2 on the surface is removed by BOE solution. The BOE solution is Buffered Oxide Etch and Buffered Oxide etching solution. Is prepared by mixing hydrofluoric acid (49%) with water or ammonium fluoride with water.
After the operations of steps S10-S11, the ITO film 8, the P-side electrode 9, and the N-side electrode 10 are formed, respectively, to obtain a wafer as shown in fig. 6. The evaporation of the ITO film, the manufacture of the P-surface metal electrode and the N-surface metal electrode are realized only by adopting a preparation mode.
Examples of specific embodiments are:
example 1
Step S1 provides a GaAs epitaxial wafer, which comprises a GaAs substrate, a GaAs buffer layer, an n-AlGaInP limiting layer, a multi-quantum well active layer, a p-AlGaInP limiting layer and a double-layer highly doped p-GaP window layer.
Step S2 etching the p-GaP window layer: and manufacturing a photoresist mask pattern on the GaAs epitaxial wafer, and corroding the GaP to form an exposed region.
Step S3 SiO2Deposition: depositing a layer of SiO on the exposed region2。
Step S4 SiO2 etching: and manufacturing a photoresist mask pattern on the SiO2, and corroding the SiO2 to form an exposed area.
Step S5 ZnO film deposition: and (4) depositing a ZnO film on the epitaxial wafer in the step 4, wherein the thickness of the ZnO film is 30 angstroms, and the speed is 1 angstrom/second.
Step S6 Zn diffusion: and (3) placing the epitaxial wafer in the step (5) in a furnace tube for diffusion treatment, wherein the temperature is 300 ℃, the nitrogen flow is 2sccm, and the annealing time is 5 min.
And step S7 removing the ZnO film, namely, placing the epitaxial wafer in the hydrochloric acid solution to remove the epitaxial wafer in the step 6.
Step S8 annealing: and (3) placing the epitaxial wafer in the step (7) in an RTP for high-temperature annealing treatment, wherein the temperature is 500 ℃, the time is 10min, and the nitrogen flow is 2 sccm.
Step S9 removes SiO 2: the step 8 wafer was placed in a BOE solution to remove SiO 2.
Step S10 is to evaporate an ITO film, and the step 9 is to evaporate an ITO film on the epitaxial wafer.
Step S11P-side metal electrode: and (3) manufacturing a photoresist mask pattern on the surface of the wafer on which the ITO film layer grows, and manufacturing a P-surface electrode through evaporation and stripping processes.
Step S12N-face metal electrode: and thinning the wafer substrate, and evaporating an N-surface metal electrode on the back surface of the thinned wafer.
The die luminance obtained by the embodiment is 1200-1300mcd, which is improved by more than 10% compared with the luminance obtained by the normal process.
Example 2
Step S1 provides a GaAs epitaxial wafer, which comprises a GaAs substrate, a GaAs buffer layer, an n-AlGaInP limiting layer, a multi-quantum well active layer, a p-AlGaInP limiting layer and a double-layer highly doped p-GaP window layer.
Step S2 etching the p-GaP window layer: and manufacturing a photoresist mask pattern on the GaAs epitaxial wafer, and corroding the GaP to form an exposed region.
Step S3 SiO2 deposition: a layer of SiO2 was deposited on the bare areas.
Step S4 SiO2 etching: and manufacturing a photoresist mask pattern on the SiO2, and corroding the SiO2 to form an exposed area.
Step S5 ZnO film deposition: a layer of ZnO was deposited on the epitaxial wafer at a thickness of 150 a at a rate of 15 a/sec in step 4.
Step S6 Zn diffusion: and (3) placing the epitaxial wafer in the step (5) in a furnace tube for diffusion treatment, wherein the temperature is 450 ℃, the nitrogen flow is 30sccm, and the annealing time is 15 min.
And step S7 removing the ZnO film, namely, placing the epitaxial wafer in the hydrochloric acid solution to remove the epitaxial wafer in the step 6.
Step S8 annealing: and (3) placing the epitaxial wafer in the step (7) in an RTP for high-temperature annealing treatment, wherein the temperature is 1000 ℃, the time is 60min, and the nitrogen flow is 30 sccm.
Step S9 removes SiO 2: the step 8 wafer was placed in a BOE solution to remove SiO 2.
Step S10 ITO film evaporation, namely evaporating an ITO film on the epitaxial wafer in the step 9
Step S11P-side metal electrode: making photoresist mask pattern on the surface of the wafer with ITO film layer, and making P-face electrode by evaporation and stripping
Step S12N-face metal electrode: and thinning the wafer substrate, and evaporating an N-surface metal electrode on the back surface of the thinned wafer.
The brightness of the tube core obtained by the embodiment is 1200-1300mcd, and is improved by more than 10% compared with the normal process brightness.
The foregoing is only a preferred embodiment of the present invention, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the invention, and such modifications and improvements are also considered to be within the scope of the invention.
Claims (7)
1. A method for preparing an LED chip for improving the product yield is characterized by comprising the following steps:
s1, manufacturing a GaAs epitaxial wafer, wherein the GaAs epitaxial wafer comprises a GaAs substrate layer, a GaAs buffer layer, an n-AlGaInP limiting layer, a multi-quantum well active layer, a p-AlGaInP limiting layer and a double-layer highly doped p-GaP window layer which are sequentially distributed from bottom to top;
s2, manufacturing a photoresist mask pattern on the GaAs epitaxial wafer, and corroding GaP to form an exposed area;
s3, depositing a layer of SiO on the exposed area2；
S4 in the SiO2Etching SiO by making photoresist mask pattern2Forming an exposed area;
s5, depositing a ZnO film on the surface of the epitaxial wafer obtained in the step S4;
s6, placing the epitaxial wafer deposited with the ZnO film in a furnace tube for Zn diffusion treatment;
s7, removing ZnO on the surface of the epitaxial wafer after diffusion treatment;
s8, carrying out high-temperature annealing treatment on the epitaxial wafer with the ZnO removed;
s9, annealing the SiO on the surface of the epitaxial wafer2Removing, removing SiO2SiO for the resist mask in step S42；
S10, removing SiO2Evaporating an ITO film on the surface of the epitaxial wafer;
s11, forming a photoresist mask pattern on the surface of the wafer on which the ITO film grows, and forming a P-surface electrode through evaporation and stripping processes;
and S12, thinning the substrate, and evaporating an N-surface metal electrode on the back surface of the thinned wafer.
2. The method of claim 1, wherein the exposed region penetrates the p-GaP window layer from the first layer to the p-GaP window layer in step S2.
3. The method for preparing LED chips according to claim 1, wherein the ZnO film deposition in step S5 is performed by magnetron sputtering or electron beam evaporation, the evaporation pressure is 2.0E-6Torr, and the chamber operation temperature is normal temperature; the evaporation rate of the ZnO film is 1-15 angstroms/second, and the evaporation thickness is 30-150 angstroms.
4. The method as claimed in claim 1, wherein the temperature of the Zn diffusion furnace tube in step S6 is 300-450 ℃, the diffusion time is 5-15min, and the flow rate of nitrogen in the furnace tube is 2-30 sccm/min.
5. The method as claimed in claim 1, wherein the step S7 is performed by removing ZnO through hydrochloric acid etching, wherein a hydrochloric acid solution with a concentration of 36-38% is used, and the etching time is 5 min.
6. The method as claimed in claim 1, wherein the annealing temperature in step S8 is 500-1000 ℃, the annealing time is 10-60min, and the flow rate of nitrogen in the annealing furnace is 2-30 sccm.
7. The method as claimed in claim 1, wherein the step of removing SiO on the surface of the LED chip by BOE solution in step S92。
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000091254A (en) * | 1998-09-11 | 2000-03-31 | Oki Electric Ind Co Ltd | METHOD FOR DIFFUSING SOLID PHASE OF Zn AND LIGHT EMITTING ELEMENT USING THE SAME |
| JP2005064113A (en) * | 2003-08-08 | 2005-03-10 | Hitachi Cable Ltd | Semiconductor light emitting element and its manufacturing method |
| JP2006147635A (en) * | 2004-11-16 | 2006-06-08 | Sumitomo Electric Ind Ltd | Method of manufacturing photo diode |
| CN1941435A (en) * | 2005-09-26 | 2007-04-04 | 日立电线株式会社 | Epitaxial wafer for led and light emitting diode |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000091254A (en) * | 1998-09-11 | 2000-03-31 | Oki Electric Ind Co Ltd | METHOD FOR DIFFUSING SOLID PHASE OF Zn AND LIGHT EMITTING ELEMENT USING THE SAME |
| JP2005064113A (en) * | 2003-08-08 | 2005-03-10 | Hitachi Cable Ltd | Semiconductor light emitting element and its manufacturing method |
| JP2006147635A (en) * | 2004-11-16 | 2006-06-08 | Sumitomo Electric Ind Ltd | Method of manufacturing photo diode |
| CN1941435A (en) * | 2005-09-26 | 2007-04-04 | 日立电线株式会社 | Epitaxial wafer for led and light emitting diode |
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