CN112885864B - CMOS image sensor and method of manufacturing the same - Google Patents
CMOS image sensor and method of manufacturing the same Download PDFInfo
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- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
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Abstract
The invention discloses a CMOS image sensor.A deep hole is formed on a semiconductor substrate in a forming area of a photodiode, and the semiconductor substrate is doped in a P type. And a first P-type epitaxial layer is formed on the inner side surface of the deep hole, and a second N-type epitaxial layer is filled in the deep hole in which the first P-type epitaxial layer is formed. The N-type region of the photodiode consists of a second N-type epitaxial layer, and the P-type region of the photodiode consists of a first P-type epitaxial layer at the bottom of the N-type region and a semiconductor substrate. The deep hole is set according to the depth requirement value of the depletion region when the photodiode is reversely biased so as to realize longitudinal size expansion of the photodiode. The first P-type epitaxial layer is in lateral contact with an N-type region of the photodiode to reduce lateral dark current of the photodiode. The invention also discloses a manufacturing method of the CMOS image sensor. The invention can realize the accurate adjustment of the depth of the reverse bias depletion region of the photodiode and further can well expand the longitudinal dimension of the photodiode.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a CMOS Image Sensor (CIS). The invention also relates to a manufacturing method of the CMOS image sensor.
Background
The conventional CMOS image sensor is composed of a Pixel (Pixel) unit circuit located in a Pixel area (Pixel area) and a CMOS circuit located in a Logic area (Logic area) for the Pixel (Pixel) unit circuit. Compared with a CCD image sensor, the CMOS image sensor has better integratability because of adopting a CMOS standard manufacturing process, can be integrated on the same chip with other digital-to-analog operation and control circuits, and is more suitable for future development.
The conventional CMOS image sensor is mainly classified into a 3T structure and a 4T structure according to the number of transistors included in a pixel unit circuit.
As shown in fig. 1, it is an equivalent circuit schematic diagram of a pixel unit circuit of a conventional 3T-type CMOS image sensor; the pixel unit circuit of the conventional 3T type CMOS image sensor includes a photodiode D1 and a CMOS pixel readout circuit. The CMOS pixel reading circuit is a 3T-type pixel circuit and comprises a reset tube M1, an amplifying tube M2 and a selecting tube M3 which are all NMOS tubes.
The N-type region of the photodiode D1 is connected with the source electrode of the reset tube M1.
The gate of the Reset tube M1 is connected to a Reset signal Reset, the Reset signal Reset is a potential pulse, and when the Reset signal Reset is at a high level, the Reset tube M1 is turned on and absorbs electrons of the photodiode D1 into the power supply Vdd of the readout circuit to realize Reset. When light irradiates, the photodiode D1 generates photo-generated electrons, the potential rises, and an electric signal is transmitted out through an amplifying circuit. The gate of the selection transistor M3 is connected to a row selection signal Rs for selecting the amplified electrical signal to be output, i.e., the output signal Vout.
As shown in fig. 2, it is an equivalent circuit schematic diagram of a pixel unit circuit of a conventional 4T-type CMOS image sensor; the difference from the structure shown in fig. 1 is that in the structure shown in fig. 2, one more transfer transistor or transfer transistor M4 is added, the source region of the transfer transistor M4 is an N-type region connected to the photodiode D1, the drain region of the transfer transistor M4 is a Floating Diffusion (FD), and the gate of the transfer transistor M4 is connected to a transfer control signal Tx. After photo-generated electrons are generated by the photodiode D1, the photo-generated electrons are transferred to the floating active region through the transfer transistor M4, and then the signal is amplified by connecting the floating active region to the gate of the amplifying tube M2.
As shown in fig. 3A, it is a top view of a pixel region of a conventional CMOS image sensor; FIG. 3B is a cross-sectional view taken along line AA in FIG. 3A; the pixel region is used for forming each pixel unit, each pixel unit comprises a photodiode and a CMOS pixel reading circuit, the photodiode is a key device for converting light into electricity, and the photodiode is formed by overlapping an N-type region 102 and a P-type region composed of a P-type semiconductor substrate 101 at the bottom. A P-type well 103 is also formed on the periphery side of the N-type region 102. The transistors for CMOS pixel read current are typically NMOS transistors, which are formed in a P-well 103. As shown in fig. 3A, the pixel units are arranged in an array structure.
The sensitivity of the CIS is strongly related to the size of the pixel region. After the photodiode is reset, the N-type region 102 is substantially depleted, light is absorbed in the depletion region to generate corresponding photo-generated electrons, and the depletion region also serves as a potential well for storing the photo-generated electrons. Therefore, the larger the depletion region formed by the N-type region 102 of the photodiode, the higher the absorption efficiency and sensitivity, and the larger the capacity of the potential well for storing photo-generated electrons, i.e., the capacity of the full well.
However, if the depletion region formed by the N-type region 102 of the photodiode is increased by increasing the lateral size of the N-type region 102 of the photodiode, the area occupied by the photodiode increases, which is not favorable for the size reduction of the CMOS image sensor.
Another approach is to increase the depletion region formed by the N-type region 102 of the photodiode by increasing the longitudinal dimension of the N-type region 102 of the photodiode, and thereby to increase the absorption efficiency and sensitivity and increase the full well capacity. Moreover, since the wavelengths of the light with different colors are different, the increase of the longitudinal dimension of the N-type region 102 is beneficial to the absorption of the light with long wavelength such as red light, thereby further improving the device performance.
In the conventional method, the N-type region 102 and the P-type well 103 are formed by photolithography definition and ion implantation, that is, the N-type region 102 and the P-type well 103 are both composed of ion implantation regions. The size of the N-type region 102 is limited by the aspect ratio of the photoresist in the photolithography process and the depth and concentration of the ion implantation, so that the reduction of the critical dimension of the N-type region 102 is limited and the increase of the longitudinal depth of the N-type region 102 is also limited, which is not favorable for the improvement of the performance of the CIS.
Disclosure of Invention
The invention aims to provide a CMOS image sensor which can realize accurate adjustment of the depth of a depletion region of a photodiode during reverse bias and further can well expand the longitudinal dimension of the photodiode. Therefore, the invention also provides a manufacturing method of the CMOS image sensor.
In order to solve the above technical problem, the present invention provides a CMOS image sensor, wherein a pixel region includes a plurality of pixel units, and each of the pixel units includes a photodiode.
And forming a deep hole on the semiconductor substrate in the forming region of the photodiode, wherein the semiconductor substrate is doped in a P type.
And forming a first P-type epitaxial layer on the inner side surface of the deep hole, and filling a second N-type epitaxial layer in the deep hole formed with the first P-type epitaxial layer.
The N-type region of the photodiode is composed of the second N-type epitaxial layer, and the P-type region of the photodiode is composed of the first P-type epitaxial layer at the bottom of the N-type region and the semiconductor substrate.
The deep hole is set according to the depth requirement value of the depletion region when the photodiode is reversely biased so as to realize longitudinal size expansion of the photodiode.
The first P-type epitaxial layer is in side contact with an N-type region of the photodiode to reduce side dark current of the photodiode.
The semiconductor substrate is a silicon substrate, the second N-type epitaxial layer is an N-type silicon epitaxial layer, and the first P-type epitaxial layer is a P-type silicon epitaxial layer.
The further improvement is that the key size of the deep hole is 0.5-2.0 microns, and the depth is 1-5 microns.
In a further improvement, the doping impurities of the second N type epitaxial layer comprise phosphorus or arsenic.
The further improvement is that the thickness of the first P-type epitaxial layer is 0.1-0.5 micron, and the doping impurities comprise boron.
In a further improvement, the shape of the deep hole comprises a square shape in a plane of top view.
In a further improvement, the pixel unit further comprises a CMOS pixel reading circuit for reading the photo-generated electrons of the photodiode.
In order to solve the above technical problem, in the manufacturing method of the CMOS image sensor provided by the present invention, the pixel region of the CMOS image sensor includes a plurality of pixel units, and each pixel unit includes a photodiode; the method comprises the following steps:
step one, etching the P-type doped semiconductor substrate to form a deep hole in the formation region of the photodiode.
The deep hole is set according to the depth requirement value of the depletion region when the photodiode is reversely biased so as to realize longitudinal size expansion of the photodiode.
And secondly, forming a first P-type epitaxial layer, wherein the first P-type epitaxial layer is formed on the side surface and the bottom surface of the deep hole.
And step three, forming a second N-type epitaxial layer to completely fill the deep hole.
The N-type region of the photodiode is composed of the second N-type epitaxial layer, and the P-type region of the photodiode is composed of the first P-type epitaxial layer at the bottom of the N-type region and the semiconductor substrate.
The first P-type epitaxial layer is in side contact with an N-type region of the photodiode to reduce side dark current of the photodiode.
The semiconductor substrate is a silicon substrate, the second N-type epitaxial layer is an N-type silicon epitaxial layer, and the first P-type epitaxial layer is a P-type silicon epitaxial layer.
The further improvement is that the key size of the deep hole is 0.5-2.0 microns, and the depth is 1-5 microns.
In a further improvement, the doping impurities of the second N type epitaxial layer comprise phosphorus or arsenic.
The further improvement is that the thickness of the first P-type epitaxial layer is 0.1-0.5 micron, and the doping impurities comprise boron.
In a further improvement, the shape of the deep hole comprises a square shape in a plane of top view.
The further improvement is that the step one comprises the following sub-steps:
forming a hard mask layer on the surface of the semiconductor substrate;
the hard mask layer is subjected to graphical definition to form a forming area of the deep hole;
and etching the semiconductor substrate by taking the hard mask layer as a mask to form the deep hole.
In the second step, the first P-type epitaxial layer is formed by adopting selective epitaxial growth;
in the third step, the second N-type epitaxial layer is formed by adopting selective epitaxial growth;
the third step further comprises the following steps:
and fourthly, leveling the top surfaces of the second N-type epitaxial layer and the first P-type epitaxial layer with the top surfaces of the deep holes by adopting a chemical mechanical grinding and back etching process, and removing the hard mask layer.
The further improvement is that in the step one, the etching process for forming the deep hole comprises dry etching or wet etching;
the fourth step comprises the following sub-steps:
performing first chemical mechanical polishing to level the top surfaces of the second N-type epitaxial layer and the first P-type epitaxial layer with the top surface of the hard mask layer;
removing the hard mask layer by dry etching or wet etching;
and carrying out second chemical mechanical polishing to enable the top surfaces of the second N-type epitaxial layer and the first P-type epitaxial layer to be flush with the top surfaces of the deep holes.
The further improvement is that the hard mask layer is the superposition of one or more layers of silicon oxide, silicon nitride and polysilicon, and the thickness of the hard mask layer is 100-800 nanometers.
The depth of the N-type region of the photodiode can be adjusted by directly adjusting the depth of the deep hole, and the N-type region of the photodiode is basically depleted to form a depletion region after the photodiode is reset, so the depth of the depletion region during reverse bias of the photodiode can be adjusted by adjusting the depth of the deep hole, and the depth of the deep hole can be accurately adjusted by an etching process, so the depth of the depletion region during reverse bias of the photodiode can be accurately adjusted, and the longitudinal dimension of the photodiode can be well expanded. The deeper the depletion region depth of the photodiode in reverse bias, the more the number of photo-generated electrons can be stored, so that the light absorption efficiency and the light sensitivity of the photodiode can be improved, and the light absorption efficiency and the light sensitivity of the photodiode can be maintained or improved under the condition of reducing the transverse size of the photodiode.
Drawings
The invention is described in further detail below with reference to the following figures and embodiments:
fig. 1 is an equivalent circuit schematic diagram of a pixel unit circuit of a conventional 3T-type CMOS image sensor;
fig. 2 is an equivalent circuit schematic diagram of a pixel unit circuit of a conventional 4T-type CMOS image sensor;
fig. 3A is a top view of a pixel region of a conventional CMOS image sensor;
FIG. 3B is a cross-sectional view taken along line AA in FIG. 3A;
FIG. 4 is a cross-sectional view of a device at a photodiode in a CMOS image sensor according to an embodiment of the present invention;
fig. 5A to 5G are cross-sectional structural views of devices at one photodiode in steps of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention.
Detailed Description
Fig. 4 is a cross-sectional view of a device at a photodiode in a CMOS image sensor according to an embodiment of the present invention; the pixel area of the CMOS image sensor comprises a plurality of pixel units, and each pixel unit comprises a photodiode.
A first P-type epitaxial layer 3 is formed on the inner side surface of the deep hole 2, and a second N-type epitaxial layer 4 is filled in the deep hole 2 formed with the first P-type epitaxial layer 3.
The N-type region of the photodiode is composed of the second N-type epitaxial layer 4, and the P-type region of the photodiode is composed of the first P-type epitaxial layer 3 at the bottom of the N-type region and the semiconductor substrate 1.
The deep hole 2 is set according to a depth requirement value of a depletion region when the photodiode is reversely biased so as to realize longitudinal dimension expansion of the photodiode.
The first P-type epitaxial layer 3 is in side contact with an N-type region of the photodiode to reduce side dark current of the photodiode.
In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate, the second N-type epitaxial layer 4 is an N-type silicon epitaxial layer, and the first P-type epitaxial layer 3 is a P-type silicon epitaxial layer.
The key size of the deep hole 2 is 0.5-2.0 microns, and the depth is 1-5 microns.
The doping impurities of the second N-type epitaxial layer 4 include phosphorus or arsenic.
The thickness of the first P-type epitaxial layer 3 is 0.1-0.5 micron, and the doping impurities comprise boron.
The shape of the deep hole 2 includes a square in a top view. The top-view structure of the deep hole 2 can also refer to the top-view structure of the N-type region 102 in fig. 3A. However, as can be seen from comparison with fig. 3B, the deep hole 2 according to the embodiment of the present invention is formed by an etching process, so that the longitudinal expansion capability of the deep hole 2, which can adjust the depth of the deep hole 2, is greater than the longitudinal expansion capability of the N-type region 102 paired with the ion implantation in fig. 3B, and therefore, the depth of the N-type region according to the embodiment of the present invention is deeper. Meanwhile, the N-type region of the embodiment of the present invention is directly composed of the second N-type epitaxial layer, and compared with the N-type region composed of the ion implantation region in fig. 3B, the N-type region of the embodiment of the present invention has more precise doping control and better doping quality, so that the device performance can be improved.
The pixel unit further comprises a CMOS pixel reading circuit for reading photo-generated electrons of the photodiode.
The number of transistors included in the CMOS pixel reading circuit is determined according to the type of an actual CMOS image sensor, for example: when the 3T CMOS image sensor shown in fig. 1 is used, the CMOS pixel readout circuit includes a reset transistor M1, an amplifying transistor M2, and a selection transistor M3, all of which are NMOS transistors. When the 4T-type CMOS image sensor shown in fig. 2 is used, the CMOS pixel reading circuit includes a reset transistor M1, an amplifying transistor M2, a selection transistor M3 and the transfer transistor 4, all of which are NMOS transistors; while the drain region of the transfer transistor 4 needs to be provided as a floating active region.
The NMOS transistor of the CMOS pixel read circuit needs to be formed in a P-well, typically formed in the top region of the semiconductor substrate 1 by ion implantation. In a top view, a forming region of the P-type well corresponding to each NMOS transistor and a forming region of the N-type region of the photodiode need to be defined by photolithography, and a cross-sectional view corresponding to fig. 4 only shows a cross-sectional view of the forming region of the N-type region of the photodiode. And the forming area of the P-type well corresponding to each NMOS tube and the forming area of the N-type area of the photodiode are formed in the same forming area of the pixel unit.
The N-type region of the photodiode in the embodiment of the invention is formed by adopting the second N-type epitaxial layer 4 filled in the deep hole 2, so that the thickness of the N-type region of the photodiode can be adjusted by directly adjusting the depth of the deep hole 2, and the N-type region of the photodiode is basically depleted to form a depletion region after the photodiode is reset, so that the depth of the depletion region in reverse bias of the photodiode can be adjusted by adjusting the depth of the deep hole 2, and the depth of the deep hole 2 can be accurately adjusted by an etching process, so that the depth of the depletion region in reverse bias of the photodiode can be accurately adjusted, and the longitudinal dimension of the photodiode can be well expanded. The deeper the depletion region depth of the photodiode in reverse bias, the more the number of photo-generated electrons can be stored, so that the light absorption efficiency and the light sensitivity of the photodiode can be improved, and therefore, the embodiment of the invention can keep or improve the light absorption efficiency and the light sensitivity of the photodiode under the condition of reducing the transverse size of the photodiode, so that the embodiment of the invention is beneficial to reducing the size of a pixel unit and improving the filling factor.
Fig. 5A to 5G are cross-sectional structural diagrams of devices at one photodiode in steps of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention. In the manufacturing method of the CMOS image sensor, the pixel area of the CMOS image sensor comprises a plurality of pixel units, and each pixel unit comprises a photodiode; the method comprises the following steps:
step one, etching the P-type doped semiconductor substrate 1 to form a deep hole 2 in a formation region of the photodiode. In the embodiment of the invention, the first step comprises the following sub-steps:
as shown in fig. 5A, a hard mask layer 201 is formed on the surface of the semiconductor substrate 1. The hard mask layer 201 is formed by stacking one or more layers of silicon oxide, silicon nitride and polycrystalline silicon, and the thickness of the hard mask layer 201 is 100-800 nanometers.
And patterning the hard mask layer 201 to define a formation region of the deep hole 2. Preferably, as shown in fig. 5B, a photolithography process is performed to form a pattern structure of the photoresist 202. As shown in fig. 5C, the photoresist 202 is used as a mask to transfer the pattern structure defined by the photoresist 202 into the hard mask layer 201.
As shown in fig. 5C, the semiconductor substrate 1 is etched by using the hard mask layer 201 as a mask to form the deep hole 2. The photoresist 202 is removed during or before or after etching the deep hole 2. The etching process for forming the deep hole 2 includes dry etching or wet etching.
The deep hole 2 is set according to a depth requirement value of a depletion region when the photodiode is reverse biased, so that the photodiode is longitudinally expanded.
The semiconductor substrate 1 is a silicon substrate. The subsequent second N-type epitaxial layer 4 is an N-type silicon epitaxial layer, and the first P-type epitaxial layer 3 is a P-type silicon epitaxial layer.
The key size of the deep hole 2 is 0.5-2.0 microns, and the depth is 1-5 microns.
The shape of the deep hole 2 includes a square in a top view.
Step two, as shown in fig. 5D, a first P-type epitaxial layer 3 is formed, and the first P-type epitaxial layer 3 is formed on the side surface and the bottom surface of the deep hole 2.
In the embodiment of the invention, the thickness of the first P-type epitaxial layer 3 is 0.1-0.5 micron, and the doping impurities comprise boron.
The first P-type epitaxial layer 3 is formed using selective epitaxial growth. Since the selective epitaxial process is only grown on the surface of the single crystal structure, the surface of the semiconductor substrate 1 exposed at the inner side surface of the deep hole 2 before the first P-type epitaxial layer 3 is grown is only the single crystal structure, and the surface of the hard mask layer 201 outside the deep hole 2 is not the single crystal structure, the first P-type epitaxial layer 3 is only grown at the inner side surface of the deep hole 2.
And step three, as shown in fig. 5E, forming a second N-type epitaxial layer 4 to completely fill the deep hole 2.
In an embodiment of the present invention, the doping impurities of the second N-type epitaxial layer 4 include phosphorus or arsenic.
The second N-type epitaxial layer 4 is formed using selective epitaxial growth. Therefore, the second N-type epitaxial layer 4 is also grown from the surface of the first P-type epitaxial layer 3, and is not grown on the surface of the hard mask layer 201 outside the deep hole 2. But after the growth is completed, the top surface of the second N-type epitaxial layer 4 may protrude above the surface of the hard mask layer 201. Therefore, the third step further comprises:
and fourthly, leveling the top surfaces of the second N-type epitaxial layer 4 and the first P-type epitaxial layer 3 with the top surfaces of the deep holes 2 by adopting chemical mechanical grinding and back etching processes, and removing the hard mask layer 201. The fourth step comprises the following sub-steps:
as shown in fig. 5F, a first chemical mechanical polishing is performed to level the top surfaces of the second N-type epitaxial layer 4 and the first P-type epitaxial layer 3 with the top surface of the hard mask layer 201.
As shown in fig. 5G, the hard mask layer 201 is removed by dry etching or wet etching.
As shown in fig. 4, a second chemical mechanical polishing is performed to level the top surfaces of the second N-type epitaxial layer 4 and the first P-type epitaxial layer 3 with the top surface of the deep hole 2.
The N-type region of the photodiode is composed of the second N-type epitaxial layer 4, and the P-type region of the photodiode is composed of the first P-type epitaxial layer 3 at the bottom of the N-type region and the semiconductor substrate 1.
The first P-type epitaxial layer 3 is in side contact with an N-type region of the photodiode to reduce side dark current of the photodiode.
And then, forming a CMOS pixel reading circuit of each pixel unit in the pixel area, wherein the CMOS pixel reading circuit is used for reading the photo-generated electrons of the photodiode.
The number of transistors included in the CMOS pixel reading circuit is determined according to the type of an actual CMOS image sensor, for example: when the 3T CMOS image sensor shown in fig. 1 is used, the CMOS pixel reading circuit includes a reset transistor M1, an amplifier transistor M2, and a selection transistor M3, which are all NMOS transistors. When the 4T-type CMOS image sensor shown in fig. 2 is used, the CMOS pixel reading circuit includes a reset transistor M1, an amplifying transistor M2, a selection transistor M3 and the transfer transistor 4, all of which are NMOS transistors; while the drain region of the transfer transistor 4 needs to be provided as a floating active region.
The NMOS transistor of the CMOS pixel readout circuit needs to be formed in a P-type well, which is typically formed in the top region of the semiconductor substrate 1 by ion implantation. In a top view, a forming region of the P-type well corresponding to each NMOS transistor and a forming region of the N-type region of the photodiode need to be defined by photolithography, and a cross-sectional view corresponding to fig. 4 only shows a cross-sectional view of the forming region of the N-type region of the photodiode. And the forming area of the P-type well corresponding to each NMOS tube and the forming area of the N-type area of the photodiode are formed in the same forming area of the pixel unit.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (16)
1. A CMOS image sensor is characterized in that a pixel area of the CMOS image sensor comprises a plurality of pixel units, and each pixel unit comprises a photodiode;
forming a deep hole on the semiconductor substrate in the forming area of the photodiode, wherein the semiconductor substrate is doped in a P type manner;
forming a first P-type epitaxial layer on the inner side surface of the deep hole, and filling a second N-type epitaxial layer in the deep hole with the first P-type epitaxial layer;
the N-type region of the photodiode consists of the second N-type epitaxial layer, and the P-type region of the photodiode consists of the first P-type epitaxial layer at the bottom of the N-type region and the semiconductor substrate;
the deep hole is set according to the depth requirement value of the depletion region when the photodiode is reversely biased so as to realize longitudinal size expansion of the photodiode;
the first P-type epitaxial layer is in side contact with an N-type region of the photodiode to reduce side dark current of the photodiode.
2. The CMOS image sensor of claim 1, wherein: the semiconductor substrate is a silicon substrate, the second N-type epitaxial layer is an N-type silicon epitaxial layer, and the first P-type epitaxial layer is a P-type silicon epitaxial layer.
3. The CMOS image sensor of claim 1 or 2, wherein: the key size of the deep hole is 0.5-2.0 microns, and the depth is 1-5 microns.
4. The CMOS image sensor of claim 1 or 2, wherein: the doping impurities of the second N-type epitaxial layer comprise phosphorus or arsenic.
5. The CMOS image sensor of claim 3, wherein: the thickness of the first P type epitaxial layer is 0.1-0.5 micron, and the doped impurities comprise boron.
6. The CMOS image sensor of claim 3, wherein: in a plane of top view, the shape of the deep hole comprises a square shape.
7. The CMOS image sensor of claim 1, wherein: the pixel unit further comprises a CMOS pixel reading circuit for reading photo-generated electrons of the photodiode.
8. A manufacturing method of a CMOS image sensor is characterized in that a pixel area of the CMOS image sensor comprises a plurality of pixel units, and each pixel unit comprises a photodiode; the method comprises the following steps:
etching a P-type doped semiconductor substrate to form a deep hole in a forming area of the photodiode;
the deep hole is set according to the depth requirement value of the depletion region when the photodiode is reversely biased so as to realize longitudinal size expansion of the photodiode;
step two, forming a first P-type epitaxial layer, wherein the first P-type epitaxial layer is formed on the side surface and the bottom surface of the deep hole;
step three, forming a second N-type epitaxial layer to completely fill the deep hole;
the N-type region of the photodiode consists of the second N-type epitaxial layer, and the P-type region of the photodiode consists of the first P-type epitaxial layer at the bottom of the N-type region and the semiconductor substrate;
the first P-type epitaxial layer is in side contact with an N-type region of the photodiode to reduce side dark current of the photodiode.
9. The method of manufacturing a CMOS image sensor according to claim 8, wherein: the semiconductor substrate is a silicon substrate, the second N-type epitaxial layer is an N-type silicon epitaxial layer, and the first P-type epitaxial layer is a P-type silicon epitaxial layer.
10. The method of manufacturing a CMOS image sensor according to claim 8 or 9, wherein: the key size of the deep hole is 0.5-2.0 microns, and the depth is 1-5 microns.
11. The method of manufacturing a CMOS image sensor according to claim 8 or 9, wherein: the doping impurities of the second N-type epitaxial layer comprise phosphorus or arsenic.
12. The method of manufacturing a CMOS image sensor according to claim 10, wherein: the thickness of the first P-type epitaxial layer is 0.1-0.5 microns, and the doping impurities comprise boron.
13. The method of manufacturing a CMOS image sensor according to claim 10, wherein: in a plane of top view, the shape of the deep hole comprises a square shape.
14. The method of manufacturing a CMOS image sensor according to claim 8, wherein: the first step comprises the following sub-steps:
forming a hard mask layer on the surface of the semiconductor substrate;
the hard mask layer is patterned to define a forming area of the deep hole;
etching the semiconductor substrate by taking the hard mask layer as a mask to form the deep hole;
in the second step, the first P-type epitaxial layer is formed by adopting selective epitaxial growth;
in the third step, the second N-type epitaxial layer is formed by adopting selective epitaxial growth;
the third step further comprises the following steps:
and fourthly, leveling the top surfaces of the second N-type epitaxial layer and the first P-type epitaxial layer and the top surfaces of the deep holes by adopting a chemical mechanical grinding and back etching process, and removing the hard mask layer.
15. The method of manufacturing a CMOS image sensor according to claim 14, wherein: in the first step, the etching process for forming the deep hole comprises dry etching or wet etching;
the fourth step comprises the following sub-steps:
performing first chemical mechanical polishing to enable the top surfaces of the second N-type epitaxial layer and the first P-type epitaxial layer to be flush with the top surface of the hard mask layer;
removing the hard mask layer by dry etching or wet etching;
and carrying out second chemical mechanical polishing to enable the top surfaces of the second N-type epitaxial layer and the first P-type epitaxial layer to be flush with the top surfaces of the deep holes.
16. The method of manufacturing a CMOS image sensor according to claim 14 or 15, wherein: the hard mask layer is formed by stacking one or more layers of silicon oxide, silicon nitride and polycrystalline silicon, and the thickness of the hard mask layer is 100-800 nanometers.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH07142757A (en) * | 1993-11-17 | 1995-06-02 | Fuji Electric Co Ltd | Manufacture of semiconductor light sensor |
| CN107910343A (en) * | 2017-12-11 | 2018-04-13 | 上海华力微电子有限公司 | Cmos image sensor and its manufacture method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07142757A (en) * | 1993-11-17 | 1995-06-02 | Fuji Electric Co Ltd | Manufacture of semiconductor light sensor |
| CN107910343A (en) * | 2017-12-11 | 2018-04-13 | 上海华力微电子有限公司 | Cmos image sensor and its manufacture method |
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