CN112885857B - CMOS image sensor and method of manufacturing the same - Google Patents

CMOS image sensor and method of manufacturing the same Download PDF

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CN112885857B
CN112885857B CN202110344986.4A CN202110344986A CN112885857B CN 112885857 B CN112885857 B CN 112885857B CN 202110344986 A CN202110344986 A CN 202110344986A CN 112885857 B CN112885857 B CN 112885857B
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CN112885857A (en
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陈广龙
李佳龙
范晓
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof

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Abstract

The invention discloses a CMOS image sensor.A deep groove isolation structure is isolated between photodiodes of pixel units in a pixel region; the deep groove penetrates through the N-type epitaxial layer, the first intrinsic epitaxial layer and the bottom and is located in the first P-type epitaxial layer, a second intrinsic epitaxial layer, a second P-type epitaxial layer and an amorphous silicon layer which is filled with the amorphous silicon layer and is surrounded by the first dielectric layer and the second dielectric layer are formed on the inner side surface of the deep groove, the top surface of the second dielectric layer on the top is lower than the top surface of the deep groove, and the third P-type epitaxial layer fills the deep groove region and is located above the N-type epitaxial layer; the N-type region of the photodiode is formed by overlapping an N-type epitaxial layer and an N-type ion implantation region with the top formed in a third P-type epitaxial layer. The invention also discloses a manufacturing method of the CMOS image sensor. The invention can well expand the longitudinal size of the photodiode and can improve the optical or electrical isolation between the photodiodes.

Description

CMOS image sensor and method of manufacturing the same
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a CMOS Image Sensor (CIS). The invention also relates to a manufacturing method of the CMOS image sensor.
Background
The conventional CMOS image sensor is composed of a Pixel (Pixel) unit circuit located in a Pixel area (Pixel area) and a CMOS circuit located in a Logic area (Logic area) for the Pixel (Pixel) unit circuit. Compared with the CCD image sensor, the CMOS image sensor has better integratability because of adopting a CMOS standard manufacturing process, can be integrated on the same chip with other digital-to-analog operation and control circuits, and is more suitable for future development.
The conventional CMOS image sensor is mainly classified into a 3T structure and a 4T structure according to the number of transistors included in a pixel unit circuit.
As shown in fig. 1, it is an equivalent circuit schematic diagram of a pixel unit circuit of a conventional 3T-type CMOS image sensor; the pixel unit circuit of the conventional 3T-type CMOS image sensor includes a photodiode D1 and a CMOS pixel readout circuit. The CMOS pixel reading circuit is a 3T-type pixel circuit and comprises a reset tube M1, an amplifying tube M2 and a selecting tube M3 which are all NMOS tubes.
The N-type region of the photodiode D1 is connected with the source electrode of the reset tube M1.
The gate of the Reset tube M1 is connected to a Reset signal Reset, the Reset signal Reset is a potential pulse, and when the Reset signal Reset is at a high level, the Reset tube M1 is turned on and absorbs electrons of the photodiode D1 into the power supply Vdd of the readout circuit to realize Reset. When light irradiates, the photodiode D1 generates photo-generated electrons, the potential rises, and an electric signal is transmitted out through an amplifying circuit. The gate of the selection transistor M3 is connected to a row selection signal Rs for selecting the amplified electrical signal to be output, i.e., the output signal Vout.
As shown in fig. 2, it is an equivalent circuit schematic diagram of a pixel unit circuit of a conventional 4T-type CMOS image sensor; the difference from the structure shown in fig. 1 is that in the structure shown in fig. 2, one more transfer transistor or transfer transistor M4 is added, the source region of the transfer transistor M4 is an N-type region connected to the photodiode D1, the drain region of the transfer transistor M4 is a Floating Diffusion (FD), and the gate of the transfer transistor M4 is connected to a transfer control signal Tx. After photo-generated electrons are generated by the photodiode D1, the photo-generated electrons are transferred to the floating active region through the transfer transistor M4, and then the signal is amplified by connecting the floating active region to the gate of the amplifying tube M2.
As shown in fig. 3A, it is a top view of a pixel region of a conventional CMOS image sensor; FIG. 3B is a cross-sectional view taken along line AA in FIG. 3A; the pixel region is used for forming each pixel unit, each pixel unit comprises a photodiode and a CMOS pixel reading circuit, the photodiode is a key device for converting light into electricity, and the photodiode is formed by overlapping an N-type region 102 and a P-type region composed of a P-type semiconductor substrate 101 at the bottom. A P-type well 103 is also formed on the periphery side of the N-type region 102. The transistors of the CMOS pixel read current are typically NMOS transistors, which are formed in a P-well 103. As shown in fig. 3A, the pixel units are arranged in an array structure.
The sensitivity of the CIS is strongly related to the size of the pixel region. After the photodiode is reset, the N-type region 102 is substantially depleted, light is absorbed in the depletion region to generate corresponding photo-generated electrons, and the depletion region also serves as a potential well for storing the photo-generated electrons. Therefore, the larger the depletion region formed by the N-type region 102 of the photodiode, the higher the absorption efficiency and sensitivity, and the larger the capacity of the potential well for storing photo-generated electrons, i.e., the capacity of the full well.
However, if the depletion region formed by the N-type region 102 of the photodiode is increased by increasing the lateral size of the N-type region 102 of the photodiode, the area occupied by the photodiode increases, which is not advantageous for the size reduction of the CMOS image sensor.
Another approach is to increase the depletion region formed by the N-type region 102 of the photodiode by increasing the longitudinal dimension of the N-type region 102 of the photodiode, and thereby to increase the absorption efficiency and sensitivity and increase the full well capacity. Moreover, since the wavelengths of the light with different colors are different, the increase of the longitudinal dimension of the N-type region 102 is beneficial to the absorption of the light with long wavelength such as red light, thereby further improving the device performance.
In the conventional method, the N-type region 102 and the P-type well 103 are formed by photolithography definition and ion implantation, that is, the N-type region 102 and the P-type well 103 are both composed of ion implantation regions. The size of the N-type region 102 is limited by the aspect ratio of the photoresist in the photolithography process and the depth and concentration of the ion implantation, so that the reduction of the critical dimension of the N-type region 102 is limited and the increase of the longitudinal depth of the N-type region 102 is also limited, which is not favorable for the improvement of the performance of the CIS.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a CMOS image sensor which can realize accurate adjustment of the depth of a depletion region when a photodiode is reverse-biased, thereby expanding the longitudinal dimension of the photodiode well and improving the optical or electrical isolation between the photodiodes. Therefore, the invention also provides a manufacturing method of the CMOS image sensor.
In order to solve the above technical problem, the pixel region of the CMOS image sensor provided by the present invention includes a plurality of pixel units, each of the pixel units includes a photodiode, and a deep trench isolation structure is isolated between the photodiodes.
The deep trench isolation structure is formed in a deep trench, the deep trench penetrates through an N-type epitaxial layer, a first intrinsic epitaxial layer and the bottom surface of the deep trench and enters a first P-type epitaxial layer, and the first P-type epitaxial layer, the first intrinsic epitaxial layer and the N-type epitaxial layer are sequentially overlapped on a P-type doped semiconductor substrate from bottom to top.
The second intrinsic epitaxial layer, the second P-type epitaxial layer and the first dielectric layer are sequentially overlapped on the inner side surface of the deep groove, the deep groove formed by the second intrinsic epitaxial layer, the second P-type epitaxial layer and the first dielectric layer is completely filled with the amorphous silicon layer, the top surface of the amorphous silicon layer is etched back to be lower than the top surface of the deep groove, the second dielectric layer is formed on the top surface of the amorphous silicon layer, and the amorphous silicon layer is enclosed inside by the first dielectric layer and the second dielectric layer; the top surface of the first dielectric layer is equal to or lower than the top surface of the second dielectric layer, and the top surface of the second dielectric layer is lower than the top surface of the deep trench.
And a third P-type epitaxial layer is formed in the formation region of the deep trench and on the surface of the N-type epitaxial layer outside the deep trench, the deep trench on the top surface of the second dielectric layer is completely filled with the third P-type epitaxial layer in the formation region of the deep trench, the top surface of the third P-type epitaxial layer is of a flat structure, and the top surface of the third P-type epitaxial layer is higher than the top surface of the deep trench.
And a P-type ion implantation region and an N-type ion implantation region are formed in the third P-type epitaxial layer, the formation region of the N-type ion implantation region comprises the formation region of the photodiode, and the formation region of the P-type ion implantation region comprises the formation region of the deep trench isolation structure.
The depth of the N-type ion implantation region is greater than or equal to that of the third P-type epitaxial layer so that the bottom surface of the N-type ion implantation region enters the N-type epitaxial layer; the N-type region of the photodiode is formed by longitudinally superposing the N-type epitaxial layer and the N-type ion implantation region corresponding to the top of the N-type epitaxial layer, and the depth of the depletion region in reverse bias of the photodiode is determined by the thickness of the N-type epitaxial layer and the thickness of the third P-type epitaxial layer so as to realize longitudinal size expansion of the photodiode.
The I-type region of the photodiode is composed of the first intrinsic epitaxial layer at the bottom of the N-type region, and the P-type region of the photodiode is composed of the first P-type epitaxial layer at the bottom of the I-type region and the semiconductor substrate.
The deep trench isolation structure is formed by overlapping the second intrinsic epitaxial layer, the second P-type epitaxial layer, the first dielectric layer, the amorphous silicon layer, the second dielectric layer and the P-type ion implantation region corresponding to the top of the deep trench.
In a further improvement, the semiconductor substrate is a silicon substrate, the N-type epitaxial layer is an N-type silicon epitaxial layer, the first P-type epitaxial layer, the second P-type epitaxial layer and the third P-type epitaxial layer are all P-type silicon epitaxial layers, and the first intrinsic epitaxial layer and the second intrinsic epitaxial layer are all intrinsic silicon epitaxial layers.
The further improvement is that the critical dimension of the deep groove is 0.2-0.5 micron.
The further improvement is that the top surface of the amorphous silicon layer is 0.4 to 0.8 microns lower than the top surface of the deep trench;
in a further improvement, the top surface of the second dielectric layer is 0.1 to 0.2 microns lower than the top surface of the deep trench.
The further improvement is that the first dielectric layer is a thermal oxidation layer.
The further improvement is that the second dielectric layer is silicon oxide formed by deposition; the deposition process of the second dielectric layer comprises the following steps: high Aspect Ratio Process (HARP), High Density Plasma (HDP) Chemical Vapor Deposition (CVD), TEOS based CVD.
In order to solve the above technical problem, the method for manufacturing a CMOS image sensor according to the present invention includes the steps of:
the method comprises the following steps of firstly, sequentially forming a first P-type epitaxial layer, a first intrinsic epitaxial layer and an N-type epitaxial layer on a P-type doped semiconductor substrate.
Etching the N-type epitaxial layer in a pixel region of the CMOS image sensor to form a plurality of deep grooves; the deep trench penetrates through the N-type epitaxial layer and the first intrinsic epitaxial layer and the bottom surface of the deep trench into the first P-type epitaxial layer.
The pixel region comprises a plurality of pixel units, each pixel unit comprises one photodiode, a deep trench isolation structure is isolated between the photodiodes, and the deep trench is located in a forming region of the deep trench isolation structure.
And thirdly, sequentially forming a second intrinsic epitaxial layer, a second P-type epitaxial layer and a first dielectric layer on the inner side surface of the deep groove.
And fourthly, forming an amorphous silicon layer to completely fill the deep groove formed by the second intrinsic epitaxial layer, the second P-type epitaxial layer and the first dielectric layer.
Fifthly, etching the top surface of the amorphous silicon layer back to be lower than the top surface of the deep groove.
Sixthly, forming a second dielectric layer on the top surface of the amorphous silicon layer, wherein the amorphous silicon layer is sealed inside by the first dielectric layer and the second dielectric layer; the top surface of the first dielectric layer is equal to or lower than the top surface of the second dielectric layer, and the top surface of the second dielectric layer is lower than the top surface of the deep trench.
And seventhly, forming a third P-type epitaxial layer, wherein the third P-type epitaxial layer is formed in the forming region of the deep groove and on the surface of the N-type epitaxial layer outside the deep groove, the deep groove on the top surface of the second dielectric layer is completely filled by the third P-type epitaxial layer in the forming region of the deep groove, the top surface of the third P-type epitaxial layer is of a flat structure, and the top surface of the third P-type epitaxial layer is higher than the top surface of the deep groove.
Step six, performing P-type ion implantation to form a P-type ion implantation area in the selected area of the third P-type epitaxial layer, and performing N-type ion implantation to form an N-type ion implantation area in the selected area of the third P-type epitaxial layer; the forming region of the N-type ion implantation region comprises a forming region of the photodiode, and the forming region of the P-type ion implantation region comprises a forming region of the deep trench isolation structure.
The depth of the N-type ion implantation region is greater than or equal to that of the third P-type epitaxial layer so that the bottom surface of the N-type ion implantation region enters the N-type epitaxial layer; the N-type region of the photodiode is formed by longitudinally superposing the N-type epitaxial layer and the N-type ion implantation region corresponding to the top of the N-type epitaxial layer, and the depth of the depletion region in reverse bias of the photodiode is determined by the thickness of the N-type epitaxial layer and the thickness of the third P-type epitaxial layer so as to realize longitudinal size expansion of the photodiode.
The I-type region of the photodiode is composed of the first intrinsic epitaxial layer at the bottom of the N-type region, and the P-type region of the photodiode is composed of the first P-type epitaxial layer at the bottom of the I-type region and the semiconductor substrate.
The deep trench isolation structure is formed by overlapping the second intrinsic epitaxial layer, the second P-type epitaxial layer, the first dielectric layer, the amorphous silicon layer, the second dielectric layer and the P-type ion implantation region corresponding to the top of the deep trench.
In a further improvement, the semiconductor substrate is a silicon substrate, the N-type epitaxial layer is an N-type silicon epitaxial layer, the first P-type epitaxial layer, the second P-type epitaxial layer and the third P-type epitaxial layer are all P-type silicon epitaxial layers, and the first intrinsic epitaxial layer and the second intrinsic epitaxial layer are all intrinsic silicon epitaxial layers.
The further improvement is that the critical dimension of the deep groove is 0.2-0.5 micron.
The further improvement is that after the fifth step is completed, the top surface of the amorphous silicon layer is 0.4-0.8 micrometer lower than the top surface of the deep trench.
The further improvement is that the step six comprises the following sub-steps:
and 61, carrying out a deposition process to form the second dielectric layer, wherein the second dielectric layer completely fills the deep trench on the top surface of the amorphous silicon layer and extends to the outside of the deep trench.
And 62, performing a chemical mechanical polishing process to remove all the second dielectric layers outside the deep trench and to level the top surfaces of the second dielectric layers and the deep trench.
And 63, carrying out an etching process to reduce the top surface of the second dielectric layer to a required height.
In a further improvement, in step 63, the top surface of the first dielectric layer is also lowered.
In a further improvement, the top surface of the second dielectric layer is 0.1 to 0.2 microns lower than the top surface of the deep trench.
In a further improvement, in step 61, the deposition process of the second dielectric layer includes: HARP, HDP CVD, TEOS based CVD.
In a further improvement, in the third step, the first dielectric layer is formed by a thermal oxidation process.
The further improvement is that the step two comprises the following steps:
and forming a hard mask layer on the surface of the N-type epitaxial layer.
And patterning the hard mask layer to define a forming region of the deep trench.
And etching the N-type epitaxial layer, the first intrinsic epitaxial layer and the first P-type epitaxial layer by taking the hard mask layer as a mask to form the deep trench.
Compared with the prior art in which the depth of the N-type region is adjusted by ion implantation, the N-type region of the photodiode of the invention adopts a structure formed by overlapping the N-type epitaxial layer and the N-type ion implantation region formed in the second P-type epitaxial layer at the top of the N-type epitaxial layer, so that the thickness of the N-type region of the photodiode is equal to the sum of the thicknesses of the N-type epitaxial layer and the second P-type epitaxial layer, the thickness of the N-type region of the photodiode can be adjusted by directly adjusting the thicknesses of the N-type epitaxial layer and the second P-type epitaxial layer, and the depth of the depletion region when the photodiode is reversely biased can be adjusted by adjusting the thicknesses of the N-type epitaxial layer and the second P-type epitaxial layer because the thicknesses of the N-type epitaxial layer and the second P-type epitaxial layer can be accurately adjusted, therefore, the invention can realize the accurate adjustment of the depth of the depletion region of the photodiode during reverse bias and further can well expand the longitudinal dimension of the photodiode. The deeper the depletion region depth of the photodiode in reverse bias, the more the number of photo-generated electrons can be stored, so that the light absorption efficiency and the light sensitivity of the photodiode can be improved, and the light absorption efficiency and the light sensitivity of the photodiode can be maintained or improved under the condition of reducing the transverse size of the photodiode.
The deep groove isolation structure is formed by overlapping the second intrinsic epitaxial layer, the second P-type epitaxial layer, the first dielectric layer, the amorphous silicon layer, the second dielectric layer and the P-type ion injection region corresponding to the top part, which are filled in the deep groove, so that the depth of the deep groove isolation structure can be well expanded in the longitudinal direction, the optical or electrical isolation between the photodiodes can be well improved, and the performance of a device can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is an equivalent circuit schematic diagram of a pixel unit circuit of a conventional 3T-type CMOS image sensor;
fig. 2 is an equivalent circuit schematic diagram of a pixel unit circuit of a conventional 4T-type CMOS image sensor;
fig. 3A is a top view of a pixel region of a conventional CMOS image sensor;
FIG. 3B is a cross-sectional view taken along line AA in FIG. 3A;
fig. 4A to 4K are cross-sectional views of devices at one photodiode in steps of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention.
Detailed Description
FIG. 4K is a cross-sectional view of a device at a photodiode in a CMOS image sensor according to an embodiment of the present invention; the pixel region of the CMOS image sensor comprises a plurality of pixel units, each pixel unit comprises a photodiode, and a deep trench isolation structure is isolated between the photodiodes.
The deep trench isolation structure is formed in a deep trench 5, the deep trench 5 penetrates through an N-type epitaxial layer 4, a first intrinsic epitaxial layer 3 and the bottom surface of the deep trench 5 and enters a first P-type epitaxial layer 2, and the first P-type epitaxial layer 2, the first intrinsic epitaxial layer 3 and the N-type epitaxial layer 4 are sequentially overlapped on a P-type doped semiconductor substrate 1 from bottom to top.
The second intrinsic epitaxial layer 6, the second P-type epitaxial layer 7 and the first dielectric layer 8 are sequentially overlapped on the inner side surface of the deep trench 5, the deep trench 5 formed with the second intrinsic epitaxial layer 6, the second P-type epitaxial layer 7 and the first dielectric layer 8 is completely filled with an amorphous silicon layer 9, the top surface of the amorphous silicon layer 9 is etched back to be lower than the top surface of the deep trench 5, the second dielectric layer 10 is formed on the top surface of the amorphous silicon layer 9, and the amorphous silicon layer 9 is enclosed by the first dielectric layer 8 and the second dielectric layer 10; the top surface of the first dielectric layer 8 is equal to or lower than the top surface of the second dielectric layer 10, and the top surface of the second dielectric layer 10 is lower than the top surface of the deep trench 5.
A third P-type epitaxial layer 11 is formed in the formation region of the deep trench 5 and on the surface of the N-type epitaxial layer 4 outside the deep trench 5, the deep trench 5 above the top surface of the second dielectric layer 10 is completely filled with the third P-type epitaxial layer 11 in the formation region of the deep trench 5, the top surface of the third P-type epitaxial layer 11 is of a flat structure, and the top surface of the third P-type epitaxial layer 11 is higher than the top surface of the deep trench 5.
A P-type ion implantation region (not shown) and an N-type ion implantation region (not shown) are formed in the third P-type epitaxial layer 11, the formation region of the N-type ion implantation region includes the formation region of the photodiode, and the formation region of the P-type ion implantation region includes the formation region of the deep trench isolation structure.
The depth of the N-type ion implantation region is greater than or equal to that of the third P-type epitaxial layer 11, so that the bottom surface of the N-type ion implantation region enters the N-type epitaxial layer 4; the N-type region of the photodiode is formed by longitudinally superposing the N-type epitaxial layer 4 and the N-type ion implantation region corresponding to the top of the N-type epitaxial layer 4, and the depth of the depletion region in reverse bias of the photodiode is determined by the thickness of the N-type epitaxial layer 4 and the thickness of the third P-type epitaxial layer 11 so as to realize longitudinal size expansion of the photodiode.
The I-type region of the photodiode is composed of the first intrinsic epitaxial layer 3 at the bottom of the N-type region, and the P-type region of the photodiode is composed of the first P-type epitaxial layer 2 at the bottom of the I-type region and the semiconductor substrate 1.
The deep trench isolation structure is formed by overlapping the second intrinsic epitaxial layer 6, the second P-type epitaxial layer 7, the first dielectric layer 8, the amorphous silicon layer 9, the second dielectric layer 10 and the P-type ion implantation region corresponding to the top in the deep trench 5.
In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate, the N-type epitaxial layer 4 is an N-type silicon epitaxial layer, the first P-type epitaxial layer 2, the second P-type epitaxial layer 7 and the third P-type epitaxial layer 11 are all P-type silicon epitaxial layers, and the first intrinsic epitaxial layer 3 and the second intrinsic epitaxial layer 6 are all intrinsic silicon epitaxial layers.
The critical dimension of the deep groove 5 is 0.2-0.5 micron.
The top surface of the amorphous silicon layer 9 is lower than the top surface of the deep groove 5 by 0.4-0.8 micrometer;
the top surface of the second dielectric layer 10 is lower than the top surface of the deep trench 5 by 0.1-0.2 microns.
The first dielectric layer 8 is a thermal oxide layer.
The second dielectric layer 10 is silicon oxide formed by deposition; the deposition process of the second dielectric layer 10 comprises the following steps: HARP, HDP CVD, TEOS based CVD.
The pixel unit further comprises a CMOS pixel reading circuit for reading photo-generated electrons of the photodiode.
The number of transistors included in the CMOS pixel reading circuit is determined according to the type of an actual CMOS image sensor, for example: when the 3T CMOS image sensor shown in fig. 1 is used, the CMOS pixel reading circuit includes a reset transistor M1, an amplifier transistor M2, and a selection transistor M3, which are all NMOS transistors. When the 4T-type CMOS image sensor shown in fig. 2 is used, the CMOS pixel reading circuit includes a reset transistor M1, an amplifying transistor M2, a selection transistor M3 and the transfer transistor 4, all of which are NMOS transistors; while the drain region of the transfer transistor 4 needs to be provided as a floating active region.
The NMOS transistor of the CMOS pixel reading circuit needs to be formed in a P-type trap, and the P-type trap can be formed by a P-type ion implantation area which is formed in a forming area of the pixel unit in the figure 4; in a forming area of each pixel unit, the P-type ion implantation area and the N-type ion implantation area need to be defined through photoetching; the cross-sectional view of FIG. 4 only shows the formation region of the N-type region of the photodiode and the cross-sectional views of the deep trench isolation structures at both sides, so the P-type ion implantation region in the formation region of the NMOS transistor of the CMOS pixel reading circuit is not shown. As shown in fig. 4, the depth of the N-type region of the photodiode is directly determined by the thicknesses of the N-type epitaxial layer 2 and the second P-type epitaxial layer 6, and since the thicknesses of the N-type epitaxial layer 2 and the second P-type epitaxial layer 6 can be precisely adjusted, the depth of the N-type region of the photodiode can be set according to the requirements in the embodiment of the present invention, so that the longitudinal size of the N-type region of the photodiode can be well expanded.
Compared with the prior art in which the depth of the N-type region of the photodiode is adjusted by ion implantation, the N-type region of the photodiode according to the embodiment of the present invention has a structure in which the N-type epitaxial layer 4 and the N-type ion implantation region formed in the second P-type epitaxial layer 7 on the top of the N-type epitaxial layer 4 are stacked, so that the thickness of the N-type region of the photodiode is the sum of the thicknesses of the N-type epitaxial layer 4 and the second P-type epitaxial layer 7, and thus the thickness of the N-type region of the photodiode can be adjusted by directly adjusting the thicknesses of the N-type epitaxial layer 4 and the second P-type epitaxial layer 7, and since the N-type region of the photodiode is substantially depleted to form a depletion region after reset, the depth of the depletion region of the photodiode during reverse bias can be adjusted by adjusting the thicknesses of the N-type epitaxial layer 4 and the second P-type epitaxial layer 7, and since the thicknesses of the N-type epitaxial layer 4 and the second P-type epitaxial layer 7 can be accurately adjusted, therefore, the embodiment of the invention can realize the accurate adjustment of the depth of the depletion region when the photodiode is reversely biased, and can further well expand the longitudinal dimension of the photodiode. The deeper the depletion region depth of the photodiode in reverse bias, the more the number of photo-generated electrons can be stored, so that the light absorption efficiency and the light sensitivity of the photodiode can be improved, and therefore, the embodiment of the invention can keep or improve the light absorption efficiency and the light sensitivity of the photodiode under the condition of reducing the transverse size of the photodiode, so that the embodiment of the invention is beneficial to reducing the size of a pixel unit and improving the filling factor.
The deep trench isolation structure of the embodiment of the invention is formed by overlapping the second intrinsic epitaxial layer 6, the second P-type epitaxial layer 7, the first dielectric layer 8, the amorphous silicon layer 9, the second dielectric layer 10 and the P-type ion implantation region corresponding to the top part, which are filled in the deep trench 5, so that the depth of the deep trench isolation structure of the embodiment of the invention can be well expanded in the longitudinal direction, the optical or electrical isolation between the photodiodes can be well improved, and the performance of the device can be improved. For example, a deep trench isolation structure and a side contact structure of the N-type region of the photodiode can well reduce dark current at the side of the N-type region of the photodiode; the amorphous silicon layer 9 can realize good filling of the deep trench 5; the first dielectric layer 8 and the second dielectric layer 10 can well realize optical and electrical isolation on the surrounding structure of the amorphous silicon layer 8; the third P-type epitaxial layer 11 can further increase the depth of the deep-hole isolation structure, so that the deep-hole isolation structure can be further expanded in the longitudinal direction.
Fig. 4A to 4K are cross-sectional views of devices at a photodiode in steps of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention. The manufacturing method of the CMOS image sensor comprises the following steps:
step one, as shown in fig. 4A, a first P-type epitaxial layer 2, a first intrinsic epitaxial layer 3 and an N-type epitaxial layer 4 are sequentially formed on a P-type doped semiconductor substrate 1.
In the method of the embodiment of the invention, the semiconductor substrate 1 is a silicon substrate, the N-type epitaxial layer 4 is an N-type silicon epitaxial layer, the first P-type epitaxial layer 2, the second P-type epitaxial layer 7 and the third P-type epitaxial layer 11 which are formed subsequently are both P-type silicon epitaxial layers, and the first intrinsic epitaxial layer 3 and the second intrinsic epitaxial layer 6 which are formed subsequently are both intrinsic silicon epitaxial layers.
The doping impurities of the N-type epitaxial layer 2 comprise phosphorus or arsenic, the first intrinsic epitaxial layer 3 is not doped, and the doping impurities of the first P-type epitaxial layer 2 comprise boron.
Etching the N-type epitaxial layer 4 in a pixel region of the CMOS image sensor to form a plurality of deep grooves 5; the deep trench 5 penetrates through the N-type epitaxial layer 4 and the first intrinsic epitaxial layer 3 and the bottom surface of the deep trench 5 into the first P-type epitaxial layer 2.
The pixel region comprises a plurality of pixel units, each pixel unit comprises one photodiode, a deep trench isolation structure is isolated between the photodiodes, and the deep trench 5 is located in a forming region of the deep trench isolation structure.
In the method of the embodiment of the invention, the second step comprises the following sub-steps:
as shown in fig. 4B, a hard mask layer 201 is formed on the surface of the N-type epitaxial layer 4. The hard mask layer 201 is one or a combination of a silicon dioxide layer, a silicon nitride layer, silicon oxynitride and polysilicon, and the thickness of the hard mask layer 201 is 100 nm-800 nm.
As shown in fig. 4C, the hard mask layer 201 is patterned to define a formation region of the deep trench 5.
As shown in fig. 4C, the N-type epitaxial layer 4, the first intrinsic epitaxial layer 3, and the first P-type epitaxial layer 2 are etched using the hard mask layer 201 as a mask to form the deep trench 5.
The critical dimension of the deep groove 5 is 0.2-0.5 micron.
The etching process of the deep trench 5 comprises dry etching or wet etching. After the etching process of the deep trench 5 is completed, a cleaning process is further included to clean the etched residues of the deep trench 5.
And step three, as shown in fig. 4D, sequentially forming a second intrinsic epitaxial layer 6 and a second P-type epitaxial layer 7 on the inner side surface of the deep trench 5.
The second intrinsic epitaxial layer 6 and the second P-type epitaxial layer 7 are formed by selective epitaxial growth, so that the surface outside the deep trench 5 is covered by the hard mask layer 201 and epitaxial layers cannot grow, and therefore, the second intrinsic epitaxial layer 6 and the second P-type epitaxial layer 7 are only located on the inner side surface of the deep trench 5.
As shown in fig. 4E, a first dielectric layer 8 is formed. The first dielectric layer 8 is formed by a thermal oxidation process, that is, the first dielectric layer 8 is formed by thermally oxidizing the surface of the second P-type epitaxial layer 7, so that the first dielectric layer 8 is only located on the inner side surface of the deep trench 5.
Step four, as shown in fig. 4E, forming the amorphous silicon layer 9 to completely fill the deep trench 5 formed with the second intrinsic epitaxial layer 6, the second P-type epitaxial layer 7 and the first dielectric layer 8.
The amorphous silicon layer 9 grows globally, so that the amorphous silicon layer 9 also extends outside the deep trench 5.
Step five, as shown in fig. 4F, the top surface of the amorphous silicon layer 9 is etched back to be lower than the top surface of the deep trench 5.
In the method of the embodiment of the invention, after the fifth step is completed, the top surface of the amorphous silicon layer 9 is 0.4-0.8 micrometer lower than the top surface of the deep trench 5.
And after the etching process corresponding to the back etching in the step five is finished, carrying out a cleaning process for removing etching residues.
Sixthly, forming a second dielectric layer 10 on the top surface of the amorphous silicon layer 9, wherein the amorphous silicon layer 9 is sealed inside by the first dielectric layer 8 and the second dielectric layer 10; the top surface of the first dielectric layer 8 is equal to or lower than the top surface of the second dielectric layer 10, and the top surface of the second dielectric layer 10 is lower than the top surface of the deep trench 5.
In the method of the embodiment of the invention, the sixth step comprises the following sub-steps:
step 61, as shown in fig. 4G, a deposition process is performed to form the second dielectric layer 10, and the second dielectric layer 10 completely fills the deep trench 5 above the top surface of the amorphous silicon layer 9 and extends to the outside of the deep trench 5.
The second dielectric layer 10 is made of silicon oxide; the deposition process of the second dielectric layer 10 comprises the following steps: HARP, HDP CVD, TEOS based CVD.
Step 62, as shown in fig. 4H, a chemical mechanical polishing process is performed to remove all the second dielectric layer 10 outside the deep trench 5 and to level the top surface of the second dielectric layer 10 with the top surface of the deep trench 5. Since the hard mask layer 201 is further formed outside the deep trench 5, the top surface of the second dielectric layer 10 and the top surface of the hard mask layer 201 on the top of the deep trench 5 can be leveled by the chemical mechanical polishing process. Then, grinding is carried out until the surface of the deep groove 5 is level to the top surface of the deep groove, and the hard mask layer 201 is also removed after grinding is finished; or after the top surface of the second dielectric layer 10 is flush with the top surface of the hard mask layer 201 on the top of the deep trench 5, removing the hard mask layer 201 separately, and then grinding the top surface of the second dielectric layer 10 to be flush with the top of the deep trench 5.
Step 63, as shown in fig. 4I, an etching process is performed to reduce the top surface of the second dielectric layer 10 to a desired height. In step 63, the top surface of the first dielectric layer 8 is also simultaneously lowered. The top surface of the second dielectric layer 10 is lower than the top surface of the deep trench 5 by 0.1-0.2 microns.
Seventhly, forming a third P-type epitaxial layer 11, wherein the third P-type epitaxial layer 11 is formed in the formation region of the deep trench 5 and on the surface of the N-type epitaxial layer 4 outside the deep trench 5, the deep trench 5 above the top surface of the second dielectric layer 10 is completely filled with the third P-type epitaxial layer 11 in the formation region of the deep trench 5, the top surface of the third P-type epitaxial layer 11 is of a flat structure, and the top surface of the third P-type epitaxial layer 11 is higher than the top surface of the deep trench 5.
Step six, performing P-type ion implantation to form a P-type ion implantation region in the selected region of the third P-type epitaxial layer 11, and performing N-type ion implantation to form an N-type ion implantation region in the selected region of the third P-type epitaxial layer 11; the forming region of the N-type ion implantation region comprises a forming region of the photodiode, and the forming region of the P-type ion implantation region comprises a forming region of the deep trench isolation structure.
The depth of the N-type ion implantation region is greater than or equal to that of the third P-type epitaxial layer 11 so that the bottom surface of the N-type ion implantation region enters the N-type epitaxial layer 4; the N-type region of the photodiode is formed by longitudinally superposing the N-type epitaxial layer 4 and the N-type ion implantation region corresponding to the top of the N-type epitaxial layer 4, and the depth of the depletion region in reverse bias of the photodiode is determined by the thickness of the N-type epitaxial layer 4 and the thickness of the third P-type epitaxial layer 11 so as to realize longitudinal size expansion of the photodiode.
The I-type region of the photodiode is composed of the first intrinsic epitaxial layer 3 at the bottom of the N-type region, and the P-type region of the photodiode is composed of the first P-type epitaxial layer 2 at the bottom of the I-type region and the semiconductor substrate 1.
The deep trench isolation structure is formed by overlapping the second intrinsic epitaxial layer 6, the second P-type epitaxial layer 7, the first dielectric layer 8, the amorphous silicon layer 9, the second dielectric layer 10 and the P-type ion implantation region corresponding to the top in the deep trench 5.
After the sixth step is finished, the method further comprises the following steps:
and forming a CMOS pixel reading circuit of each pixel unit in the pixel area, wherein the CMOS pixel reading circuit is used for reading the photo-generated electrons of the photodiode.
The number of transistors included in the CMOS pixel reading circuit is determined according to the type of an actual CMOS image sensor, for example: when the 3T CMOS image sensor shown in fig. 1 is used, the CMOS pixel reading circuit includes a reset transistor M1, an amplifier transistor M2, and a selection transistor M3, which are all NMOS transistors. When the 4T-type CMOS image sensor shown in fig. 2 is used, the CMOS pixel reading circuit includes a reset transistor M1, an amplifying transistor M2, a selection transistor M3 and the transfer transistor 4, all of which are NMOS transistors; while the drain region of the transfer transistor 4 needs to be provided as a floating active region.
The NMOS transistor of the CMOS pixel reading circuit needs to be formed in a P-type trap, and the P-type trap can be formed by a P-type ion implantation area which is formed in a forming area of the pixel unit in the figure 4; in a forming area of each pixel unit, the P-type ion implantation area and the N-type ion implantation area need to be defined through photoetching; the cross-sectional view of FIG. 4 only shows the formation region of the N-type region of the photodiode and the cross-sectional views of the deep trench isolation structures at both sides, so the P-type ion implantation region in the formation region of the NMOS transistor of the CMOS pixel reading circuit is not shown. As shown in fig. 4, the depth of the N-type region of the photodiode is directly determined by the thicknesses of the N-type epitaxial layer 2 and the second P-type epitaxial layer 6, and since the thicknesses of the N-type epitaxial layer 2 and the second P-type epitaxial layer 6 can be precisely adjusted, the depth of the N-type region of the photodiode can be set according to the requirements in the embodiment of the present invention, so that the longitudinal size of the N-type region of the photodiode can be well expanded.
The present invention has been described in detail with reference to the specific examples, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (17)

1. A CMOS image sensor is characterized in that a pixel region of the CMOS image sensor comprises a plurality of pixel units, each pixel unit comprises a photodiode, and a deep trench isolation structure is isolated between the photodiodes;
the deep groove isolation structure is formed in a deep groove, the deep groove penetrates through an N-type epitaxial layer, a first intrinsic epitaxial layer and the bottom surface of the deep groove and enters a first P-type epitaxial layer, and the first P-type epitaxial layer, the first intrinsic epitaxial layer and the N-type epitaxial layer are sequentially overlapped on a P-type doped semiconductor substrate from bottom to top;
the second intrinsic epitaxial layer, the second P-type epitaxial layer and the first dielectric layer are sequentially overlapped on the inner side surface of the deep groove, the deep groove formed by the second intrinsic epitaxial layer, the second P-type epitaxial layer and the first dielectric layer is completely filled with the amorphous silicon layer, the top surface of the amorphous silicon layer is etched back to be lower than the top surface of the deep groove, the second dielectric layer is formed on the top surface of the amorphous silicon layer, and the amorphous silicon layer is enclosed inside by the first dielectric layer and the second dielectric layer; the top surface of the first dielectric layer is equal to or lower than the top surface of the second dielectric layer, and the top surface of the second dielectric layer is lower than the top surface of the deep trench;
a third P-type epitaxial layer is formed in the formation region of the deep trench and on the surface of the N-type epitaxial layer outside the deep trench, the deep trench above the top surface of the second dielectric layer is completely filled with the third P-type epitaxial layer in the formation region of the deep trench, the top surface of the third P-type epitaxial layer is of a flat structure, and the top surface of the third P-type epitaxial layer is higher than the top surface of the deep trench;
forming a P-type ion implantation region and an N-type ion implantation region in the third P-type epitaxial layer, wherein the formation region of the N-type ion implantation region comprises the formation region of the photodiode, and the formation region of the P-type ion implantation region comprises the formation region of the deep trench isolation structure;
the depth of the N-type ion implantation region is greater than or equal to that of the third P-type epitaxial layer so that the bottom surface of the N-type ion implantation region enters the N-type epitaxial layer; the N-type region of the photodiode is formed by longitudinally superposing the N-type epitaxial layer and the N-type ion implantation region corresponding to the top of the N-type epitaxial layer, and the depth of the depletion region in reverse bias of the photodiode is determined by the sum of the thickness of the N-type epitaxial layer and the thickness of the third P-type epitaxial layer so as to realize longitudinal size expansion of the photodiode;
the I-type region of the photodiode consists of the first intrinsic epitaxial layer at the bottom of the N-type region, and the P-type region of the photodiode consists of the first P-type epitaxial layer at the bottom of the I-type region and the semiconductor substrate;
the deep trench isolation structure is formed by overlapping the second intrinsic epitaxial layer, the second P-type epitaxial layer, the first dielectric layer, the amorphous silicon layer, the second dielectric layer and the P-type ion implantation region corresponding to the top of the deep trench.
2. The CMOS image sensor of claim 1, wherein: the semiconductor substrate is a silicon substrate, the N-type epitaxial layer is an N-type silicon epitaxial layer, the first P-type epitaxial layer, the second P-type epitaxial layer and the third P-type epitaxial layer are all P-type silicon epitaxial layers, and the first intrinsic epitaxial layer and the second intrinsic epitaxial layer are all intrinsic silicon epitaxial layers.
3. The CMOS image sensor of claim 1, wherein: the critical dimension of the deep groove is 0.2-0.5 micron.
4. The CMOS image sensor of claim 3, wherein: the top surface of the amorphous silicon layer is 0.4-0.8 microns lower than the top surface of the deep trench.
5. The CMOS image sensor of claim 4, wherein: the top surface of the second dielectric layer is 0.1-0.2 microns lower than the top surface of the deep trench.
6. The CMOS image sensor of claim 1, wherein: the first dielectric layer is a thermal oxide layer.
7. The CMOS image sensor of claim 1, wherein: the second dielectric layer is silicon oxide formed by deposition; the deposition process of the second dielectric layer comprises the following steps: HARP, HDP CVD, TEOS based CVD.
8. A method for manufacturing a CMOS image sensor, comprising the steps of:
the method comprises the following steps that firstly, a first P-type epitaxial layer, a first intrinsic epitaxial layer and an N-type epitaxial layer are sequentially formed on a P-type doped semiconductor substrate;
etching the N-type epitaxial layer in a pixel region of the CMOS image sensor to form a plurality of deep grooves; the deep trench penetrates through the N-type epitaxial layer, the first intrinsic epitaxial layer and the bottom surface of the deep trench into the first P-type epitaxial layer;
the pixel region comprises a plurality of pixel units, each pixel unit comprises a photodiode, a deep trench isolation structure is isolated between the photodiodes, and the deep trench is positioned in a forming region of the deep trench isolation structure;
thirdly, sequentially forming a second intrinsic epitaxial layer, a second P-type epitaxial layer and a first dielectric layer on the inner side surface of the deep groove;
step four, forming an amorphous silicon layer, and completely filling the deep groove formed with the second intrinsic epitaxial layer, the second P-type epitaxial layer and the first dielectric layer;
fifthly, etching the top surface of the amorphous silicon layer back to be lower than the top surface of the deep groove;
sixthly, forming a second dielectric layer on the top surface of the amorphous silicon layer, wherein the amorphous silicon layer is sealed inside by the first dielectric layer and the second dielectric layer; the top surface of the first dielectric layer is equal to or lower than the top surface of the second dielectric layer, and the top surface of the second dielectric layer is lower than the top surface of the deep trench;
seventhly, forming a third P-type epitaxial layer, wherein the third P-type epitaxial layer is formed in the forming region of the deep groove and on the surface of the N-type epitaxial layer outside the deep groove, the deep groove on the top surface of the second dielectric layer is completely filled by the third P-type epitaxial layer in the forming region of the deep groove, the top surface of the third P-type epitaxial layer is of a flat structure, and the top surface of the third P-type epitaxial layer is higher than the top surface of the deep groove;
step six, performing P-type ion implantation to form a P-type ion implantation area in the selected area of the third P-type epitaxial layer, and performing N-type ion implantation to form an N-type ion implantation area in the selected area of the third P-type epitaxial layer; the forming region of the N-type ion implantation region comprises a forming region of the photodiode, and the forming region of the P-type ion implantation region comprises a forming region of the deep trench isolation structure;
the depth of the N-type ion implantation region is greater than or equal to that of the third P-type epitaxial layer so that the bottom surface of the N-type ion implantation region enters the N-type epitaxial layer; the N-type region of the photodiode is formed by longitudinally superposing the N-type epitaxial layer and the N-type ion implantation region corresponding to the top of the N-type epitaxial layer, and the depth of the depletion region in reverse bias of the photodiode is determined by the sum of the thickness of the N-type epitaxial layer and the thickness of the third P-type epitaxial layer so as to realize longitudinal size expansion of the photodiode;
the I-type region of the photodiode consists of the first intrinsic epitaxial layer at the bottom of the N-type region, and the P-type region of the photodiode consists of the first P-type epitaxial layer at the bottom of the I-type region and the semiconductor substrate;
the deep trench isolation structure is formed by overlapping the second intrinsic epitaxial layer, the second P-type epitaxial layer, the first dielectric layer, the amorphous silicon layer, the second dielectric layer and the P-type ion implantation region corresponding to the top in the deep trench.
9. The method of manufacturing a CMOS image sensor according to claim 8, wherein: the semiconductor substrate is a silicon substrate, the N-type epitaxial layer is an N-type silicon epitaxial layer, the first P-type epitaxial layer, the second P-type epitaxial layer and the third P-type epitaxial layer are all P-type silicon epitaxial layers, and the first intrinsic epitaxial layer and the second intrinsic epitaxial layer are all intrinsic silicon epitaxial layers.
10. The method of manufacturing a CMOS image sensor according to claim 8, wherein: the critical dimension of the deep groove is 0.2-0.5 micron.
11. The method of manufacturing a CMOS image sensor according to claim 10, wherein: and after the fifth step is finished, the top surface of the amorphous silicon layer is 0.4-0.8 micrometer lower than the top surface of the deep groove.
12. The method of manufacturing a CMOS image sensor according to claim 11, wherein: step six comprises the following sub-steps:
step 61, performing a deposition process to form the second dielectric layer, wherein the second dielectric layer completely fills the deep trench on the top surface of the amorphous silicon layer and extends to the outside of the deep trench;
step 62, performing a chemical mechanical polishing process to remove all the second dielectric layers outside the deep trench and to level the top surfaces of the second dielectric layers and the deep trench;
and 63, carrying out an etching process to reduce the top surface of the second dielectric layer to a required height.
13. The method of manufacturing a CMOS image sensor according to claim 12, wherein: in step 63, the top surface of the first dielectric layer is also simultaneously lowered.
14. The method of manufacturing a CMOS image sensor according to claim 12, wherein: the top surface of the second dielectric layer is 0.1-0.2 microns lower than the top surface of the deep trench.
15. The method of manufacturing a CMOS image sensor according to claim 12, wherein: in step 61, the deposition process of the second dielectric layer includes: HARP, HDP CVD, TEOS based CVD.
16. The method of manufacturing a CMOS image sensor according to claim 8, wherein: in the third step, the first dielectric layer is formed by a thermal oxidation process.
17. The method of manufacturing a CMOS image sensor according to claim 8, wherein: the second step comprises the following sub-steps:
forming a hard mask layer on the surface of the N-type epitaxial layer;
the hard mask layer is patterned to define a forming area of the deep groove;
and etching the N-type epitaxial layer, the first intrinsic epitaxial layer and the first P-type epitaxial layer by taking the hard mask layer as a mask to form the deep trench.
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