CN112885285A - GIP circuit and control method thereof - Google Patents
GIP circuit and control method thereof Download PDFInfo
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- CN112885285A CN112885285A CN202110211279.8A CN202110211279A CN112885285A CN 112885285 A CN112885285 A CN 112885285A CN 202110211279 A CN202110211279 A CN 202110211279A CN 112885285 A CN112885285 A CN 112885285A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention relates to the technical field of GIP circuits, in particular to a GIP circuit and a control method thereof, and the GIP circuit comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11 and a capacitor C1, wherein a source electrode of the transistor T5 is electrically connected with a grid electrode of a transistor T8, a drain electrode of the transistor T9, a grid electrode of a transistor T3, a source electrode of a transistor T6, a grid electrode of a transistor T7 and one end of a capacitor C1 respectively, so that the voltage level of a Q point pull-down TFT can be maintained by improving a leakage path of the Q point pull-down TFT, the output waveform of the GIP circuit is stabilized, the cost of improving a GIP manufacturing process.
Description
Technical Field
The invention relates to the technical field of GIP circuits, in particular to a GIP circuit and a control method thereof.
Background
For the display Panel, the output waveform of the GIP (Gate In Panel) circuit directly affects the display quality of the picture, and the TFTs constituting the GIP circuit directly affect the operation of the GIP circuit. Therefore, it is particularly desirable to provide a GIP circuit and a control method thereof for improving the display effect of the panel.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a GIP circuit and a control method thereof are provided for improving an output waveform of a GIP and optimizing a display effect of a display screen.
In order to solve the above technical problems, a first technical solution adopted by the present invention is:
a GIP circuit comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4 and a capacitor C4, wherein a gate of the transistor T4 is electrically connected with a gate of the transistor T4, a gate of the transistor T4 and a gate of the transistor T4 are connected with a first GIP output signal, a source of the transistor T4 is electrically connected with a drain of the transistor T4, a source of the transistor T4, a drain of the transistor T4, a gate of the transistor T4, a source of the transistor T4, a gate of the transistor T4 and one end of the capacitor C4, a source of the transistor T4 is electrically connected with a gate of the transistor T4, a drain of the transistor T4, a gate of the transistor T4, a drain of the transistor T4 and a drain of the transistor T4, The gate of the transistor T9 is electrically connected to the gate of the transistor T10, the gate of the transistor T2 is electrically connected to the drain of the transistor T2 and the drain of the transistor T3, the source of the transistor T7 is electrically connected to the other end of the capacitor C1 and the drain of the transistor T10, the source of the transistor T7, the other end of the capacitor C1 and the drain of the transistor T10 are all connected to the second GIP output signal, the gate of the transistor T4 is electrically connected to the gate of the transistor T6, the gate of the transistor T4 and the gate of the transistor T6 are all connected to the third GIP output signal, and the source of the transistor T11 is electrically connected to the source of the transistor T8 and the source of the transistor T10.
The second technical scheme adopted by the invention is as follows:
a control method of a GIP circuit, comprising the steps of:
s1, controlling the gate of the transistor T1 and the gate of the transistor T5 to input high level at the first moment;
s2, controlling the gate of the transistor T1 and the gate of the transistor T5 to input low level at the second moment;
s3, at the third moment, the drain electrode of the control transistor T7 is switched from low level to high level;
s4, at the fourth moment, the drain electrode of the control transistor T7 is switched from high level to low level;
s5, at the fifth moment, controlling the grid of the transistor T4 and the grid of the transistor T6 to input high level; the first time, the second time, the third time, the fourth time and the fifth time are sequentially continuous times.
The invention has the beneficial effects that:
the gate of the transistor T1 is electrically connected to the gate of the transistor T5, the gate of the transistor T1 and the gate of the transistor T5 are all connected to the first GIP output signal, the source of the transistor T5 is electrically connected to the gate of the transistor T8, the drain of the transistor T9, the gate of the transistor T3, the source of the transistor T6, the gate of the transistor T7 and one end of the capacitor C1, the source of the transistor T7 is electrically connected to the other end of the capacitor C1 and the drain of the transistor T10, the source of the transistor T7, the other end of the capacitor C1 and the drain of the transistor T10 are all connected to the second GIP output signal, the gate of the transistor T582 is electrically connected to the gate of the transistor T6, the gate of the transistor T53 and the gate of the transistor T6 are all connected to the third GIP output signal, so that the Q point (i.e., the source of the transistor T5, the gate of the transistor T3, the transistor T3, The gate of the transistor T7 and the common terminal of one end of the capacitor C1) pull down the leakage path of the TFT, thereby maintaining the voltage level of the Q point, stabilizing the output waveform of the GIP circuit, saving the cost of improving the GIP process, and optimizing the display effect of the display screen.
Drawings
FIG. 1 is a schematic diagram of a GIP circuit according to the present invention;
FIG. 2 is a flowchart illustrating steps of a method for controlling a GIP circuit according to the present invention;
fig. 3 is a timing waveform diagram of a GIP circuit according to the present invention.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, a technical solution provided by the present invention:
a GIP circuit comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4 and a capacitor C4, wherein a gate of the transistor T4 is electrically connected with a gate of the transistor T4, a gate of the transistor T4 and a gate of the transistor T4 are connected with a first GIP output signal, a source of the transistor T4 is electrically connected with a drain of the transistor T4, a source of the transistor T4, a drain of the transistor T4, a gate of the transistor T4, a source of the transistor T4, a gate of the transistor T4 and one end of the capacitor C4, a source of the transistor T4 is electrically connected with a gate of the transistor T4, a drain of the transistor T4, a gate of the transistor T4, a drain of the transistor T4 and a drain of the transistor T4, The gate of the transistor T9 is electrically connected to the gate of the transistor T10, the gate of the transistor T2 is electrically connected to the drain of the transistor T2 and the drain of the transistor T3, the source of the transistor T7 is electrically connected to the other end of the capacitor C1 and the drain of the transistor T10, the source of the transistor T7, the other end of the capacitor C1 and the drain of the transistor T10 are all connected to the second GIP output signal, the gate of the transistor T4 is electrically connected to the gate of the transistor T6, the gate of the transistor T4 and the gate of the transistor T6 are all connected to the third GIP output signal, and the source of the transistor T11 is electrically connected to the source of the transistor T8 and the source of the transistor T10.
From the above description, the beneficial effects of the present invention are:
the gate of the transistor T1 is electrically connected to the gate of the transistor T5, the gate of the transistor T1 and the gate of the transistor T5 are all connected to the first GIP output signal, the source of the transistor T5 is electrically connected to the gate of the transistor T8, the drain of the transistor T9, the gate of the transistor T3, the source of the transistor T6, the gate of the transistor T7 and one end of the capacitor C1, the source of the transistor T7 is electrically connected to the other end of the capacitor C1 and the drain of the transistor T10, the source of the transistor T7, the other end of the capacitor C1 and the drain of the transistor T10 are all connected to the second GIP output signal, the gate of the transistor T582 is electrically connected to the gate of the transistor T6, the gate of the transistor T53 and the gate of the transistor T6 are all connected to the third GIP output signal, so that the Q point (i.e., the source of the transistor T5, the gate of the transistor T3, the transistor T3, The gate of the transistor T7 and the common terminal of one end of the capacitor C1) pull down the leakage path of the TFT, thereby maintaining the voltage level of the Q point, stabilizing the output waveform of the GIP circuit, saving the cost of improving the GIP process, and optimizing the display effect of the display screen.
Further, the drain of the transistor T7 is connected to the clock signal.
Further, the gate of the transistor T2, the drain of the transistor T2 and the drain of the transistor T3 are all connected to the positive electrode of the power supply.
Further, the source electrode of the transistor T8, the source electrode of the transistor T11 and the source electrode of the transistor T10 are all connected to the negative pole of the power supply.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10, and the transistor T11 are all N-channel MOS transistors.
From the above description, the output waveform of the GIP driving circuit can be further stabilized by the MOS transistor with the N-channel, so that the cost for improving the GIP process is saved, and the display effect of the display screen is optimized.
Referring to fig. 2, another technical solution provided by the present invention:
a control method of a GIP circuit, comprising the steps of:
s1, controlling the gate of the transistor T1 and the gate of the transistor T5 to input high level at the first moment;
s2, controlling the gate of the transistor T1 and the gate of the transistor T5 to input low level at the second moment;
s3, at the third moment, the drain electrode of the control transistor T7 is switched from low level to high level;
s4, at the fourth moment, the drain electrode of the control transistor T7 is switched from high level to low level;
s5, at the fifth moment, controlling the grid of the transistor T4 and the grid of the transistor T6 to input high level; the first time, the second time, the third time, the fourth time and the fifth time are sequentially continuous times.
From the above description, the beneficial effects of the present invention are:
the gate of the transistor T1 is electrically connected to the gate of the transistor T5, the gate of the transistor T1 and the gate of the transistor T5 are all connected to the first GIP output signal, the source of the transistor T5 is electrically connected to the gate of the transistor T8, the drain of the transistor T9, the gate of the transistor T3, the source of the transistor T6, the gate of the transistor T7 and one end of the capacitor C1, the source of the transistor T7 is electrically connected to the other end of the capacitor C1 and the drain of the transistor T10, the source of the transistor T7, the other end of the capacitor C1 and the drain of the transistor T10 are all connected to the second GIP output signal, the gate of the transistor T582 is electrically connected to the gate of the transistor T6, the gate of the transistor T53 and the gate of the transistor T6 are all connected to the third GIP output signal, so that the Q point (i.e., the source of the transistor T5, the gate of the transistor T3, the transistor T3, The gate of the transistor T7 and the common terminal of one end of the capacitor C1) pull down the leakage path of the TFT, thereby maintaining the voltage level of the Q point, stabilizing the output waveform of the GIP circuit, saving the cost of improving the GIP process, and optimizing the display effect of the display screen.
Further, at the fifth timing, the gate of the transistor T2, the drain of the transistor T2, and the drain of the transistor T3 are all controlled to input a high level.
Referring to fig. 1 and fig. 3, a first embodiment of the present invention is:
referring to fig. 1, a GIP circuit includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, and a capacitor C4, wherein a gate of the transistor T4 is electrically connected to a gate of the transistor T4, a gate of the transistor T4 and a gate of the transistor T4 are both connected to a first GIP output signal, a source of the transistor T4 is electrically connected to a drain of the transistor T4, a source of the transistor T4, a drain of the transistor T4, a source of the transistor T4 is electrically connected to the gate of the transistor T4, the drain of the transistor T4, the gate of the transistor T4, the source of the transistor T4, a gate of the transistor T4, a source of the transistor T4, and one end of the capacitor C4, and a source of, The gate of the transistor T9 is electrically connected to the gate of the transistor T10, the gate of the transistor T2 is electrically connected to the drain of the transistor T2 and the drain of the transistor T3, the source of the transistor T7 is electrically connected to the other end of the capacitor C1 and the drain of the transistor T10, the source of the transistor T7, the other end of the capacitor C1 and the drain of the transistor T10 are all connected to the second GIP output signal, the gate of the transistor T4 is electrically connected to the gate of the transistor T6, the gate of the transistor T4 and the gate of the transistor T6 are all connected to the third GIP output signal, and the source of the transistor T11 is electrically connected to the source of the transistor T8 and the source of the transistor T10.
The drain of the transistor T7 is connected to the clock signal.
The gate of the transistor T2, the drain of the transistor T2 and the drain of the transistor T3 are all connected to the anode of the power supply.
The source electrode of the transistor T8, the source electrode of the transistor T11 and the source electrode of the transistor T10 are all connected with the cathode of the power supply.
The transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10 and the transistor T11 are all N-channel MOS transistors.
Each stage of GIP circuit of the scheme has 11 TFTs, 1 capacitor C1, FW and VGH are direct current high voltage, and BW and VGL are direct current low voltage. In this embodiment, the high potential of ck (n) is VGH potential, and the low potential thereof is VGL potential. According to the scheme, the voltage of the Qb node is introduced, so that no leakage current is generated on a leakage path of the Q point, the level of the Q point cannot be influenced by the bias negative of the threshold voltage of the TFT, and the voltage level of the Q point can be maintained. The driving process of the GIP circuit is described below (please analyze with reference to fig. 3):
at time T1, Vg (n-4) is high, the transistor T1 and the transistor T5 are turned on, and the Qb point and the Q point start to be charged. At this time, since the voltage level of the point Q is high, the transistor T7 is in an on state, and the level of the output vg (n) is the level of ck (n), i.e., VGL; the transistor T8 is turned on, and the level of the point P is pulled down to VGL through the transistor T8.
At time T2, Vg (n-4) is low, and both the transistor T1 and the transistor T5 are turned off, and the Q point remains floating. Since the voltage at the point Q is high, the transistor T3 is turned on, the point Qb receives the VGH level, and the voltage at the point Qb is also high. Here, it is assumed that threshold voltages of the transistors T9, T11, T4, and T6 are all less than 0 with respect to the TFTs in the leakage path at the Q point, VGS (gate-source voltage) of the transistors T11 and T4 is 0, and considering that the threshold voltage is less than 0, the TFTs may generate leakage current, but the transistor T3 is in an on state at this time, and a high level at the Qb point is not affected by the leakage current; the TFTs directly related to the Q-point potential, such as the transistor T9 and the transistor T6, have VGS much smaller than 0 (due to the presence of the Qb-point potential), so that the Q-point is free from the influence of leakage current and the high level of the Q-point can be maintained.
At time T3, ck (n) changes from low to high, and at this time, due to the capacitor C1, the voltage at the point Q becomes higher due to the capacitive coupling effect, the transistor T7 is better opened, and the waveform vg (n) is transmitted as VGH.
At time T4, the ck (n) level changes from high to low, and at this time, due to the capacitor C1, the voltage level at the point Q changes back to the original H level due to the capacitive coupling effect, the transistor T7 is still turned on, and the waveform vg (n) is transferred to VGL.
At time T5, Vg (n +4) is high, the transistor T4 and the transistor T6 are turned on, and the potential at the point Q is discharged through this path. At this time, since the potential at the point Q is discharged to a low level, the potential at the point P is raised to VGH by the turn-on of the transistor T2, so that the TFTs controlled by the point P, such as the transistor T9, the transistor T10 and the transistor T11, will be turned on, and pull down the potentials at the point Q and the point vg (n) to VGL, thereby stabilizing the output waveform of the GIP circuit.
The GIP circuit designed by the scheme maintains the voltage level of the Q point by improving the leakage path of the pull-down TFT of the Q point, stabilizes the output waveform of the GIP circuit, saves the cost of improving the GIP process and optimizes the display effect of the display screen.
Referring to fig. 2 and fig. 3, a second embodiment of the present invention is:
referring to fig. 2, a method for controlling a GIP circuit includes the following steps:
s1, controlling the gate of the transistor T1 and the gate of the transistor T5 to input high level at the first moment;
s2, controlling the gate of the transistor T1 and the gate of the transistor T5 to input low level at the second moment;
s3, at the third moment, the drain electrode of the control transistor T7 is switched from low level to high level;
s4, at the fourth moment, the drain electrode of the control transistor T7 is switched from high level to low level;
s5, at the fifth moment, controlling the grid of the transistor T4 and the grid of the transistor T6 to input high level; the first time, the second time, the third time, the fourth time and the fifth time are sequentially continuous times.
At the fifth timing, the gate of the transistor T2, the drain of the transistor T2, and the drain of the transistor T3 are all controlled to input a high level.
Each stage of GIP circuit of the scheme has 11 TFTs, 1 capacitor C1, FW and VGH are direct current high voltage, and BW and VGL are direct current low voltage. In this embodiment, the high potential of ck (n) is VGH potential, and the low potential thereof is VGL potential. According to the scheme, the voltage of the Qb node is introduced, so that no leakage current is generated on a leakage path of the Q point, the level of the Q point cannot be influenced by the bias negative of the threshold voltage of the TFT, and the voltage level of the Q point can be maintained. The control method of the GIP circuit is implemented as follows (please analyze with reference to fig. 3):
at time T1, Vg (n-4) is high, the transistor T1 and the transistor T5 are turned on, and the Qb point and the Q point start to be charged. At this time, since the voltage level of the point Q is high, the transistor T7 is in an on state, and the level of the output vg (n) is the level of ck (n), i.e., VGL; the transistor T8 is turned on, and the level of the point P is pulled down to VGL through the transistor T8.
At time T2, Vg (n-4) is low, and both transistor T1 and transistor T5 are turned off, and the Q point remains floating. Since the voltage at the point Q is high, the transistor T3 is turned on, the point Qb receives the VGH level, and the voltage at the point Qb is also high. Here, it is assumed that threshold voltages of the transistors T9, T11, T4, and T6 are all less than 0 with respect to the TFTs in the leakage path at the Q point, VGS (gate-source voltage) of the transistors T11 and T4 is 0, and considering that the threshold voltage is less than 0, the TFTs may generate leakage current, but the transistor T3 is in an on state at this time, and a high level at the Qb point is not affected by the leakage current; the TFTs directly related to the Q-point potential, such as the transistor T9 and the transistor T6, have VGS much smaller than 0 (due to the presence of the Qb-point potential), so that the Q-point is free from the influence of leakage current and the high level of the Q-point can be maintained.
At time T3, ck (n) changes from low to high, and at this time, due to the capacitor C1, the voltage at the point Q becomes higher due to the capacitive coupling effect, the transistor T7 is better opened, and the waveform vg (n) is transmitted as VGH.
At time T4, the ck (n) level changes from high to low, and at this time, due to the capacitor C1, the voltage level at the point Q changes back to the original H level due to the capacitive coupling effect, the transistor T7 is still turned on, and the waveform vg (n) is transferred to VGL.
At time T5, Vg (n +4) is high, the transistor T4 and the transistor T6 are turned on, and the potential at the point Q is discharged through this path. At this time, since the potential at the point Q is discharged to a low level, the potential at the point P is raised to VGH by the turn-on of the transistor T2, so that the TFTs controlled by the point P, such as the transistor T9, the transistor T10 and the transistor T11, will be turned on, and pull down the potentials at the point Q and the point vg (n) to VGL, thereby stabilizing the output waveform of the GIP circuit.
The GIP circuit designed by the scheme maintains the voltage level of the Q point by improving the leakage path of the pull-down TFT of the Q point, stabilizes the output waveform of the GIP circuit, saves the cost of improving the GIP process and optimizes the display effect of the display screen.
In summary, according to the GIP circuit and the control method thereof provided by the present invention, the gate of the transistor T1 is electrically connected to the gate of the transistor T5, the gate of the transistor T1 and the gate of the transistor T5 are both connected to the first GIP output signal, the source of the transistor T5 is electrically connected to the gate of the transistor T8, the drain of the transistor T9, the gate of the transistor T3, the source of the transistor T6, the gate of the transistor T7 and one end of the capacitor C1, the source of the transistor T7 is electrically connected to the other end of the capacitor C1 and the drain of the transistor T10, the source of the transistor T7, the other end of the capacitor C1 and the drain of the transistor T10 are all connected to the second GIP output signal, the gate of the transistor T4 is electrically connected to the gate of the transistor T6, and the gate of the transistor T4 and the gate of the transistor T6 are both connected to the third GIP output signal, so that the Q point can, The gate of the transistor T3, the drain of the transistor T9, the source of the transistor T6, the gate of the transistor T7, and the common terminal of one end of the capacitor C1) pull down the leakage path of the TFT, thereby maintaining the voltage level of the Q point, stabilizing the output waveform of the GIP circuit, saving the cost of improving the GIP process, and optimizing the display effect of the display screen.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.
Claims (7)
1. A GIP circuit is characterized by comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11 and a capacitor C1, wherein a gate of the transistor T1 is electrically connected with a gate of a transistor T5, a gate of the transistor T1 and a gate of the transistor T5 are connected with a first GIP output signal, a source of the transistor T1 is electrically connected with a drain of a transistor T5, a source of a transistor T3, a drain of a transistor T11, a source of a transistor T4 and a drain of a transistor T6, a source of the transistor T5 is electrically connected with a gate of a transistor T8, a drain of a transistor T9, a gate of a transistor T3, a source of a transistor T6, a gate of a transistor T7 and one end of a capacitor C1, and a source of the transistor T2 is electrically connected with a drain of a transistor T8, A gate of the transistor T11, a gate of the transistor T9, and a gate of the transistor T10 are electrically connected, the gate of the transistor T2 is electrically connected to a drain of the transistor T2 and a drain of the transistor T3, a source of the transistor T7 is electrically connected to the other end of the capacitor C1 and a drain of the transistor T10, a source of the transistor T7, the other end of the capacitor C1, and a drain of the transistor T10 are all connected to the second GIP output signal, the gate of the transistor T4 is electrically connected to a gate of the transistor T6, a gate of the transistor T4 and a gate of the transistor T6 are all connected to the third GIP output signal, and a source of the transistor T11 is electrically connected to a source of the transistor T8 and a source of the transistor T10, respectively.
2. The GIP circuit according to claim 1, wherein a drain of said transistor T7 is connected to a clock signal.
3. The GIP circuit according to claim 1, wherein the gate of the transistor T2, the drain of the transistor T2 and the drain of the transistor T3 are connected to the positive electrode of the power supply.
4. The GIP circuit according to claim 1, wherein the source of the transistor T8, the source of the transistor T11 and the source of the transistor T10 are connected to the negative terminal of a power supply.
5. The GIP circuit of claim 1, wherein the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10 and the transistor T11 are all N-channel MOS transistors.
6. A control method of the GIP circuit of claim 1, comprising the steps of:
s1, controlling the gate of the transistor T1 and the gate of the transistor T5 to input high level at the first moment;
s2, controlling the gate of the transistor T1 and the gate of the transistor T5 to input low level at the second moment;
s3, at the third moment, the drain electrode of the control transistor T7 is switched from low level to high level;
s4, at the fourth moment, the drain electrode of the control transistor T7 is switched from high level to low level;
s5, at the fifth moment, controlling the grid of the transistor T4 and the grid of the transistor T6 to input high level; the first time, the second time, the third time, the fourth time and the fifth time are sequentially continuous times.
7. The method of controlling the GIP circuit according to claim 6, wherein at the fifth timing, the gate of the transistor T2, the drain of the transistor T2 and the drain of the transistor T3 are all controlled to input a high level.
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| CN113793573A (en) * | 2021-10-14 | 2021-12-14 | 福建华佳彩有限公司 | Low-power-consumption GIP circuit and driving method thereof |
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| CN215220223U (en) * | 2021-02-25 | 2021-12-17 | 福建华佳彩有限公司 | GIP circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113793573A (en) * | 2021-10-14 | 2021-12-14 | 福建华佳彩有限公司 | Low-power-consumption GIP circuit and driving method thereof |
| CN113793573B (en) * | 2021-10-14 | 2024-05-14 | 福建华佳彩有限公司 | GIP circuit with low power consumption and driving method thereof |
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| Publication number | Publication date |
|---|---|
| CN112885285B (en) | 2024-01-19 |
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