CN112881283B - Detection method and detection device for bonding degree of wafer and semiconductor process equipment - Google Patents
Detection method and detection device for bonding degree of wafer and semiconductor process equipment Download PDFInfo
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Abstract
The application provides a method and a device for detecting the bonding degree of a wafer and semiconductor process equipment, wherein the method comprises the following steps: the method comprises the steps of obtaining a cross section of a wafer in the thickness direction, wherein the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked, and the thickness direction is parallel to the thickness direction of the wafer; controlling an indentation apparatus to press the first silicon layer with a predetermined load to generate a crack on the first silicon layer; and determining whether the crack passes through the bonding layer and extends to the second silicon layer, and determining that the bonding degree of the wafer is qualified under the condition that the crack passes through the bonding layer and extends to the second silicon layer. The method can visually determine the bonding degree of the specific structure regions such as the central region, the step region and the like of the wafer, and solves the problem that the interface bonding strength of the specific position of the wafer cannot be measured in the prior art.
Description
Technical Field
The present application relates to the field of semiconductors, and in particular, to a method and an apparatus for detecting a bonding degree of a wafer, a computer-readable storage medium, a processor, and a semiconductor processing device.
Background
In the research and development of the three-dimensional NAND chip, the interface bonding strength (bonding strength) of a structural wafer of a final product is evaluated, and the method has great significance for adjusting the process and the anti-failure performance of the product.
At present, the interface bonding degree of the bonding structure wafer is mainly evaluated by a blade insertion method and a double cantilever beam stretching method. The blade insertion method is characterized in that a thin blade with a certain thickness is inserted to generate cracks, the length of the cracks is measured by using infrared imaging, and the bonding degree of a wafer is quantized; the double-cantilever beam stretching method is to continuously stretch and compress the bonding structure wafer, and the bonding strength is represented by the crack length and the load required for tearing the bonding structure wafer;
the following short plates exist for blade insertion and double cantilever beam tensile evaluation of bond strength:
the blade insertion method can only insert along the position of the edge of the wafer with the complete structure, and cannot measure the interface bonding degree of the center position and the specific position of the wafer with the structure; the consumption of samples is large, the test cost is high, and the risk of wafer breakage and test failure exists in the insertion process;
the method for preparing the sample by the double-cantilever beam stretching method is complex and tedious, has long periodicity, and has low test success rate for the structural sample with stronger bonding degree. In addition, the double cantilever beam tensile method test is a macroscopic bonding strength test method, and the bonding strength of the bonding wafer with a specific structure cannot be evaluated in a fixed-point manner.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present application mainly aims to provide a method, an apparatus, a computer-readable storage medium, a processor and a semiconductor processing device for detecting a bonding degree of a wafer, so as to solve the problem that the interface bonding strength of a specific position of the wafer cannot be measured in the prior art.
According to an aspect of the embodiments of the present invention, there is provided a method for detecting a bonding degree of a wafer, including: obtaining a cross section of the wafer in the thickness direction, wherein the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked; controlling an indentation apparatus to press the first silicon layer with a predetermined load to generate a crack on the first silicon layer; and detecting whether the crack passes through the bonding layer and extends to the second silicon layer, and if the crack passes through the bonding layer and extends to the second silicon layer, determining that the bonding degree of the wafer is qualified.
Optionally, before controlling the indentation apparatus to press the first silicon layer with a predetermined load, the method further comprises: and controlling polishing equipment to perform polishing treatment on the section so as to enable the section to be flat and smooth.
Optionally, controlling a polishing device to perform polishing treatment on the cross section so as to make the cross section flat and smooth, includes: controlling the polishing equipment to perform rough grinding on the section; and controlling the polishing equipment to carry out fine grinding on the cross section after the rough grinding.
Optionally, the indentation apparatus is a nanoindentation apparatus comprising a needle tip indenter.
According to another aspect of the embodiments of the present invention, there is also provided an apparatus for detecting a bonding degree of a wafer, including an obtaining unit, a control unit, and a detection unit, where the obtaining unit is configured to obtain a cross section of the wafer in a thickness direction, and the cross section includes at least a first silicon layer, a bonding layer, and a second silicon layer that are stacked in sequence; the control unit is used for controlling the indentation equipment to press the first silicon layer with a preset load so as to generate cracks on the first silicon layer; the detecting unit is used for detecting whether the crack passes through the bonding layer and extends to the second silicon layer, and if the crack passes through the bonding layer and extends to the second silicon layer, determining that the bonding degree of the wafer is qualified.
Optionally, the apparatus further comprises a processing unit for controlling a polishing device to perform a polishing process on the cross section to make the cross section flat and smooth before controlling the indentation device to press the first silicon layer with a predetermined load.
Optionally, the processing unit comprises a first control module and a second control module, wherein the first control module is used for controlling the polishing device to perform rough grinding on the cross section; the second control module is used for controlling the polishing equipment to carry out fine grinding on the cross section after the rough grinding.
According to still another aspect of embodiments of the present invention, there is also provided a computer-readable storage medium including a stored program, wherein the program executes any one of the methods.
According to another aspect of the embodiments of the present invention, there is also provided a processor, configured to execute a program, where the program executes any one of the methods.
According to another aspect of the embodiments of the present invention, there is also provided a semiconductor process apparatus, including: one or more processors, memory, a display device, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing any of the methods.
According to the method for detecting the bonding degree of the wafer, the cross section of the wafer in the thickness direction is obtained firstly, and the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked; then controlling an indentation apparatus to press the first silicon layer with a predetermined load to generate a crack on the first silicon layer; and finally, detecting whether the crack passes through the bonding layer and extends to the second silicon layer, and determining that the bonding degree of the wafer is qualified under the condition that the crack passes through the bonding layer and extends to the second silicon layer. The detection method can detect the bonding degree of the specific structure regions such as the central region and the step region of the wafer intuitively, realizes the qualitative confirmation of the interface bonding degree of the specific position of the wafer, and better solves the problem that the interface bonding strength of the specific position of the wafer cannot be measured in the prior art.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 is a schematic flow chart generated by a method for detecting a bonding degree of a wafer according to an embodiment of the present application;
fig. 2 shows a schematic view of an apparatus for detecting a bonding degree of a wafer according to an embodiment of the present application;
fig. 3 shows a schematic diagram of crack generation according to an embodiment of the application.
Wherein the figures include the following reference numerals:
100. a first silicon layer; 101. a bonding layer; 102. a second silicon layer.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As mentioned in the background art, the interface bonding strength of a specific position of a wafer cannot be measured in the prior art, and in order to solve the above problems, in an exemplary embodiment of the present application, a method for detecting the bonding degree of a wafer, a detection apparatus, a computer-readable storage medium, a processor, and a semiconductor processing apparatus are provided.
According to an embodiment of the application, a method for detecting the bonding degree of a wafer is provided.
Fig. 1 is a flowchart of a method for detecting a bonding degree of a wafer according to an embodiment of the present disclosure. As shown in fig. 1, the method comprises the steps of:
step S101, obtaining a cross section of the wafer in the thickness direction, wherein the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked;
step S102, controlling an indentation device to extrude the first silicon layer with a preset load so as to generate cracks on the first silicon layer;
step S103, detecting whether the crack passes through the bonding layer and extends to the second silicon layer, and if the crack passes through the bonding layer and extends to the second silicon layer, determining that the bonding degree of the wafer is acceptable.
Firstly, obtaining a cross section of the wafer in the thickness direction, wherein the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked; then controlling an indentation apparatus to press the first silicon layer with a predetermined load to generate a crack on the first silicon layer; and finally, detecting whether the crack passes through the bonding layer and extends to the second silicon layer, and determining that the bonding degree of the wafer is qualified under the condition that the crack passes through the bonding layer and extends to the second silicon layer. The detection method can detect the bonding degree of the specific structure regions such as the central region and the step region of the wafer intuitively, realizes the qualitative confirmation of the interface bonding degree of the specific position of the wafer, and better solves the problem that the interface bonding strength of the specific position of the wafer cannot be measured in the prior art.
Of course, the cross section may include other layers, and the bonding degree of the wafer may be determined to be acceptable as long as the crack passes through the bonding layer and extends to a layer immediately below the bonding layer.
In the practical application process, the detection method can be applied to various bonded wafer samples, including control wafers, wafer samples which are not thinned, wafer samples with a thinned single surface, bare die (wafer body) samples, packaged wafer samples and the like.
In a specific embodiment of the present application, after controlling the indentation apparatus to press the first silicon layer with a predetermined load to generate a crack on the first silicon layer, the image processing apparatus may be controlled to collect image information of the crack propagating on the cross section; identifying the image information based on a neural network model to determine whether the crack passes through the bonding layer and extends to the second silicon layer, the neural network model being a model generated by training image information of crack propagation at the cross section.
In practical applications, the crack stops extending and stays in a certain layer in the cross section, and the bonding energy of the wafer can be quantitatively obtained by determining the length of the crack in a second direction of the layer, such as the length L shown in fig. 3, wherein the second direction is perpendicular to the thickness direction of the wafer.
In order to facilitate subsequent generation of cracks on the first silicon layer and to more clearly and intuitively determine whether the cracks pass through the bonding layer and extend to the second silicon layer, and further to ensure that the bonding degree of the wafer is more accurately determined to be acceptable, according to a specific embodiment of the present application, before controlling the indentation apparatus to press the first silicon layer with a predetermined load, the method further includes: and controlling polishing equipment to polish the section so as to enable the section to be flat and smooth. And the subsequent extrusion of the section and crack observation are facilitated through polishing treatment.
Of course, the skilled person can also choose other ways to treat the cross-section so that it is even and smooth.
According to another specific embodiment of the present application, controlling the polishing device to perform polishing treatment on the section so as to make the section flat and smooth includes: controlling the polishing equipment to carry out coarse grinding on the section; and controlling the polishing equipment to carry out accurate grinding on the cross section after the rough grinding. The rough grinding is carried out firstly, then the fine grinding is carried out, so that the cracks can be conveniently generated on the first silicon layer subsequently, and whether the bonding degree of the wafer is qualified or not can be clearly and visually determined subsequently.
In the practical application process, the indentation device is a nano indentation device, and the nano indentation device comprises a needle tip pressure head. And pressing the first silicon layer with a predetermined load by controlling a tip indenter of the nanoindentation apparatus, thereby generating a triangular crack on the first silicon layer, and the crack propagates along a corner of the triangle. As shown in fig. 3. The empirical bonding level is determined to be acceptable when the crack extends from the first silicon layer 100 to the second silicon layer 102 through the bonding layer 101.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.
The embodiment of the present application further provides a device for detecting a bonding degree of a wafer, and it should be noted that the device for detecting a bonding degree of a wafer according to the embodiment of the present application may be used to execute the method for detecting a bonding degree of a wafer according to the embodiment of the present application. The following describes an apparatus for detecting a bonding degree of a wafer according to an embodiment of the present application.
Fig. 2 is a schematic view of an apparatus for detecting a bonding degree of a wafer according to an embodiment of the present disclosure. As shown in fig. 2, the apparatus includes: the wafer thickness measurement method comprises an acquisition unit 10, a control unit 20 and a detection unit 30, wherein the acquisition unit 10 is used for acquiring a cross section of the wafer in the thickness direction, and the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked; the control unit 20 is configured to control the indentation apparatus to press the first silicon layer with a predetermined load to generate a crack in the first silicon layer; the detecting unit 30 is configured to detect whether the crack passes through the bonding layer and extends to the second silicon layer, and determine that the bonding degree of the wafer is acceptable if the crack passes through the bonding layer and extends to the second silicon layer.
The detection device for the bonding degree of the wafer obtains the cross section of the wafer in the thickness direction through the obtaining unit, wherein the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked; controlling an indentation apparatus to press the first silicon layer with a predetermined load by the control unit to generate a crack on the first silicon layer; and detecting whether the crack passes through the bonding layer and extends to the second silicon layer through the detection unit, and determining that the bonding degree of the wafer is qualified when the crack passes through the bonding layer and extends to the second silicon layer. The detection device can detect the bonding degree of the specific structure regions such as the central region and the step region of the wafer intuitively, realizes qualitative confirmation of the interface bonding degree of the specific position of the wafer, and well solves the problem that the interface bonding strength of the specific position of the wafer cannot be measured in the prior art.
Of course, the cross section may include other layers, and the bonding degree of the wafer may be determined to be acceptable as long as the crack passes through the bonding layer and extends to a layer immediately below the bonding layer.
In the practical application process, the detection method can be applied to various bonded wafer samples, including control wafers, wafer samples which are not thinned, wafer samples with a thinned single surface, bare die (wafer body) samples, packaged wafer samples and the like.
In a specific embodiment of the present application, after controlling the indentation apparatus to press the first silicon layer with a predetermined load to generate a crack on the first silicon layer, the image processing apparatus may be controlled to collect image information of the crack propagating on the cross section; identifying the image information based on a neural network model to determine whether the crack passes through the bonding layer and extends to the second silicon layer, the neural network model being a model generated by training image information of crack propagation at the cross section.
In practical applications, the crack stops extending and stays in a certain layer in the cross section, and the bonding energy of the wafer can be quantitatively obtained by determining the length of the crack in a second direction of the layer, such as the length L shown in fig. 3, wherein the second direction is perpendicular to the thickness direction of the wafer.
In order to facilitate subsequent generation of cracks on the first silicon layer and to more clearly and intuitively determine whether the cracks pass through the bonding layer and extend to the second silicon layer, and further to ensure that the bonding degree of the wafer is more accurately determined to be qualified, according to a specific embodiment of the present application, the apparatus further includes a processing unit, and the processing unit is configured to control the polishing device to perform polishing processing on the cross section before controlling the indentation device to press the first silicon layer with a predetermined load, so as to make the cross section flat and smooth. And the subsequent extrusion of the section and crack observation are facilitated through polishing treatment.
Of course, the skilled person can also choose other ways to treat the cross-section so that it is even and smooth.
According to another specific embodiment of the present application, the processing unit includes a first control module and a second control module, wherein the first control module is configured to control the polishing apparatus to perform rough grinding on the cross section; and the second control module is used for controlling the polishing equipment to carry out accurate grinding on the cross section after the rough grinding. The rough grinding is carried out firstly, then the fine grinding is carried out, so that the cracks can be conveniently generated on the first silicon layer subsequently, and whether the bonding degree of the wafer is qualified or not can be clearly and visually determined subsequently.
In the practical application process, the indentation device is a nano indentation device, and the nano indentation device comprises a needle tip pressure head. And pressing the first silicon layer with a predetermined load by controlling a tip indenter of the nanoindentation apparatus, thereby generating a triangular crack on the first silicon layer, and the crack propagates along a corner of the triangle. As shown in fig. 3. The empirical bonding level is determined to be acceptable when the crack extends from the first silicon layer 100 to the second silicon layer 102 through the bonding layer 101.
The device for detecting the bonding degree of the wafer comprises a processor and a memory, wherein the acquiring unit, the control unit, the detecting unit and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.
The processor comprises a kernel, and the kernel calls the corresponding program unit from the memory. One or more than one inner core can be set, and the problem that the interface bonding strength of a specific position of a wafer cannot be measured in the prior art is solved by adjusting inner core parameters.
The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.
An embodiment of the present invention provides a computer-readable storage medium, on which a program is stored, where the program, when executed by a processor, implements the method for detecting the bonding degree of a wafer.
The embodiment of the invention provides a processor, which is used for running a program, wherein the program executes the method for detecting the bonding degree of the wafer when running.
The embodiment of the invention provides equipment, which comprises a processor, a memory and a program which is stored on the memory and can run on the processor, wherein when the processor executes the program, at least the following steps are realized:
step S101, obtaining a cross section of the wafer in the thickness direction, wherein the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked;
step S102, controlling an indentation device to extrude the first silicon layer with a preset load so as to generate cracks on the first silicon layer;
step S103, detecting whether the crack passes through the bonding layer and extends to the second silicon layer, and if the crack passes through the bonding layer and extends to the second silicon layer, determining that the bonding degree of the wafer is acceptable.
The device herein may be a server, a PC, a PAD, a mobile phone, etc.
The present application further provides a computer program product adapted to perform a program of initializing at least the following method steps when executed on a data processing device:
step S101, obtaining a cross section of the wafer in the thickness direction, wherein the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked;
step S102, controlling an indentation device to extrude the first silicon layer with a preset load so as to generate cracks on the first silicon layer;
step S103, detecting whether the crack passes through the bonding layer and extends to the second silicon layer, and if the crack passes through the bonding layer and extends to the second silicon layer, determining that the bonding degree of the wafer is acceptable.
According to still another exemplary embodiment of the present application, there is also provided a semiconductor process apparatus, including: one or more processors, memory, a display device, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing any of the above-described methods.
The semiconductor processing apparatus described above, comprising one or more processors, memory, display devices, and one or more programs, the one or more programs comprising instructions for performing any of the methods described above. The semiconductor process equipment can visually detect the bonding degree of the specific structure areas such as the central area and the step area of the wafer, realizes qualitative confirmation of the interface bonding degree of the specific position of the wafer, and well solves the problem that the interface bonding strength of the specific position of the wafer cannot be measured in the prior art.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) the method for detecting the bonding degree of the wafer comprises the steps of firstly obtaining a cross section of the wafer in the thickness direction, wherein the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked; then controlling an indentation apparatus to press the first silicon layer with a predetermined load to generate a crack on the first silicon layer; and finally, detecting whether the crack passes through the bonding layer and extends to the second silicon layer, and determining that the bonding degree of the wafer is qualified under the condition that the crack passes through the bonding layer and extends to the second silicon layer. The detection method can detect the bonding degree of the specific structure regions such as the central region and the step region of the wafer intuitively, realizes the qualitative confirmation of the interface bonding degree of the specific position of the wafer, and better solves the problem that the interface bonding strength of the specific position of the wafer cannot be measured in the prior art.
2) The detection device for the bonding degree of the wafer obtains the cross section of the wafer in the thickness direction through the obtaining unit, wherein the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked; controlling an indentation apparatus to press the first silicon layer with a predetermined load by the control unit to generate a crack on the first silicon layer; and detecting whether the crack passes through the bonding layer and extends to the second silicon layer through the detection unit, and determining that the bonding degree of the wafer is qualified when the crack passes through the bonding layer and extends to the second silicon layer. The detection device can detect the bonding degree of the specific structure regions such as the central region and the step region of the wafer intuitively, realizes qualitative confirmation of the interface bonding degree of the specific position of the wafer, and well solves the problem that the interface bonding strength of the specific position of the wafer cannot be measured in the prior art.
3) Semiconductor processing apparatus of the present application includes one or more processors, memory, display devices, and one or more programs including instructions for performing any of the methods described above. The semiconductor process equipment can visually detect the bonding degree of the specific structure areas such as the central area and the step area of the wafer, realizes qualitative confirmation of the interface bonding degree of the specific position of the wafer, and well solves the problem that the interface bonding strength of the specific position of the wafer cannot be measured in the prior art.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for detecting the bonding degree of a wafer is characterized by comprising the following steps:
obtaining a cross section of the wafer in the thickness direction, wherein the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked;
controlling an indentation apparatus to press the first silicon layer with a predetermined load to generate a crack on the first silicon layer;
and detecting whether the crack passes through the bonding layer and extends to the second silicon layer, and if the crack passes through the bonding layer and extends to the second silicon layer, determining that the bonding degree of the wafer is qualified.
2. The method according to claim 1, wherein prior to controlling the indentation apparatus to compress the first silicon layer at a predetermined load, the method further comprises:
and controlling polishing equipment to perform polishing treatment on the section so as to enable the section to be flat and smooth.
3. The method of claim 2, wherein controlling a polishing device to polish the cross section to make the cross section flat and smooth comprises:
controlling the polishing equipment to perform rough grinding on the section;
and controlling the polishing equipment to carry out fine grinding on the cross section after the rough grinding.
4. The method according to claim 1, wherein the creasing device is a nanoindenting device that includes a needle tip indenter.
5. An apparatus for detecting a bonding degree of a wafer, comprising:
the wafer thickness measurement device comprises an acquisition unit, a measurement unit and a measurement unit, wherein the acquisition unit is used for acquiring the cross section of the wafer in the thickness direction, and the cross section at least comprises a first silicon layer, a bonding layer and a second silicon layer which are sequentially stacked;
a control unit for controlling an indentation apparatus to press the first silicon layer with a predetermined load to generate a crack on the first silicon layer;
and the detecting unit is used for detecting whether the crack passes through the bonding layer and extends to the second silicon layer, and if the crack passes through the bonding layer and extends to the second silicon layer, determining that the bonding degree of the wafer is qualified.
6. The apparatus of claim 5, further comprising:
and the processing unit is used for controlling the polishing device to perform polishing treatment on the section so as to enable the section to be flat and smooth before controlling the indentation device to press the first silicon layer with a preset load.
7. The apparatus of claim 6, wherein the processing unit comprises:
the first control module is used for controlling the polishing equipment to carry out rough grinding on the cross section;
and the second control module is used for controlling the polishing equipment to carry out accurate grinding on the cross section after the rough grinding.
8. A computer-readable storage medium, characterized in that the computer-readable storage medium comprises a stored program, wherein the program performs the method of any one of claims 1 to 4.
9. A processor, characterized in that the processor is configured to run a program, wherein the program when running performs the method of any of claims 1 to 4.
10. A semiconductor processing apparatus, comprising: one or more processors, memory, a display device, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs comprising instructions for performing the method of any of claims 1-4.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110034420.1A CN112881283B (en) | 2021-01-11 | 2021-01-11 | Detection method and detection device for bonding degree of wafer and semiconductor process equipment |
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| CN202110034420.1A CN112881283B (en) | 2021-01-11 | 2021-01-11 | Detection method and detection device for bonding degree of wafer and semiconductor process equipment |
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