CN112867105A

CN112867105A - Communication device having power saving mode and capable of saving power as much as possible in power saving mode

Info

Publication number: CN112867105A
Application number: CN201911184068.9A
Authority: CN
Inventors: 郭俊伟
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-11-27
Filing date: 2019-11-27
Publication date: 2021-05-28
Anticipated expiration: 2039-11-27
Also published as: CN112867105B

Abstract

The communication device with the power saving mode comprises a storage circuit unit and a direct memory access module. The storage circuit unit is used for storing instruction and data information to be executed by a microcontroller or a control circuit of the communication device. The direct memory access module is used for backing up and transferring the instruction and data information stored in the storage circuit unit to a memory of the electronic device when the communication device receives a broadcast synchronization signal periodically transmitted by another communication device. The memory circuit unit is powered off when in the power-saving mode; when the electronic device leaves the power saving mode, the storage circuit unit is powered on, and the direct memory access module acquires and backfills instruction and data information from a memory of the electronic device to the storage circuit unit.

Description

Communication device having power saving mode and capable of saving power as much as possible in power saving mode

Technical Field

The present invention relates to a communication apparatus, and more particularly, to a communication apparatus having a power saving mode and capable of saving power as much as possible in the power saving mode.

Background

Generally, for a communication circuit chip (e.g., a WLAN wireless network communication chip) having a power saving mode (low power saving mode), a conventional mechanism still supplies power to a part of the memory circuit units when the communication circuit chip enters the power saving mode, for example, a static random access memory (sram) inside the communication circuit chip is supplied with a lower supply voltage level, the sram is used for storing data information of at least one instruction that needs to be immediately executed by a microcontroller or a control circuit of the communication circuit chip when the communication circuit chip leaves the power saving mode and returns to the normal mode, and for the conventional mechanism, if the sram is not supplied with power in the power saving mode, the microcontroller cannot immediately execute the at least one instruction when the communication circuit chip returns to the normal mode, the performance is greatly limited. Therefore, even though the conventional mechanism reduces the supply voltage level as much as possible to save power, in the power saving mode, the power consumption of the sram still accounts for, for example, about one third of the power consumption of the leakage current of the communication circuit chip. Therefore, the conventional scheme has its performance limit, and it is difficult to achieve the power saving effect.

Disclosure of Invention

Therefore, an object of the present invention is to provide a communication device having a power saving mode and capable of saving power as much as possible in the power saving mode, so as to solve the above problems.

According to an embodiment of the present invention, a communication device having a power saving mode for externally connecting to a host system of an electronic device is disclosed, and the communication device includes an interface circuit, a memory circuit unit and a direct memory access module. The interface circuit is configured to be externally coupled to the host-end system. The storage circuit unit is coupled to the interface circuit and is used for storing data information of at least one instruction to be executed by a microcontroller or a control circuit of the communication device. The direct memory access module is coupled to the storage circuit unit and the interface circuit, and is used for backing up and transferring the data information of the at least one instruction stored in the storage circuit unit to a memory of the electronic device when the communication device receives a broadcast synchronization signal periodically transmitted by another communication device. When the communication device enters the power saving mode, the storage circuit unit is powered off; when the communication device leaves the power saving mode, the storage circuit unit is powered on, and the direct memory access module acquires and backfills the data information of the at least one instruction from the memory of the electronic device to the storage circuit unit.

According to an embodiment of the present invention, a communication device having a power saving mode is disclosed, the communication device is configured to be disposed inside an electronic device, and the communication device is configured to be externally connected to a processor and a memory of the electronic device through a bus interface, and the communication device includes an interface circuit, a storage circuit unit, and a direct memory access module. The interface circuit is coupled to the processor and the memory of the electronic device through the bus interface. The storage circuit unit is coupled to the interface circuit and is used for storing data information of at least one instruction to be executed by a microcontroller or a control circuit of the communication device. The direct memory access module is coupled to the storage circuit unit and the interface circuit, and is used for backing up and transferring the data information of the at least one instruction stored in the storage circuit unit to the memory of the electronic device when the communication device receives a broadcast synchronization signal periodically transmitted by another communication device. When the communication device enters the power saving mode, the storage circuit unit is powered off; when the communication device leaves the power saving mode, the storage circuit unit is powered on, and the direct memory access module acquires and backfills the data information of the at least one instruction from the memory of the electronic device to the storage circuit unit.

Drawings

Fig. 1 is a schematic diagram of an electronic device to which a communication device according to an embodiment of the invention is applied.

Fig. 2 is a schematic diagram of the DMA module shown in fig. 1 backing up and transferring content information stored in the at least one memory circuit unit to the memory of the electronic device according to an embodiment of the invention.

Fig. 3 is a schematic diagram of the DMA module shown in fig. 1 restoring content data from the memory of the electronic device to the at least one memory circuit unit according to an embodiment of the invention.

Fig. 4 is a schematic diagram of a time sequence for performing backup and dump of content data and content data restoration according to an embodiment of the present application.

Fig. 5 is a schematic diagram of a timing sequence for performing backup and dump of content data and content data restoration according to another embodiment of the present application.

FIG. 6 is a diagram of an electronic device with a communication apparatus applied to an embedded system circuit according to another embodiment of the invention.

Description of the symbols

100 communication device

101. 200 electronic device

102 host-end system circuit

103. 201 processor

104. 202 memory

105 host interface

110 interface circuit

111 microcontroller or control circuit

112 memory circuit cell

113 direct memory access module

114 direct memory access circuit

115 analysis processing circuit

116 timer circuit

203 bus interface

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a communication device 100 applied to an electronic device 101 according to an embodiment of the invention. The communication device 100 has a power saving mode and is used to be externally connected to a host system circuit 102 of an electronic device 101, the communication device 100 is, for example, but not limited to, a wireless network communication circuit chip and has the power saving mode (for example, a low power consumption mode), and the electronic device 101 can be, for example, a portable electronic device, a non-portable electronic device, a mobile phone device or a notebook computer device (but not limited to), in other words, in an embodiment, the communication device 100 can be a wireless network communication circuit chip and is disposed inside a mobile phone device or a notebook computer device. As shown in fig. 1, the communication device 100 is disposed inside the electronic device 101, the electronic device 101 further includes a host-system circuit 102, the host-system circuit 102 includes a processor 103, such as a cpu, a memory 104, and a host interface (host interface)105, and the host-system circuit 102 and the communication device 100 are connected and communicate through an external bus, the host interface 105, and an interface circuit of the communication device 100.

Practically, in one embodiment, the communication device 100 includes, for example, the interface circuit 110, a microcontroller or control circuit 111, at least one memory circuit unit 112 (one or more memory circuit units), and a direct memory access module (DMA module) 113, wherein the DMA module 113 includes, for example, a direct memory access circuit (DMA circuit) 114, an analysis processing circuit 115, and a timer circuit (timer circuit)116, the at least one memory circuit unit 112 is coupled to the microcontroller or control circuit 111, the interface circuit 110, and the DMA module 113, the at least one memory circuit unit 112 is, for example, at least one static random access memory, at least one register circuit, at least one content addressable memory (associative memory), and/or at least one flip-flop, the at least one memory circuit unit 112 is used for storing or temporarily storing data information and/or values of at least one instruction to be executed by the microcontroller or control circuit 111.

For example, the at least one memory circuit unit 112 includes a sram, a plurality of register circuits, a plurality of content addressable memories and/or a plurality of flip-flops, and when entering the power saving mode, the conventional mechanism would reduce the supply voltage to the sram, the plurality of register circuits, the plurality of content addressable memories and/or the plurality of flip-flops for power saving, however, such a method cannot achieve the power saving purpose effectively, and still has excessive leakage current, but the idea of the present disclosure is to power down the memory area of the sram, the register circuits, the content addressable memories and/or the flip-flops that can be powered down in the communication device 100, so that the portion does not need to be powered up in the power saving mode, and the generation of leakage current is avoided directly, for example, the memory areas, register circuits, CAM and/or flip-flops that are not powered down may be classified as one or more units that are powered down, such as to store the next closest time to wake up and other parameters or values that may be used in the power saving mode; for example, in the case of a sram with a size of 96KB (but not limited to), the present disclosure may achieve that only the storage area of the sram with a size of 16KB or 32KB (but not limited to) is powered on (even the sram is not powered at all) in the power saving mode, and other storage areas are powered off, so as to save more power, and for the register circuit, the content addressable memory and/or the flip-flop, the number of the register circuit, the content addressable memory and/or the flip-flop that need to be powered on may be reduced as much as possible in the power saving mode, so as to save more power.

In practice, the DMA module 113 is used for backing up and transferring the data information of the at least one instruction stored in the at least one memory circuit unit 112 to the memory 104 of the electronic device 101 when the communication device 100 receives a broadcast synchronization signal periodically transmitted by another communication device. When the communication device 100 enters the power saving mode, the at least one memory circuit unit 112 is powered off. When the communication device leaves the power saving mode, the at least one memory circuit unit 112 is powered, and the DMA module 113 retrieves and backfills the data message of the at least one command from the memory 104 of the electronic device 101 to the at least one memory circuit unit 112, such that, when the communication device 100 enters the power saving mode, the size of the memory area and the number of register circuits, content addressable memories and/or flip-flops that power the sram may be minimized, i.e., the memory area, register circuit, content addressable memory and/or flip-flops of the SRAM that are not needed in the power saving mode can be powered down, but only supplies power to the storage area, register circuit, content addressable memory and/or flip-flop of the sram that needs to be used in the power saving mode. In order to achieve the purpose of saving power and rapidly restore the content information correspondingly stored in the storage area, the register circuit, the content addressable memory and/or the trigger of the static random access memory which is powered off in the power saving mode, the present disclosure adopts a mechanism of direct memory access operation, rapidly performs the backup of the content data periodically or once, and performs the restoration and the backfill of the content data periodically.

Taking the communication device 100 as a wireless network communication circuit chip as an example, the other communication device is, for example, a wireless access point (wireless access point) that periodically sends a broadcast synchronization signal to all wireless network communication circuits within its coverage area to synchronize the wireless network communication circuits, the broadcast synchronization signal is, for example, a beacon packet (beacon packet) followed by a data transmission interval of the wireless access point (the wireless access point is used to transmit data packets), because the beacon packet contains information for different wireless network communication circuits, if a wireless network communication circuit enters a power saving mode, the wireless network communication circuit needs to periodically monitor whether the beacon packet will transmit one or more data packets to the wireless network communication circuit in the subsequent data transmission interval, if it is judged that there is a data packet to be transmitted, the wireless network communication circuit will wake up in the data transmission interval without entering the power saving mode, otherwise, if it is judged that there is no data packet to be transmitted, the wireless network communication circuit will fall asleep in the data transmission interval to enter the power saving mode, at this time, if the wireless access point suddenly has a data packet to be transmitted to the wireless network communication circuit, the wireless access point will temporarily store (queue) the data packet first, wait for the next data transmission interval and then transmit to the wireless network communication circuit.

Furthermore, in one embodiment, the DMA operation may include two DMA modes, the first DMA mode is to backup and backfill restore the content data sequentially according to the address, and the second DMA mode is to backup part of the content data in an address and corresponding backfill restore. Referring to fig. 2 and fig. 3 in combination, fig. 2 is a schematic diagram of the DMA module 113 shown in fig. 1 backing up and transferring content information stored in the at least one memory circuit unit 112 to the memory 104 of the electronic device 101 according to an embodiment of the present invention, and fig. 3 is a schematic diagram of the DMA module 113 shown in fig. 1 restoring content data from the memory 104 of the electronic device 101 to the at least one memory circuit unit 112 according to an embodiment of the present invention.

As shown in fig. 2, for the example of the first DMA mode for sequentially backing up data directly, for example, the analysis processing circuit 115 of the DMA module 113 is configured to sequentially back up and forward one or more corresponding content data corresponding to one or more first addresses of the at least one memory circuit unit 112 to the DMA circuit 114 in sequence according to the sequence of the one or more first addresses; the DMA circuit 114 is used for storing the one or more corresponding content data to one or more second addresses of the memory 104 of the electronic device 101 in an order of one or more second addresses of the memory 104 through a direct memory access operation, for example, a storage circuit unit 112 stores two corresponding pieces of content information, i.e. 0x1111_1111 and 0x2222_2222, using two consecutive first addresses, i.e. SA [31:0] and (SA +4) [31:0], and an analysis processing circuit 115 obtains 0x1111_1111 and 0x2222_2222 data and transfers the two pieces of data to the DMA circuit 114 in an order of SA [31:0] and (SA +4) [31:0], and the DMA circuit 114 writes the two pieces of data to two consecutive second addresses, i.e. DA [31:0] and (DA +4) [31:0], wherein [31:0] indicates that the address is 32 bits (i.e., 4 bits, but not limited to), so SA +4 and DA +4 indicate the next addresses of SA and DA, respectively.

In the second DMA mode for indirect data backup, for example, the analysis processing circuit 115 is configured to generate at least one bit mask information and at least one transferred content information according to the at least one first address information and the at least one corresponding content information when the communication device 100 receives the beacon packet periodically transmitted by the wireless access point, and the DMA circuit 114 is configured to store the at least one first address information, the at least one bit mask information and the at least one transferred content information to at least one set of second addresses of the dram 104 of the electronic device 101 through a direct memory access operation via the interface circuit 110, wherein each set of second addresses includes three consecutive addresses. For example, in the example of fig. 2, a part of bits in the first address 0x0 in the memory circuit unit, i.e. 0x0[31:24], is recorded with corresponding content information 0x12, and the other bits in the address 0x0 do not record content information, the analyzing circuit 115 of the DMA module 113 is used for analyzing a part of bits (i.e. 0x0[31:24]) in the first address 0x0 and corresponding content information 0x12, for example, to generate a bit mask information 0xFF00_0000 and a transcribed content information, e.g. 0x1234_5678 (but not limited, also 0x1200_0000, etc.), the bit mask information 0xFF00_0000 indicates that only a certain part (i.e. the first 8 bits of high bits) of the address 0x0 is recorded with corresponding content information, and the other bits are not recorded with content information, the analyzing circuit 115 records content information in the first address 0x0, The generated bitmask information 0xFF00_0000 and the dumped content information, such as 0x1234_5678, are transmitted to the DMA circuit 114, and the DMA circuit 114 stores the three data items sequentially in a storage space with three consecutive second addresses, such as DA [31:0], (DA +4) [31:0], and (DA +8) [31:0], in the memory 104 of the electronic device 100, that is, the DMA circuit 114 performs the operation of sequentially storing different input data items in the memory 104 of the electronic device 100 through the direct memory access operation according to the sequence of the received input data items.

As shown in fig. 3, when the communication device 100 determines to leave the power saving mode, the storage circuit unit 112 is powered, and the corresponding data is restored and refilled into the storage circuit unit 112, and then leaves the power saving mode to enter the normal operation mode, so that the microcontroller or the control circuit 111 can normally or correctly read the data information of at least one instruction stored in the storage circuit unit 112 in the normal operation mode to perform the corresponding operation or calculation. Accordingly, restoring and backfilling the corresponding data to the memory circuit unit also has two modes, namely, directly restoring the data and indirectly restoring the data sequentially.

For example, in the case of sequentially restoring data as shown in FIG. 3, the DMA circuit 114 reads the content data of 0x1111_1111 and 0x2222_2222 from two consecutive second addresses of the memory 104, namely DA [31:0] and (DA +4) [31:0], through the DMA operation, and transmits the two content data to the analysis circuit 115, and the analysis circuit 115 transmits the two content data to two first addresses of the memory circuit unit 112, namely SA [31:0] and (SA +4) [31:0 ]. Thus, after the one or more content data entries are restored, the microcontroller or control circuit 111 may retrieve data information of at least one instruction from one or more first locations to execute the execution of the at least one instruction.

In addition, for the indirectly restored data of FIG. 3, the DMA circuit 114 reads the first address 0x0, the previously backed-up generated bitmask information 0xFF00_0000 and the transferred content information 0x1234_5678 from a set of three consecutive second addresses of the memory 104, such as DA [31:0], (DA +4) [31:0] and (DA +8) [31:0], through the direct memory access operation, and transmits the data to the analysis processing circuit 115, and the analysis processing circuit 115 parses the data through the bitmask information 0xFF00_0000 to obtain only 0x12 of the transferred content information, such as 0x1234_5678, and parses the information of the partial bits (i.e., 0x0[31:24]) stored in the first address 0x0, and then the analysis processing circuit 115 writes data 0x12 to the portion (i.e., 0x 360 x 0) of the first address 0x12 (i.e., 0x 3624: 24, 0, 3, the data is written through the direct memory access operation, therefore, after the content data is restored, the microcontroller or the control circuit 111 can obtain the data information of at least one instruction from the partial address of one or more first addresses to execute the operation of the at least one instruction.

In addition, please refer to fig. 4, fig. 4 is a schematic diagram illustrating a timing sequence for performing the backup and the dump of the content data and the restore of the content data according to an embodiment of the present application. As shown in fig. 4, when backing up and transferring content data, the DMA module 113 can selectively adopt a single backup and a periodic data recovery, the clock signal for data backup and/or data recovery can be provided by the timer circuit 116 to trigger the DMA module 113, and the timer circuit 116 is configured to periodically or once generate a trigger signal to trigger the DMA module 113 according to a time interval of the beacon packet periodically transmitted by the wireless access point, so as to start the DMA circuit 114 for DMA operation. For example, as shown in fig. 4, the TBTT represents a target beacon transmission time (target beacon transmission time) and represents a start time of broadcasting each beacon packet periodically, and for a second time interval T2 after the first target beacon transmission time TBTT, the second time interval T2 at least includes a transceiving time of a beacon packet, and for a single backup of content data, the DMA module 113 can perform backup and dump of content data at the following time points: such as when the software firmware sets an immediate trigger, receives a beacon packet, or does not receive a beacon packet but T2 times out, etc. After the target beacon transmission time TBTT is received subsequently, the DMA module 113 does not perform data backup and dump, for example, when the second time interval T2 begins, the communication device 100 starts to receive the beacon packet transmitted by the wireless ap to determine whether to enter the power saving mode or not during the next transmission time, if it is determined that the power saving mode is to be entered (i.e., the communication device 100 determines that no data packet is transmitted from the wireless ap), for example, when the time of beacon transmission ends (but not limited to) and/or the communication device 100 enters the power saving mode again, the DMA module 113 starts to perform content data backup and dump, for example, when the time of beacon transmission ends (i.e., when no data packet is transmitted from the wireless ap), and/or when the communication device 100 enters the power saving mode again, the data information of the at least one instruction recorded by the storage circuit unit 112 is quickly backed up and dumped to the memory 104 of the electronic device 101 by the DMA operation, the memory circuit unit 112 is then powered down to save more power. Therefore, when content data is periodically restored, the DMA module 113 reads the first backup data from the memory 104 to periodically restore and generate and store the data information to the memory circuit unit 112, so that the data information recorded by the memory circuit unit 112 is the same as one copy. For example, for a first time interval T1 before the second target beacon transmission time TBTT, for example, when the first time interval T1 begins, the communication device 100 starts to leave the power saving mode, the memory circuit unit 112 starts to be powered, and the DMA module 113 starts to perform content data recovery, quickly reads previously backed-up data from the memory 104 of the electronic device 101 through the direct memory access operation and recovers the backed-up data to the memory circuit unit 112, so that the memory circuit unit 112 records data information of the at least one command.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating a timing sequence for performing a content data backup and dump and a content data restore according to another embodiment of the present application. As shown in fig. 5, when the DMA module 113 performs periodic content data backup, at the beginning of each first time interval T1, the communication device 100 starts to leave the power saving mode, the memory circuit unit 112 starts to be powered, the DMA module 113 starts to perform content data recovery, the memory 104 of the electronic device 101 quickly reads the previously backed-up data through the DMA operation and restores the backed-up data to the memory circuit unit 112, so that the memory circuit unit 112 records the data information of the at least one command, and at a second time interval T2 after each target beacon transmission time TBTT, when the second time interval T2 starts, the communication device 100 starts to receive the beacon packet transmitted by the wireless access point to determine whether to enter the power saving mode or not to enter the power saving mode during the next transmission time, if it is determined that the power saving mode is to be entered (i.e., the communication device 100 determines that no data packet is to be transmitted from the ap), after the beacon packet reception is finished and/or when the communication device 100 is to enter the power saving mode again, the DMA module 113 starts to perform content data backup and dump, quickly backup and dump the data information of the at least one command recorded by the memory circuit unit 112 to the memory 104 of the electronic device 101 through the DMA operation, and then the memory circuit unit 112 is powered off to save more power. In other words, for periodic backup, the DMA module 113 performs backup and dump of content data each time the second time interval T2 after the target beacon transmission time TBTT is received, so that when content data is periodically restored, the DMA module 113 reads the latest data to be dumped from the memory 104 to periodically restore and generate and store the data information to the memory circuit unit 112, and thus the data information currently recorded by the memory circuit unit 112 is not identical to the previously stored content information.

Furthermore, a communication device can be disposed inside an embedded system circuit, for example, and the backup and restore of content data can be from a memory circuit element of the communication device to a memory of the embedded system circuit, and then the memory restores the content data back to the memory circuit element. Referring to fig. 6, fig. 6 is a schematic diagram of the communication device 100 applied to an electronic device 200 according to another embodiment of the invention. The communication device 100 is configured to be disposed inside an electronic device 200 (e.g., embedded system circuit), and the communication device 100 is configured to be externally connected to a processor 201 and a memory 202 of the electronic device 200 through a bus interface 203; other operations and functions are the same as those in the above paragraphs, and are not described in detail.

Furthermore, for the embodiment having only the operation of directly backing up and restoring the content data, the analysis processing circuit 115 shown in fig. 1 may be optional (optional), for example, in an embodiment, the DMA module 113 may not include the analysis processing circuit 115, at least one storage circuit unit 112 is connected to the DMA circuit 114, and the DMA circuit 114 performs the operation of directly backing up and restoring the content data without transferring the data through the analysis processing circuit 115.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims

1. A communication device having a power-saving mode, the communication device being configured to be externally connected to a host system of an electronic device, the communication device comprising:

an interface circuit for externally coupling to the host-end system;

a memory circuit unit, coupled to the interface circuit, for storing data information of at least one instruction to be executed by a microcontroller or a control circuit of the communication device; and

a direct memory access module, coupled to the memory circuit unit and the interface circuit, for backing up and transferring the data information of the at least one command stored in the memory circuit unit to a memory of the electronic device when the communication device receives a broadcast synchronization signal periodically transmitted by another communication device;

wherein the memory circuit unit is powered off when the communication device enters the power saving mode; when the communication device leaves the power saving mode, the storage circuit unit is powered on, and the direct memory access module acquires and backfills the data information of the at least one instruction from the memory of the electronic device to the storage circuit unit.

2. The communication device as claimed in claim 1, wherein the another communication device is a wireless access point, and the broadcast synchronization signal is a beacon packet.

3. The communication device as claimed in claim 2, wherein the memory circuit unit comprises at least one of a static random access memory, a register circuit, a content addressable memory, and a flip-flop.

4. The communication device as claimed in claim 2, wherein the data message of the at least one command includes at least one corresponding content message stored in at least one first address, and when the communication device receives the beacon packet periodically transmitted by the wireless access point, the dma module backs up the at least one corresponding content message stored in the storage circuit unit through a dma operation and sequentially transfers the at least one corresponding content message to at least one second address of a dram of the electronic device according to the at least one first address through the interface circuit.

5. The communication device as claimed in claim 4, wherein the DMA module retrieves and backfills the at least one corresponding content information from the memory of the electronic device to the memory circuit unit via the DMA operation when the communication device leaves the power saving mode.

6. The communication device of claim 2, wherein the data message of the at least one command includes at least one corresponding content message stored at least one first address, the direct memory access module comprising:

an analysis processing circuit, for generating at least one bit mask information and at least one dump content information according to the at least one first address information and the at least one corresponding content information when the communication device receives the beacon packet periodically transmitted by the wireless access point; and

a direct memory access circuit, coupled to the analysis processing circuit, for storing the at least one first address information, the at least one bit mask information and the at least one dumped content information to at least one set of second addresses of a DRAM of the electronic device through a direct memory access operation by the interface circuit, each set of second addresses including three consecutive addresses.

7. The communication device as claimed in claim 6, wherein when the communication device leaves the power saving mode, the parsing circuit obtains the at least one first address information, the at least one bit mask information and the at least one dumped content information from the at least one set of second addresses of the DRAM of the electronic device, parses the at least one first address information and the at least one corresponding content information, and the DMA circuit backfills the at least one corresponding content information to the at least one first address information of the storage circuit unit through the DMA operation.

8. The communication device of claim 6, wherein the direct memory access module further comprises:

a timer circuit, coupled to the dma circuit, for periodically or once generating a trigger signal to the dma module according to a time interval of the beacon packet periodically transmitted by the wireless ap to initiate the dma operation of the dma circuit.

9. The communication device as claimed in claim 1, wherein the dma module automatically backs up and transfers the data information of the at least one command stored in the memory circuit unit to the memory of the electronic device according to at least one triggering event, and retrieves and backfills the data information of the at least one command from the memory of the electronic device to the memory circuit unit.

10. A communication device having a power saving mode, the communication device configured to be disposed inside an electronic device and externally connected to a processor and a memory of the electronic device through a bus interface, the communication device comprising:

an interface circuit, for coupling to the processor and the memory of the electronic device through the bus interface;

a memory circuit unit, coupled to the interface circuit, for storing data information of at least one instruction to be executed by a microcontroller of the communication device; and

a direct memory access module, coupled to the memory circuit unit and the interface circuit, for backing up and transferring the data information of the at least one command stored in the memory circuit unit to the memory of the electronic device when the communication device receives a broadcast synchronization signal periodically transmitted by another communication device;