CN112865561B - Diode clamping type back-to-back bridgeless three-level rectifier - Google Patents

Diode clamping type back-to-back bridgeless three-level rectifier Download PDF

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CN112865561B
CN112865561B CN202110121181.3A CN202110121181A CN112865561B CN 112865561 B CN112865561 B CN 112865561B CN 202110121181 A CN202110121181 A CN 202110121181A CN 112865561 B CN112865561 B CN 112865561B
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inductor
voltage
capacitor
diode
current
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CN112865561A (en
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马辉
曾雨涵
周沫函
邹旭
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China Three Gorges University CTGU
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output

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  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

A diode clamping type back-to-back bridgeless three-level rectifier comprises a power inductor series branch; the bidirectional tube is connected with the power supply inductance branch in parallel, the bidirectional tube is connected with the power supply inductance branch in series, and the two groups of bidirectional tubes form a PWM (pulse width modulation) rectification circuit; the midpoint voltage of the series capacitor is clamped by a diode bank. The three-level smoothing circuit is a three-level rectifier consisting of 4 full-controllable power switching tubes, 6 common diodes and 2 polar capacitors. Compared with the traditional two-level rectifying circuit, the voltage stress requirement on circuit elements is reduced. When the rectifying circuit works, the number of semiconductor devices flowing through is not more than 3, and the working loss of the circuit is small; the working mode of the circuit is switched by only changing one switching tube, so that the switching loss of the circuit is effectively reduced. The direct current bus is connected in series by two capacitors to work, and output current ripples are effectively reduced.

Description

Diode clamping type back-to-back bridgeless three-level rectifier
Technical Field
The invention relates to the technical field of single-phase three-level active rectifiers, in particular to a diode clamping type back-to-back bridgeless three-level rectifier.
Background
The power factor correction circuit can improve the power factor of the electric equipment and reduce the reactive power generated by the equipment. The flow of reactive power in the grid inevitably causes an increase in the losses of the transmission of electric energy in the grid, thus causing economic losses. In order to reduce the reactive power input by the load side to the power grid and simultaneously isolate higher harmonics which bring harm to electric equipment in the power grid, more and more targeted power electronic devices are put into the electric equipment. Meanwhile, the power electronic device is added into the electric equipment, so that the harmful higher harmonics can be effectively solved. The diode-clamped back-to-back bridgeless three-level rectifier bidirectional tube type three-level rectifier can keep stable voltage output to a load under the condition of maintaining high power factor, and is suitable for various occasions. Compared with a traditional two-level rectifier, the three-level rectifier has smaller ripple level; less device voltage stress; better power factor and power density.
Disclosure of Invention
The invention provides a diode clamping type back-to-back bridgeless three-level rectifier, which reduces the voltage stress requirement on circuit elements compared with the traditional two-level rectifier circuit. The diode clamps the midpoint of the series capacitor, so that the voltage stress borne by the switching tube is reduced, and the cost of the switching tube is reduced; two polar capacitors are used in series, and the voltage of the capacitors is reduced; when the rectifying circuit works, the number of semiconductor devices flowing through is not more than 3, and the working loss of the circuit is small; the working mode of the circuit is switched by only changing one switching tube, so that the switching loss of the circuit is effectively reduced. The direct current bus is connected in series by two capacitors to work, and output current ripples are effectively reduced.
The technical scheme adopted by the invention is as follows:
a diode-clamped back-to-back bridgeless three-level rectifier comprising:
switch tube S1、S2、S3、S4Diode D1、D2、D3、D4、D5、D6Inductor L, capacitor C1、C2；
One side of the AC power supply is connected with one end of an inductor L, and the other end of the inductor L is respectively connected with a switch tube S1Drain electrode, diode D1Anode, diode D2A cathode;
the other side of the AC power supply is respectively connected with a switch tube S2Drain electrode, switching tube S3Source electrode, switch tube S4A drain electrode;
switch tube S1Source electrode connecting switch tube S2A source electrode;
diode D1The cathodes are respectively connected with a diode D3Cathode and capacitor C1One end;
diode D2The anodes are respectively connected with a diode D4Anode and capacitor C2The other end;
switch tube S3The drain electrodes are respectively connected with a diode D3Anode, diode D5A cathode;
switch tube S4The source electrodes are respectively connected with a diode D4Cathode, diode D6An anode;
capacitor C1The other end is respectively connected with a diode D5Anode, diode D6Cathode, capacitor C2One end;
the two ends of the load R are respectively connected with a capacitor C1One terminal, capacitor C2And the other end.
Wherein, 4 full control power switch tubes: s1、S2、S3、S 46 common diodes: d1、D2、D3、D4、D5、D6And a diode clamp circuit composed of these switching devices and diodes.
Comprising an inductor L and a switching tube S1、S2Forming back-to-back branches.
By semiconductor bidirectional switches S3、S4Diode D1、D2、D3、D4Capacitors C in series1、C2To form a single-phase three-level arrangement structure.
Composed of diode group D5、D6Forming a diode clamping structure.
By a capacitor C1、C2The output side of the voltage stabilizing branch is connected in parallel.
The rectifying circuit of the invention is a semiconductor two-way switch S1、S2、S3、S4、D5、D6(ii) a Rectifier diode D1、D2、D3、D4And its parallel capacitor C1、C2The composition is as follows.
The rectification loop included in the three-level rectification circuit is improved on the traditional single-phase three-level rectification bridge, and a circuit construction method of a bridgeless back-to-back bidirectional switch circuit tube is introduced.
A rectifying loop included in the rectifier circuit is improved on a traditional back-to-back bridgeless rectifying bridge, and a group of clamping diodes are added at the midpoint of a series capacitor to clamp the midpoint voltage of the series capacitor group.
The rectifier circuit charges two diode clamping capacitors respectively through conversion of working modes, so that the output voltage of a direct current side is stabilized, and the input end of the rectifier circuit has three voltage levels.
The rectifier circuit has the advantages that a back-to-back switch tube structure is added in the traditional bridgeless rectification structure, the problem of reverse recovery of diodes of a switch tube body is solved, the reliability is high, the efficiency is high, and the like.
Because the operating characteristic of power frequency alternating grid voltage, for guaranteeing three level rectifier circuit output voltage's stability, need adjust different working mode in the electric wire netting voltage interval of difference:
1) mode 1: switch tube S1、S2、S3Off, S4Conducting, diode D1、D4Working in the on state, the loop flows through the capacitor C1、C2At this time, the grid voltage us<Udc. The current on the inductor L cannot suddenly change, so that the capacitor C1、C2Clamping the voltage at the load terminal to UdcOn the inductor L, a balance voltage u is generatedab＝Udc. At this time, the inductor releases energy, the current on the inductor L is reduced, and the capacitor C1、C2And (6) charging.
2) Mode 2: switch tube S1、S2、S4Off, S3And conducting. Diode D1、D5Working in the on state, the loop flows through the capacitor C1. When the grid voltage us<+UdcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L1Clamping the ab-terminal voltage to UdcAt/2, a balanced voltage u is generated on the inductor Lab＝Udc/2. At this time, the inductor releases energy, the current on the inductor L is reduced, and the capacitor C1Charging, capacitance C2Discharging; when the grid voltage us>+UdcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L1Clamping the voltage at the ab terminal to UdcAt/2, a balanced voltage u is generated on the inductor Lab＝Udc/2. At this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C1Charging, capacitance C2And (4) discharging.
3) Modality 3: switch tube S3、S4Are all turned off, S1、S2And conducting. The diodes in the circuit are all cut off, and the power grid and the load have no power channel. The network voltage is now 0<us<+Udc/2. The current on the inductor L cannot suddenly change, so that the capacitor C1、C2Clamping the voltage at the load terminal to UdcOn the inductor L, a balance voltage u is generatedab0. At this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C1、C2And (4) discharging.
4) Modality 4: switch tube S1、S2、S4Off S3Conducting, diode D2、D3Working in the on state, the loop flows through the capacitor C1、C2At this time, the grid voltage us<-Udc/2. The current on the inductor L cannot suddenly change, so that the capacitor C1、C2Clamping the voltage at the load terminal to UdcOn the inductor L, a balanced voltage is generated to make-uab＝Udc. At this time, the inductor releases energy, the current on the inductor L is reduced, and the capacitor C1、C2And (6) charging.
5) Mode 5: switch tube S1、S2、S3Off, S4And conducting. Diode D2、D6Working in the on state, the loop flows through the capacitor C2. When the grid voltage us>-UdcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L2Clamping the ab-terminal voltage to UdcAt/2, a balanced voltage is generated at the inductor L to make-uab＝Udc/2. At this time, the inductor releases energy, the current on the inductor L is reduced, and the capacitor C2Charging, capacitance C1Discharging; when the grid voltage us<-UdcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L2Clamping the voltage at the ab terminal to UdcAt/2, a balanced voltage is generated at the inductor L to make-uab＝Udc/2. At this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C2Charging, capacitance C1And (4) discharging.
6) Modality 6: switch tube S3、S4Are all turned off, S1、S2And conducting. The diodes in the circuit are all cut off, and the power grid and the load have no power channel. At this time, the grid voltage is 0<us<-Udc/2. The current on the inductor L cannot suddenly change, so that the capacitor C1、C2Clamping the voltage at the load terminal to UdcOn the inductor L, a balance voltage u is generatedab0. The inductor absorbs energy at this time, and the inductorIncrease of current on L, capacitance C1、C2And (4) discharging.
The charging and discharging operation can be carried out on the direct current bus side capacitor by changing the state of the switching tube, and the direct current side voltage is stabilized in a relatively ideal state. The conversion of the respective operating modes follows the mode of the PWM (pulse width modulation) pair circuit and the selected pair of operating times. In the proposed circuit, during the positive half-cycle of the network, the circuit has a Udc、UdcThe working states of the three voltage levels of/2 and 0 correspond to a mode 1, a mode 2 and a mode 3 respectively:
the invention discloses a diode clamping type back-to-back bridgeless three-level rectifier, which has the following technical effects:
1) the three-level rectification of the invention clamps the middle point of a series capacitor by a diode group, clamps the voltage by the capacitor, stabilizes the voltage of an alternating current power supply and outputs stable output voltage.
2) The three-level rectification utilizes the energy storage characteristic of the inductor, and utilizes the characteristic that the current on the inductor L can not change suddenly to match the diode and the voltage clamping capacitor to carry out three-level rectification, thereby maintaining the stable voltage of the bus and ensuring that the voltage fluctuation output by the direct current bus is very small.
3) Compared with the traditional two-level rectifier circuit, the voltage stress requirement on circuit elements is reduced.
4) Because the series diode is used for directly clamping the voltage of the capacitor, the voltage stress born by the switching tube is reduced, and the cost of the switching tube is reduced.
5) Two polar capacitors are used in series, and the voltage of the capacitor is reduced.
6) When the rectifying circuit works, the number of the semiconductor devices flowing through is not more than 3, and the working loss of the circuit is small.
7) The working mode of the circuit is switched by only changing one switching tube, thereby effectively reducing the switching loss of the circuit.
8) The direct current bus is connected in series by two capacitors to work, and output current ripples are effectively reduced.
Drawings
FIG. 1 is a main topology structure diagram of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;
FIG. 2 is a diagram of a working mode of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;
FIG. 3 is a diagram of a second working mode of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;
FIG. 4 is a diagram of a three-level circuit operation mode of a diode-clamped back-to-back bridgeless three-level rectifier according to the present invention;
FIG. 5 is a diagram of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;
FIG. 6 is a five-diagram of the working mode of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;
FIG. 7 is a six-diagram of the working mode of a diode-clamped back-to-back bridgeless three-level rectifier circuit according to the present invention;
FIG. 8 shows a circuit switch S of the present invention1～S4Six working mode diagrams;
FIG. 9 shows the circuit voltage U of the present inventionabA waveform diagram;
FIG. 10 shows the AC-side input voltage U of the circuit of the present inventionsAnd current iLA waveform diagram;
FIG. 11 shows the DC output voltage U of the circuit of the present inventiondcAnd (4) waveform diagrams.
FIG. 12(1) shows a switch tube S of the circuit of the present invention1A pulse distribution map;
FIG. 12(2) shows a switch tube S of the circuit of the present invention2A pulse distribution map;
FIG. 12(3) shows a switch tube S of the circuit of the present invention3A pulse distribution map;
FIG. 12(4) shows a switch tube S of the circuit of the present invention4A pulse distribution diagram.
Detailed Description
As shown in fig. 1, a diode-clamped back-to-back bridgeless three-level rectifier includes: back-to-back structure, diode clamping voltage-stabilizing structure, single-phase three-level structure.
The back-to-back structure comprises two power switchesTube: s1、S2The two switch tubes form a back-to-back bidirectional switch structure.
The diode clamping voltage stabilizing structure is composed of a diode group D5、D6To series capacitor group C1、C2The midpoint voltage is regulated by clamping.
The structure of the diode-clamped back-to-back bridgeless three-level rectifier comprises 4 diodes D1、D2、D3、D 42 power switches S3、S4Capacitor C1、C2. Diode D1Anode of (2) is connected to (D)2A connection point of the cathode is connected with one end of an alternating current power supply and one end of a back-to-back bidirectional switch, and a diode D3Anode and full-controlled switch tube S3Is connected with the source electrode of the switching tube S3And S4The source electrode of the diode D forms a connection point and is connected with the other end of the power supply4Cathode and full-control type switch tube S4The drain electrodes of the two electrodes are connected; capacitor C1Positive electrode and capacitor C2Are respectively connected with a load, a diode D3Cathode connection capacitor C1Anode of (2), diode D4Anode connected capacitor C2The negative electrode of (1); back-to-back bidirectional 2 full-control type switch tubes S1、S2(ii) a Clamping diode D5Anode and clamp diode D6Cathode connected, diode D5、D6Connecting point and series capacitor C1、C2Are connected to each other.
The specific experimental parameters were as follows:
a power grid voltage effective value in an input side of a diode clamping type back-to-back bridgeless three-level rectifier is 220V, the frequency is 50Hz, the output voltage of a direct current side is 400V, the switching frequency is 20kHz, the filter inductance L is 3mH, and a load R is connected with a load RLHas a resistance value of 80 omega, and an output capacitor C1＝C2＝4700μF。
Due to the working characteristics of the public power grid, in order to ensure the stability of the output voltage of the three-level rectification circuit, different working modes need to be adjusted in different power grid voltage intervals:
1) mode 1: as shown in fig. 2, the switching tube S4And the other switching tubes are switched on and off. u. ofs>+Udc/2,uab＝UdcThe inductor L releases energy, iLGradually decreasing, capacitance C1、C2And (6) charging.
2) Mode 2: as shown in fig. 3, the switching tube S3And the other switching tubes are switched on and off. Since modality 2 has two operating states, it needs to be discussed case by case.
At us>+UdcAt/2, uab＝Udc/2, when the inductance L absorbs energy, iLGradually increased, capacitance C1Charging, C2And (4) discharging.
At us<+UdcAt/2, uab＝Udc/2, when the inductor L releases energy, iLGradually decreasing, capacitance C1Charging, C2And (4) discharging.
3) Modality 3: as shown in fig. 4, the switching tube S1、S2And the other switching tubes are switched on and off. 0<us<+Udc/2，uabWhen 0, the inductance L absorbs energy, iLGradually increased, capacitance C1、C2And (4) discharging.
4) Modality 4: as shown in fig. 5, the switching tube S3And the other switching tubes are switched on and off. u. ofs<-Udc/2，uab＝UdcInductor L releases energy, iLGradually decreasing, capacitance C1、C2And (6) charging.
5) Mode 5: as shown in fig. 6, the switching tube S4And the other switching tubes are switched on and off. Since modality 2 has two operating states, it needs to be discussed case by case.
At us<-UdcAt/2, uab＝Udc/2, when the inductance L absorbs energy, iLGradually increased, capacitance C2Charging, C1And (4) discharging.
At 0>us>-UdcAt/2, uab＝Udc/2, when the inductor L releases energy, iLGradually decreasing, capacitance C2Charging, C1And (4) discharging.
6) Modality 6: as shown in fig. 7, the switching tube S1、S2And the other switching tubes are switched on and off. 0>us>-Udc/2，uabInductance absorbs energy, i ═ 0LGradually increased, capacitance C1、C2And (4) discharging.
Series capacitor bank C in the above working mode1、C2The DC output power supply has the function of stabilizing the voltage of the DC side output load all the time, and realizes the voltage stabilization output of DC power supplies with different output voltages by matching with the adjustment of parameters.
Fig. 8, 9, 10 and 11 are experimental waveforms of the present invention when the load is 80 Ω, and are related waveforms of the present invention in a steady state.
FIG. 8 shows a circuit switch S of the present invention1～S4Six working mode diagrams; the on state of the switch tube is represented by 1, and the off state of the switch tube is represented by 0. According to the invention, different ab-end output voltages U are obtained by changing the circuit structure through the combination of on-off of different switching tubesab. The output rated voltage is represented by +/-1, +/-1/2 and 0, and the ab terminal voltage is 0. FIG. 9 shows the circuit voltage U of the present inventionabA waveform diagram; on the basis of FIG. 8, the switch tube S is switched by the pair circuit1～S4The on/off state of the invention is modulated on a direct current bus UdcWhen the rated output voltage is 400V, the voltage at the ab end can output rated voltage which is half of the rated voltage and 0 voltage grade, namely voltages of +/-400V, +/-200V and 0V. FIG. 10 shows the AC-side input voltage U of the circuit of the present inventionsAnd current iLA waveform diagram; showing the steady-state AC input voltage U of the inventionsThe waveform keeps changing in a sine rule; AC input current iLWaveform following AC input voltage UsThe waveform is stable and approaches to a sine wave, and the voltage and current phases of the circuit are basically the same through experimental waveform comparison, so that the power factor correction function can be realized.
FIG. 11 shows the DC output voltage U of the circuit of the present inventiondcA waveform diagram; shows that the invention outputs when the rated voltage is 400VThe obtained voltage U on the side of the DC busdcThe steady state waveform of (a).
FIG. 12(1) shows a switch tube S of the circuit of the present invention1A pulse distribution map; for the switching tube S of the invention1Switching pulse voltage US1And the waveform diagram shows a switching pulse distribution signal, namely the driving voltage for switching on and off the switching tube. When the voltage of the switch tube reaches 12V, the switch tube is conducted corresponding to the signal 1 in FIG. 8. When the voltage of the switch tube reaches 0V, the switch tube is turned off corresponding to the 0 signal in fig. 8.
FIG. 12(2) shows a switch tube S of the circuit of the present invention2A pulse distribution map; for the switching tube S of the invention2Switching pulse voltage US2And the waveform diagram shows a switching pulse distribution signal, namely the driving voltage for switching on and off the switching tube. When the voltage of the switch tube reaches 12V, the switch tube is conducted corresponding to the signal 1 in FIG. 8. When the voltage of the switch tube reaches 0V, the switch tube is turned off corresponding to the 0 signal in fig. 8.
FIG. 12(3) shows a switch tube S of the circuit of the present invention3A pulse distribution map; for the switching tube S of the invention3Switching pulse voltage US3And the waveform diagram shows a switching pulse distribution signal, namely the driving voltage for switching on and off the switching tube. When the voltage of the switch tube reaches 12V, the switch tube is conducted corresponding to the signal 1 in FIG. 8. When the voltage of the switch tube reaches 0V, the switch tube is turned off corresponding to the 0 signal in fig. 8.
FIG. 12(4) shows a switch tube S of the circuit of the present invention4A pulse distribution map; for the switching tube S of the invention4Switching pulse voltage US4And the waveform diagram shows a switching pulse distribution signal, namely the driving voltage for switching on and off the switching tube. When the voltage of the switch tube reaches 12V, the switch tube is conducted corresponding to the signal 1 in FIG. 8. When the voltage of the switch tube reaches 0V, the switch tube is turned off corresponding to the 0 signal in fig. 8.

Claims (1)

1. A control method of a diode clamping type back-to-back bridgeless three-level rectifier is characterized in that: the three-level rectifier comprises a switching tube S1、S2、S3、S4Diode D1、D2、D3、D4、D5、D6Inductor L, capacitor C1、C2；
One side of the AC power supply is connected with one end of an inductor L, and the other end of the inductor L is respectively connected with a switch tube S1Drain electrode, diode D1Anode, diode D2A cathode, the connection node of which constitutes an end a;
the other side of the AC power supply is respectively connected with a switch tube S2Drain electrode, switching tube S3Source electrode, switch tube S4A drain connected to the node to form an end point b;
switch tube S1Source electrode connecting switch tube S2A source electrode;
diode D1The cathodes are respectively connected with a diode D3Cathode and capacitor C1One end;
diode D2The anodes are respectively connected with a diode D4Anode and capacitor C2The other end;
switch tube S3The drain electrodes are respectively connected with a diode D3Anode, diode D5A cathode;
switch tube S4The source electrodes are respectively connected with a diode D4Cathode, diode D6An anode;
capacitor C1The other end is respectively connected with a diode D5Anode, diode D6Cathode and capacitor C2One end;
the two ends of the load R are respectively connected with a capacitor C1One terminal, capacitor C2The other end;
the control method of the three-level rectifier comprises the following steps: different working modes are adjusted in different power grid voltage intervals:
1) mode 1: switch tube S1、S2、S3Off, S4Conducting, diode D1、D4When operating in the on state, the loop passes through the capacitor C1、C2At this time, the grid voltage us<Udc；UdcFor the voltage across the load R, the capacitor C is connected to the inductor L1、C2Clamping the voltage at the load terminal to UdcUpper, lower electricityA balance voltage u is generated on the inductor Lab＝Udc；uabIs the voltage between the terminals a and b, when the inductor releases energy, the current on the inductor L decreases, and the capacitor C1、C2Charging;
2) mode 2: switch tube S1、S2、S4Off, S3Conducting; diode D1、D5When operating in the on state, the loop passes through the capacitor C1(ii) a When the grid voltage us<+UdcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L1Clamping the voltage between terminals a and b at UdcAt/2, a balanced voltage u is generated on the inductor Lab＝Udc2; at this time, the inductor releases energy, the current on the inductor L is reduced, and the capacitor C1Charging, capacitance C2Discharging; when the grid voltage us>+UdcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L1Clamping the voltage between the terminals a and b at UdcAt/2, a balanced voltage u is generated on the inductor Lab＝Udc2; at this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C1Charging, capacitance C2Discharging;
3) modality 3: switch tube S3、S4Are all turned off, S1、S2Conducting; diodes in the circuit are all cut off, and a power channel does not exist between a power grid and a load; the network voltage is now 0<us<+Udc2; the current on the inductor L can not change suddenly, and the capacitor C1、C2Clamping the voltage at the load terminal to UdcOn the inductor L, a balance voltage u is generatedab0; at this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C1、C2Discharging;
4) modality 4: switch tube S1、S2、S4Off S3Conducting, diode D2、D3When operating in the on state, the loop passes through the capacitor C1、C2At this time, the grid voltage us<-Udc2; due to the inductance LThe current on cannot suddenly change, the capacitor C1、C2Clamping the voltage at the load terminal to UdcOn the inductor L, a balanced voltage is generated to make-uab＝Udc(ii) a At this time, the inductor releases energy, the current on the inductor L is reduced, and the capacitor C1、C2Charging;
5) mode 5: switch tube S1、S2、S3Off, S4Conducting; diode D2、D6When operating in the on state, the loop passes through the capacitor C2(ii) a When the grid voltage us>-UdcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L2Clamping the voltage between terminals a and b at UdcAt/2, a balanced voltage is generated at the inductor L to make-uab＝Udc2; at this time, the inductor releases energy, the current on the inductor L is reduced, and the capacitor C2Charging, capacitance C1Discharging; when the grid voltage us<-UdcAt/2, the capacitor C cannot change suddenly due to the current on the inductor L2Clamping the voltage between the terminals a and b at UdcAt/2, a balanced voltage is generated at the inductor L to make-uab＝Udc2; at this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C2Charging, capacitance C1Discharging;
6) modality 6: switch tube S3、S4Are all turned off, S1、S2Conducting; diodes in the circuit are all cut off, and a power channel does not exist between a power grid and a load; the network voltage is now 0<us<-Udc2; the current on the inductor L cannot suddenly change, so that the capacitor C1、C2Clamping the voltage at the load terminal to UdcOn the inductor L, a balance voltage u is generatedab0; at this time, the inductor absorbs energy, the current on the inductor L increases, and the capacitor C1、C2And (4) discharging.
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