CN112864328B - Ag/C 60 Per P3HT/n-GaN/In planar heterojunction material and preparation method thereof - Google Patents

Ag/C 60 Per P3HT/n-GaN/In planar heterojunction material and preparation method thereof Download PDF

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CN112864328B
CN112864328B CN202110120380.2A CN202110120380A CN112864328B CN 112864328 B CN112864328 B CN 112864328B CN 202110120380 A CN202110120380 A CN 202110120380A CN 112864328 B CN112864328 B CN 112864328B
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孙文红
王家斌
杨亚
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Abstract

The invention discloses Ag/C 60 the/P3 HT/n-GaN/In planar heterojunction material comprises a substrate, an n-GaN thin film layer, a P3HT layer, and a C layer 60 The preparation method of the layer, the Ag layer and the In electrode comprises the following steps: growing an n-GaN thin film layer on the substrate by MOCVD, spin-coating a P3HT solution on the n-GaN thin film layer to obtain a P3HT layer, and vapor-plating C on the P3HT layer 60 To obtain C 60 Layer at C 60 Evaporating Ag on the layer to obtain an Ag layer; then the material and indium are annealed on the n-GaN film layer In a nitrogen atmosphere by a two-step method to prepare an In electrode, and the Ag/C is obtained 60 the/P3 HT/n-GaN/In planar heterojunction material. The current of the material can reach a stable value more quickly under a certain voltage intensity, and the material has excellent electrical properties; the preparation process has the advantages of simple steps, short time consumption and low cost, and is very suitable for large-scale production and application.

Description

Ag/C 60 /P3HT/n-GaN/In planar heterojunction material and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor materials, and particularly relates to Ag/C 60 a/P3 HT/n-GaN/In planar heterojunction material and a preparation method thereof.
Background
In recent years, research on organic-inorganic semiconductor materials has been extremely active, and the organic-inorganic semiconductor materials have shown wide application prospects in information display, photovoltaic cells, and the like. Organic-inorganic p-n junctions are applications that take advantage of the respective advantages of organic and inorganic semiconductors to improve optoelectronic devices. Organic semiconductors are not only simple in manufacturing processes such as spin coating, screen printing, ink jet printing, and spray coating, but also have good optical characteristics, and are widely used in rectifier diodes and photoelectric devices. Inorganic semiconductors have good electrical properties, such as high carrier mobility and controllable conductivity.
Poly-3 hexylthiophene (P3-hexylthiophene), P3HT, is one of the most well-known P-type polymers and has very high carrier mobility. Gallium nitride (GaN) is a wide band gap (E at room temperature) g 3.4eV), which has the advantages of high strength, high melting point, as well as high breakdown field strength and extremely high chemical stability, has been used in the research of short wavelength optical devices and high power electronic devices. At present, the researchers are workingAn inorganic-organic hybrid structure is designed to combine the advantages of each of the above materials to save cost and simplify the manufacturing process, thereby manufacturing a device with high efficiency. The Hu Li Feng uses P3HT and n-GaN to construct a P3HT/n-GaN planar heterojunction and a P3HT/n-PGaN bulk heterojunction, and the Rectification Ratios (RR) of the two structures are respectively 62 and 1443. Chen et al constructed C 60 a/n-GaN planar heterojunction having a rectification ratio in excess of 10 6 . How to further improve the electrical performance of the planar heterojunction material on this basis is a hot spot of current research.
Disclosure of Invention
Aiming at the technical problems, the invention provides Ag/C 60 a/P3 HT/n-GaN/In planar heterojunction material and a preparation method thereof.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
Ag/C 60 a/P3 HT/n-GaN/In planar heterojunction material comprising: substrate, n-GaN thin film layer, P3HT layer, and C 60 Layer, Ag layer and In electrode.
The substrate is made of sapphire;
wherein the n-GaN thin film layer is disposed on the substrate; the thickness of the n-GaN thin film layer is 1-2 mu m, and preferably 1.5 mu m;
wherein the P3HT layer and In electrode are disposed on the n-GaN thin film layer; the thickness of the P3HT layer is 80-120 nm, and preferably 100 nm;
wherein, the C 60 A layer disposed on the P3HT layer; said C is 60 The thickness of the layer is 30-70 nm, preferably 50 nm;
wherein the Ag layer is disposed on the C 60 On the layer; the thickness of the Ag layer is 80-120 nm, and preferably 100 nm.
The invention also provides the Ag/C 60 The preparation method of the/P3 HT/n-GaN/In planar heterojunction material comprises the following steps:
(1) growing an n-GaN thin film layer on a substrate by MOCVD;
(2) spin coating the solution of P3HT on the n-GaN thin film layer to obtain a P3HT layer;
(3) vapor plating C on P3HT layer 60 To obtain C 60 Layer at C 60 Evaporating Ag on the layer to obtain an Ag layer;
(4) putting the material prepared In the step (3) and indium into a rapid annealing furnace, annealing the material and the indium on the n-GaN thin film layer In a nitrogen atmosphere by a two-step method to prepare an In electrode, annealing at 180-220 ℃ for 3-7 min In the first step, and annealing at 280-320 ℃ for 6-10 min In the second step; to obtain Ag/C 60 the/P3 HT/n-GaN/In planar heterojunction material.
In the step (1), after an n-GaN thin film layer grows on a substrate by MOCVD, acetone, alcohol and deionized water are respectively used for ultrasonic cleaning, and then cleaning is carried out in an ultraviolet cleaning machine.
In the step (2), P3HT is firstly dissolved in chlorobenzene to obtain a P3HT solution with the mass fraction of 1.1 wt%, and then the P3HT layer is obtained by spin-coating the P3HT solution on the n-GaN thin film layer for 60s at the rotating speed of 1500 rpm/s.
In the step (2), after the P3HT layer is prepared, heating the material at 140-145 ℃ for 10min to evaporate chlorobenzene; further, the heating temperature is preferably 142 ℃.
In the step (3), a metal organic evaporation system is used for evaporating C on the P3HT layer 60 To obtain C 60 Layer at C 60 And evaporating Ag on the layer to obtain an Ag layer.
Wherein, in the step (4), the first step is carried out for 5min at 200 ℃, and the second step is carried out for 8min at 300 ℃.
Compared with the prior art, the invention has the following beneficial effects:
(1) ohmic contact is formed between the In and the n-GaN thin film layer through a two-step annealing method, no rectification phenomenon is generated between the In and the n-GaN thin film layer, only the rectification function of a P-n structure formed between the P3HT layer and the n-GaN thin film layer is reserved, and the rectification function of the whole material is not influenced;
(2)C 60 due to the addition of the layers, the reverse saturation current and the parallel resistance of the material are reduced, the defect density can be reduced, the current of the material can reach a stable value more quickly under a certain voltage intensity, and the electrical property of the material is improved;
(3) the preparation process has the advantages of simple steps, short time consumption and low cost, and is very suitable for large-scale production and application.
Drawings
FIG. 1 shows Ag/C of the present invention 60 The structure schematic diagram of the/P3 HT/n-GaN/In planar heterojunction material is shown In the reference numeral: 1-substrate, 2-n-GaN film layer, 3-P3HT layer, 4-In electrode, 5-C 60 Layer, 6-Ag layer.
FIG. 2 is a schematic structural diagram of Ag/P3HT/n-GaN/In planar heterojunction material, with reference numbers: the GaN-based solar cell comprises a 1-substrate, a 2-n-GaN thin film layer, a 3-P3HT layer, a 4-In electrode and a 5-Ag layer.
FIG. 3 is an I-V curve of In/n-GaN/In on an n-GaN film.
FIG. 4 is an I-V plot of forward bias and reverse bias on a semi-logarithmic scale for the sample.
FIG. 5 is a sample resistance (R) i ) The variation curve with applied voltage.
FIG. 6 is a graph of dV/d (lnI) -I and H (I) -I for two samples.
FIG. 7 is an I-V curve of a sample in log-log coordinates.
Detailed Description
The following detailed description is to be read in connection with the accompanying drawings, but it is to be understood that the scope of the invention is not limited to the specific embodiments. The raw materials used in the examples were all commercially available unless otherwise specified.
EXAMPLE 1 preparation of Ag/C 60 P3HT/n-GaN/In planar heterojunction material
(1) After an n-GaN thin film layer with a thickness of 1.5 μm is grown on a substrate by MOCVD (Metal-organic Chemical Vapor Deposition), ultrasonic cleaning is respectively performed by acetone, alcohol and deionized water, and then cleaning is performed in an ultraviolet cleaning machine;
(2) dissolving P3HT in chlorobenzene to obtain a P3HT solution with the mass fraction of 1.1 wt%, and spin-coating the P3HT solution on the n-GaN thin film layer for 60s at the rotating speed of 1500rpm/s to obtain a P3HT layer, wherein the thickness of the P3HT layer is 100 nm; the material was then heated at 142 ℃ for 10min to evaporate the chlorobenzene;
(3) vapor plating C on P3HT layer by metal organic vapor plating system 60 To obtain C 60 Layer at C 60 Evaporating Ag on the layer to obtain an Ag layer; said C is 60 The layer thickness is 50 nm; the thickness of the Ag layer is 100 nm;
(4) putting the material prepared In the step (3) and indium into a rapid annealing furnace, annealing the material and the indium on the n-GaN thin film layer In a nitrogen atmosphere by a two-step method to prepare an In electrode, annealing the material and the indium at 200 ℃ for 5min In the first step, and annealing the material and the indium at 300 ℃ for 8min In the second step, wherein the diameter of the obtained In electrode is 1 mm; to obtain Ag/C 60 the/P3 HT/n-GaN/In planar heterojunction material.
Prepared Ag/C 60 The structure of the/P3 HT/n-GaN/In planar heterojunction material is shown In figure 1.
COMPARATIVE EXAMPLE 2 preparation of Ag/P3HT/n-GaN/In planar heterojunction Material
(1) After an n-GaN thin film layer with a thickness of 1.5 μm was grown on a substrate by MOCVD (Metal-organic Chemical Vapor Deposition), ultrasonic cleaning was performed with acetone, alcohol and deionized water, respectively, and then cleaning was performed in an ultraviolet cleaner;
(2) dissolving P3HT in chlorobenzene to obtain a P3HT solution with the mass fraction of 1.1 wt%, and spin-coating the P3HT solution on the n-GaN thin film layer for 60s at the rotating speed of 1500rpm/s to obtain a P3HT layer, wherein the thickness of the P3HT layer is 100 nm; the material was then heated at 142 ℃ for 10min to evaporate the chlorobenzene;
(3) utilizing a metal organic evaporation system to evaporate Ag on the P3HT layer to obtain an Ag layer; the thickness of the Ag layer is 100 nm;
(4) putting the material prepared In the step (3) and indium into a rapid annealing furnace, annealing the material and the indium on the n-GaN thin film layer In a nitrogen atmosphere by a two-step method to prepare an In electrode, annealing the material and the indium at 200 ℃ for 5min In the first step, and annealing the material and the indium at 300 ℃ for 8min In the second step, wherein the diameter of the obtained In electrode is 1 mm; thus obtaining the Ag/P3HT/n-GaN/In planar heterojunction material.
The structure of the prepared Ag/P3HT/n-GaN/In planar heterojunction material is shown In figure 2.
Example 3 Performance testing
The I-V curves of the samples of examples 1 and 2 were examined using a Keithley 2400 SourceMeter in a dark and room temperature environment. All measurements were performed immediately after sample preparation to avoid changes in electrical properties due to aging, contamination. The detection results are as follows:
1. the I-V curve of In/n-GaN/In on the n-GaN thin film is shown In fig. 3, and the I-V curve of fig. 3 is a straight line of zero-crossing points, so that it can be confirmed that ohmic contact is made between the In electrode and the n-GaN, and resistances of 34.483 Ω and 30.303 Ω, respectively, are obtained.
2. The I-V curves of the forward bias and the reverse bias of the samples of example 1 and example 2 in semilogarithmic coordinates are shown in fig. 4, and as shown in fig. 4, both samples produced nonlinear, asymmetric I-V curves, exhibiting good rectifying characteristics, which are characteristic of the Thermionic Emission (TE) current. The non-linear I-V curve is due to interface state density, series resistance (R) s ) And the value of the ideality factor (n). In view of these influencing factors, according to thermionic emission theory, the relationship of I-V can be expressed by the following equation:
Figure BDA0002922133300000051
wherein, V, IR s N, k and T are respectively the forward bias voltage, the voltage drop of the diode series resistance, the ideality factor, the Boltzmann constant and the Kelvin temperature. I is 0 Is the reverse saturation current, which can be derived from the straight line intercept of the lnI-V plot when V is 0, and can be expressed as:
Figure BDA0002922133300000052
wherein A is the junction area, A * Effective Richardson constant (n-GaN of 26.4 Acm) -2 K -2 ),φ B0 Is the barrier height at 0 bias and can be expressed as:
Figure BDA0002922133300000053
the ideality factor n, which represents the deviation of an actual diode from the ideal TE theory, can be obtained from the slope of the linear region in the I-V characteristic on the semilogarithmic graph by the following relationship,
Figure BDA0002922133300000054
therefore, the ideality factor n and the reverse saturation current I can be obtained from FIG. 4 0 The value of (3) can be used to calculate the barrier height φ under 0 bias B0 The calculated values are in table 1. Can be derived from the table because C 60 Existence of a layer, an ideality factor n and a barrier height phi B0 Increased value of (d), reverse saturation current I 0 And decreases. The reason for the increase in n may be: Ag/C 60 The density of interface state at the interface is higher than that of Ag/P3HT, the influence of non-uniformity of a potential barrier exists, and the tunneling effect, Ag/C 60 The pressure drop present at the interface is higher than that of Ag/P3 HT. From the rectification ratio, the rectification characteristic of the I-V curve can be analyzed. The rectification ratio is the ratio of forward bias current to reverse bias current under fixed voltage (+ -2V) and is 1.273 × 10 6 And 1.282 × 10 5 ；
TABLE 1 calculation of experimental values of diode parameters from forward biased I-V characteristics by different methods
Figure BDA0002922133300000061
The I-V curve is also influenced by its half-life resistance-series resistance R s And a parallel resistor R sh The influence of (c). The parallel resistance is related to the P3HT/n-GaN interface, and the series resistance is related to Ag/P3HT or Ag/C 60 The interfaces are related. The parallel resistance can be represented by the formula
Figure BDA0002922133300000062
Obtained when V is 0. The series resistance is the sum of the total resistance of the ohmic contacts and the resistance of the semiconductor depletion region. In an ideal diode, the series resistance is very large and reaches M omega level
Figure BDA0002922133300000063
Tending towards 0 as the forward bias increases. However, the generation and recombination of carriers in the depletion region, high injection conditions and imperfect ohmic contact all significantly affect the forward current. As shown in FIG. 4, R sh And R s Can pass through R in the figure i vsV, is determined from the graph. To obtain R sh And R s The values of (A) are shown in Table 1, R i Are almost equal, however, R of the sample of example 1 sh The values are significantly smaller than the sample of example 2, probably due to C 60 The presence of a resistor at the/P3 HT interface in parallel relationship with the resistance at the P3HT/n-GaN interface results in a reduced parallel resistance of the entire device.
4. Sample resistance (R) i ) The curve with applied voltage is shown in FIG. 5. In fig. 4, the forward bias I-V characteristics of the two samples have linear characteristics on a semi-logarithmic scale at low forward bias voltages, and are non-linear I-V curves with downward curvature at high bias voltages. This characteristic results in two linear regions in the forward bias ln i-V plot, with high slope values in the low bias regions and smaller slope values in the high bias regions. Another method proposed by Cheung and Cheung to calculate R of the nonlinear region of the lnI-V curve under forward bias s 、φ B0 And n. According to the function of Cheung, considering the forward bias, when V is more than 3kT/q, the diode has junction resistance, and R is combined with a thermionic emission model s 、φ B0 And the value of n can be obtained by the following formula,
Figure BDA0002922133300000071
Figure BDA0002922133300000072
H(I)＝IR s +nΦ B (7)
from the formulas (5) and (6), it can be seen that dV/d (lnI) -I and H (I) -I are linearThe relationship (fig. 6). Thus, R s And n can be determined from the slope and intercept of dV/d (lnI) -I, phi B0 Can be determined by the intercept of H (I) -I. It can be seen from table 1 that the value of n determined by the forward bias ln I-V plot is lower than the value of n derived from the dV/d (ln I) -I plot. This may be due to the low voltage region interface states varying with bias and series resistance.
4. The I-V curve of the sample in log-log coordinates is shown in FIG. 7. in FIG. 7, three different linear regions represent different charge transfer mechanisms. These regions have different slopes for the two samples. In these regions, the current is proportional to the voltage, I ^ V m And m is the slope of the line. From the value of m, the dominant current conduction mechanism of the sample is space-charge limited current (SCLC) controlled by the trap. As can be seen from the change in m value, the current change rate of the sample of example 1 is faster than that of example 2, which indicates that the sample of example 1 has fewer trap levels than that of example 2. Therefore, C 60 The presence of the layer can reduce the number of traps.
5. In summary, C 60 The presence of the layer, which reduces the reverse saturation current and the parallel resistance of the organic-inorganic heterojunction, can be considered to be C 60 The presence of a resistor at the/P3 HT interface in parallel relationship with the resistance at the P3HT/n-GaN interface results in a reduced parallel resistance of the overall device. Because of C 60 Layer, ideality factor and barrier height increase, with the increase in ideality factor due to Ag/C 60 The density of interface state at the interface is higher than that of Ag/P3HT, the influence of potential barrier nonuniformity and the existence of tunneling effect, Ag/C 60 The pressure drop existing at the interface is higher than that of Ag/P3 HT. The values of the series resistances obtained by the different methods are almost equal, which indicates that Ag/P3HT and Ag/C 60 The series resistance formed by the interface is not greatly changed due to the change of the organic layer material.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (9)

1. Ag/C 60 a/P3 HT/n-GaN/In planar heterojunction material, comprising: substrate, n-GaN thin film layer, P3HT layer, and C 60 A layer, an Ag layer and an In electrode;
the substrate is made of sapphire; the n-GaN thin film layer is arranged on the substrate; the P3HT layer and the In electrode are arranged on the n-GaN thin film layer; said C is 60 A layer disposed on the P3HT layer; the Ag layer is arranged on the C 60 On the layer;
wherein, ohmic contact is formed between the n-GaN thin film layer and the In electrode through a two-step annealing method: the first step is annealing at 200 deg.C for 5min, and the second step is annealing at 300 deg.C for 8 min.
2. Ag/C according to claim 1 60 the/P3 HT/n-GaN/In planar heterojunction material is characterized In that: the thickness of the n-GaN thin film layer is 1-2 mu m, the thickness of the P3HT layer is 80-120 nm, and C is 60 The thickness of the layer is 30-70 nm, and the thickness of the Ag layer is 80-120 nm.
3. Ag/C according to claim 1 60 the/P3 HT/n-GaN/In planar heterojunction material is characterized In that: the thickness of the n-GaN film layer is 1.5 mu m, the thickness of the P3HT layer is 100nm, and the C layer is 60 The thickness of the layer is 50nm, and the thickness of the Ag layer is 100 nm.
4. Ag/C according to claim 1 60 The preparation method of the/P3 HT/n-GaN/In planar heterojunction material is characterized by comprising the following steps of:
(1) growing an n-GaN thin film layer on a substrate by using MOCVD;
(2) spin coating the P3HT solution on the n-GaN thin film layer to obtain a P3HT layer;
(3) vapor plating C on P3HT layer 60 To obtain C 60 Layer at C 60 Evaporating Ag on the layer to obtain an Ag layer;
(4) putting the material prepared In the step (3) and indium into a rapid annealing furnace, annealing the material and the indium on the n-GaN thin film layer In a nitrogen atmosphere by a two-step method to prepare an In electrode, annealing the material at 200 ℃ for 5min In the first step, and annealing the material at 300 ℃ for 8min In the second step; then Ag/C is obtained 60 the/P3 HT/n-GaN/In planar heterojunction material.
5. The method of claim 4, wherein: in the step (1), after an n-GaN thin film layer grows on a substrate by MOCVD, acetone, alcohol and deionized water are respectively used for ultrasonic cleaning, and then cleaning is carried out in an ultraviolet cleaning machine.
6. The method of claim 4, wherein: in the step (2), P3HT is firstly dissolved in chlorobenzene to obtain a P3HT solution with the mass fraction of 1.1 wt%, and then the P3HT layer is obtained by spin-coating the P3HT solution on the n-GaN thin film layer for 60s at the rotating speed of 1500 rpm/s.
7. The method of claim 4, wherein: in the step (2), after the P3HT layer is prepared, the material is heated at 140-145 ℃ for 10min to evaporate chlorobenzene.
8. The method of claim 7, wherein: the heating temperature was 142 ℃.
9. The method of claim 4, wherein: in the step (3), a metal organic evaporation system is used for evaporating C on the P3HT layer 60 To obtain C 60 Layer at C 60 And evaporating Ag on the layer to obtain an Ag layer.
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