CN112860001B - Fast current mirror circuit - Google Patents

Fast current mirror circuit Download PDF

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CN112860001B
CN112860001B CN202110069683.6A CN202110069683A CN112860001B CN 112860001 B CN112860001 B CN 112860001B CN 202110069683 A CN202110069683 A CN 202110069683A CN 112860001 B CN112860001 B CN 112860001B
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transistor
current
gate
current mirror
mirrors
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CN112860001A (en
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许胜国
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Fiberhome Telecommunication Technologies Co Ltd
Wuhan Fisilink Microelectronics Technology Co Ltd
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Fiberhome Telecommunication Technologies Co Ltd
Wuhan Fisilink Microelectronics Technology Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

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Abstract

The application relates to a fast current mirror circuit, which comprises a current mirror unit and a source follower, wherein the current mirror unit comprises two cascode current mirrors and two current mirrorsOne end of the current mirrors is connected with a power supply VCC after being connected in series, the other end of the current mirrors is grounded, and two connection points of the two current mirrors are respectively connected with an input current IINOutput current IOUT(ii) a The source follower is connected with the grid connection points of the two current mirrors, and is connected with the two current mirrors to input current IINIs used for being dependent on the input current IINThe voltage of the grid connection point of the two current mirrors is dynamically adjusted by the change of the voltage, so that the charging and discharging time of the grid parasitic capacitance is shortened, and the delay of the mirror image output is reduced. The rapid current mirror circuit of the embodiment of the application can meet the application scene with higher requirement on mirror image delay.

Description

Fast current mirror circuit
Technical Field
The present application relates to the field of semiconductor integrated circuit technologies, and in particular, to a fast current mirror circuit.
Background
At present, a current mirror is very commonly applied to the design of various analog circuits, and conventionally, as a static circuit, the mirror accuracy is mainly considered, and when the input current changes, a delay time is required for the output current to be stable. Some applications have strict requirements on such delay, such as in G/EPON burst laser drivers and high-speed current-mode digital-to-analog converters, which require that the output current follows the input current faster.
Referring to fig. 1, a current mirror circuit in the related art is directly composed of two NMOS transistors with a certain ratio in size, which are respectively denoted as NM1 transistor and NM2 transistor, a gate of the NM1 transistor is simultaneously connected to a gate of the NM2 transistor and a drain of the NM1 transistor, and a drain of the NM1 transistor is connected to an input current IINConnected, drain output current I of NM2 tubeOUT。
Considering only the steady state current, let the size ratio of NM1 tube and NM2 tube be 1: n, because the grid potentials of the two NMOS tubes are equal, and the source potentials are both 0, when the NMOS tube works in a saturation region, the steady-state current ratio I isOUT：IIN1, thereby realizing the current mirror design.
When considering current variations, e.g. input current changes from 0 to IINIn the process, the grid voltages of the two NMOS transistors are gradually increased from 0, the voltage increase is realized by charging various parasitic capacitances of the grids, however, the parasitic capacitances of the grids are often larger, the charging time is longer, and particularly, the voltages of the two NMOS transistors are mirroredThe flow is small. Similarly, the input current is from IINWhen the voltage changes to 0, the parasitic capacitance of the gate discharges slowly, and when the gate voltage is lower than the NMOS threshold, the discharge current is greatly reduced, resulting in a longer settling time than charging and a longer delay of the mirror output.
Disclosure of Invention
The embodiment of the application provides a fast current mirror circuit to solve the technical problems of long charging and discharging time of a gate parasitic capacitor and long delay of mirror image output in the related technology.
In a first aspect, a fast current mirror circuit is provided, which includes:
the current mirror unit comprises two cascode current mirrors, one end of the two current mirrors is connected with a power supply VCC after being connected in series, the other end of the two current mirrors is grounded, and two connection points of the two current mirrors are respectively connected with an input current IINOutput current IOUT；
A source follower connected to the gate connection points of the two current mirrors and connected to the input current IINIs used for being dependent on the input current IINThe voltage of the grid connection point of the two current mirrors is dynamically adjusted by the change of the voltage, so that the charging and discharging time of the grid parasitic capacitance is shortened, and the delay of the mirror image output is reduced.
In some embodiments, the source follower comprises a fifth transistor Q5 and a constant current source ISSThe fifth transistor Q5 and a constant current source ISSOne end of the series circuit is connected with a power supply VCC, the other end of the series circuit is grounded, and the fifth transistor Q5 and the constant current source I are connectedSSThe gate of the fifth transistor Q5 is connected to the gate connection of the two current mirrors, respectively, and the gate of the fifth transistor Q5 is connected to the two current mirrors for inputting the current IINAre connected to each other.
In some embodiments, the two current mirrors respectively include a first transistor Q1 and a second transistor Q2 that are mirror images of each other, and a third transistor Q3 and a fourth transistor Q4 that are mirror images of each other, the first transistor Q1 and the third transistor Q3 are connected in series, one end of the first transistor Q1 is connected to the VCC power supply, the other end of the first transistor Q3925 is connected to the ground, the second transistor Q2 and the fourth transistor Q4 are connected in series, and the other end of the second transistor Q2 and the fourth transistor Q4 are connected to the groundThe other end of the first transistor Q1 is connected with the input current I, the other end of the first transistor Q3 is connected with the power supply VCC, and the connecting point of the first transistor Q1 and the third transistor Q3578 is connected with the input current IINThe connection point of the second transistor Q2 and the fourth transistor Q4 is connected with the output current IOUTAre connected.
In some embodiments, the source follower comprises a fifth transistor Q5 and a constant current source ISSThe fifth transistor Q5 and a constant current source ISSOne end of the series circuit is connected with a power supply VCC, the other end of the series circuit is grounded, and the fifth transistor Q5 and the constant current source I are connectedSSThe gates of the fifth transistor Q5 are connected to the gate connection points of the two current mirrors, respectively, and the connection points of the first transistor Q1 and the third transistor Q3 are connected to the gate of the fifth transistor Q5.
In some embodiments, the fifth transistor Q5 is a PMOS transistor, the gate connection point NG of the first transistor Q1 and the second transistor Q2 is connected to the gate of the fifth transistor Q5, and the gate connection point PG of the third transistor Q3 and the fourth transistor Q4 is connected to the fifth transistor Q5 and the constant current source ISSAre connected to each other.
In some embodiments, the fifth transistor Q5 is an NMOS transistor, and the gate connection point NG of the first transistor Q1 and the second transistor Q2 is connected to the fifth transistor Q5 and the constant current source ISSAnd the gate connection point PG of the third and fourth transistors Q3 and Q4 is connected to the gate of the fifth transistor Q5.
In some embodiments, the first transistor Q1 and the second transistor Q2 are both NMOS transistors, and the third transistor Q3 and the fourth transistor Q4 are both PMOS transistors.
In some embodiments, each current mirror includes two cascode transistors, where two transistors of one current mirror are both PMOS transistors, and two transistors of the other current mirror are both NMOS transistors.
In some embodiments, the device parameters of the two transistors of each current mirror are the same.
In some embodiments, the two current mirrors are in the same size ratio.
The beneficial effect that technical scheme that this application provided brought includes: the charging and discharging time of the grid parasitic capacitance is shortened, the delay of mirror image output is reduced, and the application scene with higher requirement on mirror image delay can be met.
The embodiment of the application provides a rapid current mirror circuit, and a source follower is connected with grid connection points of two current mirrors and is connected with an input current I of the two current mirrorsINSo that the source follower can be operated in dependence on the input current IINThe voltage of the grid connection point of the two current mirrors is dynamically adjusted by the change of the voltage, so that the charging and discharging time of grid parasitic capacitance is shortened, the delay of mirror image output is reduced, and the application scene with higher requirement on mirror image delay can be met.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a circuit diagram of a prior art current mirror circuit;
fig. 2 is a circuit diagram of a first fast current mirror circuit according to an embodiment of the present disclosure;
fig. 3 is a circuit diagram of a second fast current mirror circuit according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 2, an embodiment of the present application provides a fast current mirror circuit, which includes: a current mirror unit and a source follower.
The current mirror unit comprises two cascode current mirrors, one end of the two current mirrors is connected with a power supply VCC after being connected in series, the other end of the two current mirrors is grounded VSS, and two connection points of the two current mirrors are respectively connected with an input current IINOutput current IOUT；
The source follower is connected with the grid connection points of the two current mirrors, and is connected with the two current mirrors to input current IINIs connected to the source follower, the source follower is used for being dependent on the input current IINThe voltage of the grid connection point of the two current mirrors is dynamically adjusted by the change of the voltage, so that the charging and discharging time of the grid parasitic capacitance is shortened, and the delay of the mirror image output is reduced.
The working principle of the fast current mirror circuit in the embodiment of the application is as follows:
when inputting current IINWhen the voltage is 0, the source follower provides normally-on current for the grid connection point of the current mirror, at the moment, the voltage of the NG point is not 0, and the parasitic capacitance of the NG point can be saved from rising to the threshold value V from 0 no matter whether the parasitic capacitance is charged or dischargedTHOr threshold value VTHThe time of dropping to 0 greatly improves the stabilizing speed of the circuit, shortens the charging and discharging time of the grid parasitic capacitance and reduces the delay of mirror image output;
when inputting current IINRises from 0 to ImaxIn the meantime, the source follower raises the potential of the PG point, so that the current of the fourth transistor Q4 is lowered, and the potential change of the NG point is adjusted, so that the potential change of the NG point is smaller, the charging and discharging time of the parasitic capacitor of the NG point is reduced, and the delay of the mirror image output is reduced.
The source follower is connected with the grid connection points of the two current mirrors, and is connected with the two current mirrors to input current IINSo that the source follower can be operated in dependence on the input current IINThe voltage of the grid connection point of the two current mirrors is dynamically adjusted by the change of the voltage, so that the charging and discharging time of the grid parasitic capacitance is shortened, the delay of the mirror image output is reduced, and the application with higher requirement on the mirror image delay can be metAnd (4) scene.
Further, in the embodiment of the present application, the source follower includes a fifth transistor Q5 and a constant current source ISSThe fifth transistor Q5 and a constant current source ISSOne end of the series circuit is connected with a power supply VCC, the other end of the series circuit is grounded, and the fifth transistor Q5 and the constant current source I are connectedSSThe gate of the fifth transistor Q5 is connected to the gate connection of the two current mirrors, respectively, and the gate of the fifth transistor Q5 is connected to the two current mirrors for inputting the current IINAre connected to each other.
In the embodiment of the application, the source follower comprises a combination form of a transistor and a constant current source, is simple in structure, can realize the voltage of the grid connection point of the two current mirrors in dynamic adjustment according to the connection relation of different components, and is high in practicability.
Specifically, in the embodiment of the present application, the two current mirrors respectively include a first transistor Q1 and a second transistor Q2 that are mirror images of each other, and a third transistor Q3 and a fourth transistor Q4 that are mirror images of each other, the first transistor Q1 and the third transistor Q3 are connected in series, one end of which is connected to the power source VCC, the other end of which is grounded, the second transistor Q2 and the fourth transistor Q4 are connected in series, one end of which is connected to the power source VCC, the other end of which is grounded, and the connection point of the first transistor Q1 and the third transistor Q3 is connected to the input current IINThe connection point of the second transistor Q2 and the fourth transistor Q4 is connected with the output current IOUTAre connected.
Referring to fig. 2, in the embodiment of the present application, the fifth transistor Q5 is a PMOS transistor, the gate connection point NG of the first transistor Q1 and the second transistor Q2 is connected to the gate of the fifth transistor Q5, and the gate connection point PG of the third transistor Q3 and the fourth transistor Q4 is connected to the fifth transistor Q5 and the constant current source ISSIs connected to the gate of the fifth transistor Q5 is connected to two current mirrors for connecting the input current IINAre connected to each other.
Referring to fig. 3, in the embodiment of the present application, the fifth transistor Q5 is an NMOS transistor, and the gates of the first transistor Q1 and the second transistor Q2 are connected to each otherPoint NG, the fifth transistor Q5 and a constant current source ISSAnd the gate connection point PG of the third and fourth transistors Q3 and Q4 is connected to the gate of the fifth transistor Q5.
In the embodiment of the present application, the fifth transistor Q5 may be a PMOS transistor or an NMOS transistor, and both the functions can be realized, and only different connection modes need to be adopted according to different types of selections of the fifth transistor Q5, which are all within the protection scope of the present application.
Furthermore, in the embodiment of the present application, the first transistor Q1 and the second transistor Q2 are both NMOS transistors, and the third transistor Q3 and the fourth transistor Q4 are both PMOS transistors, so that the current mirror circuit has a simpler structure and better reliability.
Furthermore, in the embodiment of the present application, each current mirror includes two cascode transistors, where two transistors of one current mirror are both PMOS transistors, and two transistors of the other current mirror are both NMOS transistors.
Further, in the embodiment of the present application, the device parameters of the two transistors of each current mirror are the same, that is, the device parameters of the first transistor Q1 and the second transistor Q2 are the same, and the device parameters of the third transistor Q3 and the fourth transistor Q4 are also the same. At this time, the current I is inputINAnd an output current IOUTThe same is true.
Further, in the embodiment of the present application, the size ratio of the two current mirrors is the same. When the size ratio of the first transistor Q1 to the second transistor Q2 is 1: N, the size ratio of the third transistor Q3 to the fourth transistor Q4 is also 1: N, so that the output current I can be outputOUTAnd an input current IINThe ratio of (1) is N, and current mirror image output is realized.
In the embodiment of the present application, the size of the fifth transistor Q5 has no special requirement, and the constant current source ISSAnd forming the source follower.
Referring to fig. 2, in the fast current mirror circuit according to the embodiment of the present application, when the input current I is inputINWhen 0, the circuit is in self-bias stateAfter stabilization, the currents of the first transistor Q1 and the third transistor Q3 are set as I0The currents of the second transistor Q2 and the fourth transistor Q4 are N × I0Output current IOUT0, in accordance with the principle of a mirror circuit, and at this time, the potential of the gate connection point NG of the first transistor Q1 and the second transistor Q2 is set to VG0The threshold values of the first transistor Q1 and the second transistor Q2 are set to VTHThen current I0The calculation formula of (2) is as follows:
Figure BDA0002905555520000071
in the formula, kn' is constant, W is the width of the first transistor Q1, L is the length of the first transistor Q1;
is provided with
Figure BDA0002905555520000072
Then
Figure BDA0002905555520000073
It can be seen that when the current I is inputINVoltage value V of NG point is 0G0Greater than a threshold value VTHAnd V isG0Not 0, this voltage value VG0Generally between 500mV and 700mV, namely the parasitic capacitance at the NG point can be omitted from rising from 0 to V no matter whether the parasitic capacitance is charged or dischargedTHOr VTHThe time for dropping to 0 greatly improves the stabilizing speed of the circuit.
When inputting current IINRises from 0 to ImaxAt this time, the potential at the NG point rises due to charging, the fifth transistor Q5 and the constant current source ISSThe source follower can raise the PG point potential and further lower the current of the fourth transistor Q4, and after the circuit is stabilized, the current reduction is set to be delta I, and the potential of the NG point is VG1Similarly, V can be calculatedG1：
Figure BDA0002905555520000074
When inputting current IINIncrease from 0 to ImaxIn the process of (3), the NG point voltage changes to:
Figure BDA0002905555520000075
similarly, according to the current mirror circuit of the related art shown in fig. 1, the voltage change of the NG point calculated in the related art can be calculated:
Figure BDA0002905555520000076
Δ V obtained as described aboveGAnd Δ VGThe difference between the rising amplitudes of the NG point potentials in the current mirror circuit of the present application and the current mirror circuit of the prior art can be obtained by the following calculation formula:
Figure BDA0002905555520000077
due to the fact that
Figure BDA0002905555520000078
It can be seen that,
Figure BDA0002905555520000079
namely, it is
Figure BDA00029055555200000710
It can be seen that the amount of decrease Δ I of the current of the fourth transistor Q4 due to the source follower is a key factor affecting the difference between the rising amplitudes, and the source follower can adjust the potential variation at the NG point, make the potential variation at the NG point smaller, further reduce the charging and discharging time of the parasitic capacitor at the NG point, and reduce the delay of the mirror output.
In an embodiment of the present application, in one aspect, the source follower may provide a normally-on current for the current mirror unit, so that the NG point is powered onThe pressure is always above the threshold VTH(ii) a On the other hand, since the feedback currents are supplied to the third transistor Q3 and the fourth transistor Q4, the current of the fourth transistor Q4 is reduced, thereby realizing the effect of varying the input current IINThe voltage of the grid connection point of the two current mirrors is dynamically adjusted by the change of the voltage, so that the charging and discharging time of the grid parasitic capacitance is shortened, and the delay of the mirror image output is reduced.
Similarly, when inputting current IINFrom ImaxWhen the voltage becomes 0, the NG point is avoided and the voltage is lower than the threshold value VTHThe discharge current does not suddenly decrease in the period of time, so that the stabilization time is shortened more obviously, the delay of mirror image output is reduced, and the application scene with higher requirement on mirror image delay can be completely met.
In the description of the present application, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
It is noted that, in the present application, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A fast current mirror circuit, comprising:
the current mirror unit comprises two cascode current mirrors, one end of the two current mirrors is connected with a power supply VCC after being connected in series, the other end of the two current mirrors is grounded, and two connection points of the two current mirrors are respectively connected with an input current IINOutput current IOUT；
A source follower connected to the gate connection points of the two current mirrors and connected to the input current IINIs used for being dependent on the input current IINThe voltage of the grid connection point of the two current mirrors is dynamically adjusted by the change of the voltage, so that the charging and discharging time of the grid parasitic capacitance is shortened, and the delay of the mirror image output is reduced.
2. The fast current mirror circuit of claim 1, wherein:
the source follower comprises a fifth transistor Q5 and a constant current source ISSThe fifth transistor Q5 and a constant current source ISSAfter series connection, one end is connected with a power supply VCC, the other end is grounded, and the fifth end is connected with a groundThe junction of the transistor Q5 and the constant current source ISS is connected to the gate junction of one current mirror, the gate of the fifth transistor Q5 is connected to the gate junction of the other current mirror, and the gate of the fifth transistor Q5 is connected to the two current mirrors for the input current IINAre connected to each other.
3. The fast current mirror circuit of claim 1, wherein:
the two current mirrors respectively comprise a first transistor Q1 and a second transistor Q2 which are mirror images of each other, and a third transistor Q3 and a fourth transistor Q4 which are mirror images of each other, wherein one end of the first transistor Q1 and one end of the third transistor Q3 are connected in series and are connected with a power supply VCC, the other end of the first transistor Q1 and one end of the third transistor Q3 are connected with the ground, the second transistor Q2 and the fourth transistor Q4 are connected in series and are connected with the power supply VCC, the other end of the second transistor Q2 and the fourth transistor Q4 are connected with the ground, and the connection point of the first transistor Q1 and the third transistor Q3 is connected with an input current IINThe connection point of the second transistor Q2 and the fourth transistor Q4 is connected with the output current IOUTAre connected.
4. The fast current mirror circuit of claim 3, wherein:
the source follower comprises a fifth transistor Q5 and a constant current source ISSThe fifth transistor Q5 and a constant current source ISSAfter the series connection, one end of the fifth transistor Q5 is connected with a power supply VCC, the other end of the fifth transistor Q5 is connected with the ground, the connection point of the fifth transistor Q5 and the constant current source ISS is connected with the gate connection point of one current mirror, the gate of the fifth transistor Q5 is connected with the gate connection point of the other current mirror, and the connection point of the first transistor Q1 and the third transistor Q3 is connected with the gate of the fifth transistor Q5.
5. The fast current mirror circuit of claim 4, wherein:
the fifth transistor Q5 is a PMOS transistor, the gate connection point NG of the first transistor Q1 and the second transistor Q2 is connected to the gate of the fifth transistor Q5, and the gate connection point PG of the third transistor Q3 and the fourth transistor Q4 is connected to the fifth transistor Q5 and the constant current source ISSAre connected to each other.
6. The fast current mirror circuit of claim 4, wherein:
the fifth transistor Q5 is an NMOS transistor, and the gate connection point NG of the first transistor Q1 and the second transistor Q2, the fifth transistor Q5 and the constant current source ISSAnd the gate connection point PG of the third and fourth transistors Q3 and Q4 is connected to the gate of the fifth transistor Q5.
7. The fast current mirror circuit of claim 3, wherein: the first transistor Q1 and the second transistor Q2 are both NMOS transistors, and the third transistor Q3 and the fourth transistor Q4 are both PMOS transistors.
8. The fast current mirror circuit of claim 1, wherein: each current mirror comprises two cascode transistors, wherein two transistors of one current mirror are both PMOS tubes, and two transistors of the other current mirror are both NMOS tubes.
9. The fast current mirror circuit of claim 8, wherein: the component parameters of the two transistors of each current mirror are the same.
10. The fast current mirror circuit of claim 1, wherein: the two current mirrors are in the same size ratio.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4748884B2 (en) * 2000-06-27 2011-08-17 株式会社半導体エネルギー研究所 Level shifter
US6949972B1 (en) * 2004-04-02 2005-09-27 National Semiconductor Corporation Apparatus and method for current sink circuit
US7332965B2 (en) * 2006-04-19 2008-02-19 Texas Instruments Incorporated Gate leakage insensitive current mirror circuit
CN101064497B (en) * 2006-04-24 2010-12-01 中国科学院电子学研究所 Complementary metal oxide semiconductor cascade high-gain current-to-voltage converter
CN101083453A (en) * 2006-05-31 2007-12-05 中国科学院微电子研究所 Self-starting low-voltage operation current mirror circuit
CN102331809A (en) * 2011-07-14 2012-01-25 复旦大学 Current mirror circuit with grid leakage compensating function
CN103780212B (en) * 2012-10-25 2016-12-21 华为技术有限公司 A kind of operational amplifier, level shifting circuit and programmable gain amplifier
US9898028B2 (en) * 2014-11-20 2018-02-20 Qualcomm Incorporated Low voltage, highly accurate current mirror

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