CN112838892A - Testing device and method for Ethernet MAC data communication optical module - Google Patents
Testing device and method for Ethernet MAC data communication optical module Download PDFInfo
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Abstract
Disclosed are a test device and a method for an Ethernet MAC data communication optical module. The device comprises: a PHY chip; the optical module is used for receiving the data frame from the PHY chip and transmitting the received data frame back to the PHY chip through an optical fiber connected with the optical module; an ethernet MAC controller comprising: the data sending module is used for sending a data frame to the PHY chip; the data receiving module is used for receiving the data frame from the PHY chip; a transmission frame counter for counting the number of data frames transmitted to the PHY chip; a received frame counter for counting the number of data frames received from the PHY chip; and the continuity judging module is used for determining the state of the finite state machine and judging whether the data frames transmitted and/or received by the optical module are continuous or not based on the state of the finite state machine, wherein the state of the finite state machine is determined based on the data frames received by the data receiving module from the PHY chip.
Description
Technical Field
The present invention relates to a testing apparatus and method for a communication optical module, and more particularly, to a testing apparatus and method for an ethernet MAC data communication optical module.
Background
Communication protocols in the field of communications are time-varying, and due to the programmable nature of hardware such as FPGAs, DSPs, etc., communication protocol converters based on, for example, FPGAs are widely used in the field of communications, especially ethernet communications. Taking FPGA as an example, the prior art mainly focuses on FPGA implementation of an ethernet MAC layer protocol, and the ethernet MAC controller mainly includes a data sending module, a data receiving module, and a flow control module, where the data sending module and the data receiving module mainly complete receiving and sending of data frames (such as framing and identification and error check of the data frames).
In the prior art, the identification of the received data frame is mainly based on the receiving enabling signal and the preamble, but does not relate to the judgment of the continuity of the received data frame. In the prior art, Cyclic Redundancy Check (CRC) checking for MAC frames can only guarantee no bit errors, and cannot determine whether a frame is lost, so that a frame loss condition possibly caused by a transmission medium (e.g., an optical module) cannot be fed back in time, and thus, the transmission quality of data cannot be guaranteed.
Disclosure of Invention
Aspects of the present disclosure are to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Therefore, an object of the present invention is to provide a testing apparatus and method for an ethernet MAC data communication optical module, which can test whether the ethernet MAC data communication optical module causes a loss of a data frame, so as to improve data transmission quality.
One aspect of the present invention provides a testing apparatus for an ethernet MAC data communication optical module, the apparatus comprising: a PHY chip; the optical module is used for receiving the data frame from the PHY chip and transmitting the received data frame back to the PHY chip through an optical fiber connected with the optical module; an ethernet MAC controller comprising: the data sending module is used for sending a data frame to the PHY chip; the data receiving module is used for receiving the data frame from the PHY chip; a transmission frame counter for counting the number of data frames transmitted to the PHY chip; a received frame counter for counting the number of data frames received from the PHY chip; a continuity judging module for determining the state of the finite state machine in a data frame period and judging whether the data frames sent and/or received by the optical module are continuous or not based on the state of the finite state machine,
wherein the state of the finite state machine is determined based on the data frame received by the data receiving module from the PHY chip.
Optionally, the finite state machine transitions between a first state, a second state and a third state within one data frame period; wherein,
the first state and the second state represent that the data frame transmission and/or reception of the optical module is discontinuous;
the third state represents that the optical module transmits and/or receives data frames continuously.
Optionally, the continuity judging module may be configured to: the state of the finite state machine is determined based on a time interval between arrival times of enable signals of two consecutive data frames received by the data receiving module from the PHY chip and/or a count of a transmission frame counter and a count of a reception frame counter.
Optionally, the continuity judging module may be configured to: in the process of transmitting a data frame to the optical module by the data transmission module through the PHY chip, determining whether a time interval between arrival times of enabling signals of two continuous data frames received by the data receiving module is greater than a preset time interval, when the time interval between the arrival times of the enabling signals of two continuous data frames received by the data receiving module is greater than the preset time interval, determining the state of the finite state machine as a first state, and when the state of the finite state machine is the first state, determining that the data frame transmission and/or reception of the optical module is discontinuous.
Optionally, the continuity judging module may be configured to: when the time interval between the arrival times of the enabling signals of every two continuous data frames received by the data receiving module is smaller than the preset time interval and the count of the sending frame counter reaches the preset number, whether the count of the receiving frame counter is the same as the preset number or not is determined, when the count of the receiving frame counter is determined to be different from the preset number, the state of the finite state machine is determined to be a second state, when the state of the finite state machine is the second state, the data frames sent and/or received by the optical module are determined to be discontinuous, and/or when the count of the receiving frame counter is determined to be the same as the preset number, the state of the finite state machine is determined to be a third state, and when the state of the finite state machine is the third state, the data frames sent and/or received by the optical module are determined to be continuous.
Another aspect of the present disclosure is to provide a method for testing an ethernet MAC data communication optical module, which transmits a data frame to the optical module via a PHY chip by a data transmission module of an ethernet MAC controller; receiving, by a data receiving module of the ethernet MAC controller via a PHY chip, a data frame transmitted back via the optical module and an optical fiber connected to the optical module and transmitted by the data transmitting module; and determining the state of a finite state machine in a data frame period, and judging whether data frames transmitted and/or received by the optical module are continuous or not according to the state of the finite state machine, wherein the state of the finite state machine is determined based on the data frames received by the data receiving module from the PHY chip.
Optionally, the finite state machine transitions between a first state, a second state and a third state within one data frame period; wherein,
the first state and the second state represent that the data frame transmission and/or reception of the optical module is discontinuous;
the third state represents that the optical module transmits and/or receives data frames continuously.
Optionally, the step of determining the state of the finite state machine may comprise: and determining the state of the finite state machine based on the time interval between the arrival times of the enabling signals of the data receiving module for receiving two continuous data frames from the PHY chip and/or the number of the data frames transmitted by the data transmitting module and the number of the data frames received by the data receiving module.
Optionally, the step of determining whether the data frames transmitted and/or received by the optical module are continuous according to the state of the finite state machine may include: in the process of transmitting a data frame to the optical module by the data transmission module through the PHY chip, determining whether a time interval between arrival times of enabling signals of two continuous data frames received by the data receiving module is greater than a preset time interval, when the time interval is greater than the preset time interval, determining the state of the finite state machine as a first state, and when the state of the finite state machine is the first state, determining that the optical module does not transmit and/or receive the data frame continuously.
Optionally, the step of determining whether the data frames transmitted and/or received by the optical module are continuous based on the state of the finite state machine may include: when the time interval between the arrival times of the enabling signals of every two continuous data frames received by the data receiving module is smaller than the preset time interval and the number of the data frames transmitted by the data transmitting module is determined to reach the preset number, whether the number of the data frames received by the data receiving module is the same as the preset number or not is determined, when the number of the data frames received by the data receiving module is determined to be not the same as the preset number, the state of the finite state machine is determined to be a second state, when the state of the finite state machine is determined to be the second state, the data frames transmitted and/or received by the optical module are determined to be discontinuous, and/or when the number of the data frames received by the data receiving module is determined to be the same as the preset number, the state of the finite state machine is determined to be a third state, and when the state of the finite state machine is the third state, determining that the optical module transmits and/or receives data frames continuously.
Optionally, the number of data frames sent by the data sending module and the number of data frames received by the data receiving module are counted by a sending frame number counter and a receiving frame number counter, respectively.
The embodiment of the disclosure provides a continuity testing device and method based on a finite-state machine, which can test whether a data frame loss occurs in an Ethernet MAC data communication optical module in a data frame period, so that the data transmission quality can be improved. In a data frame period, the finite state machine is switched among the first state, the second state and the third state, so that all steps of the continuity test can be ensured to be completed in the data frame period.
Drawings
The above and other aspects, features and advantages of particular embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram of an example of a prior art Ethernet communication system;
fig. 2 is a block diagram of a testing apparatus of an ethernet MAC data communication optical module according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of a test apparatus for an Ethernet MAC controller in an Ethernet MAC data communication system according to an embodiment of the disclosure;
fig. 4 is a block diagram of a test apparatus of a PHY chip in an ethernet MAC data communication system according to an embodiment of the present disclosure;
fig. 5 is a flowchart of a method for testing an ethernet MAC data communication optical module according to an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.
Fig. 1 is a block diagram of an example of an ethernet communication system in the prior art.
Referring to fig. 1, an ethernet communication system 100 includes an ethernet MAC controller 110, a PHY (Physical layer) chip 120, and an optical module 130. Optionally, Ethernet MAC communication system 100 may additionally include other components. The ethernet MAC controller 110 includes a data transmission module 111, a flow control module 112, and a data reception module 113. Optionally, the ethernet MAC controller 110 may additionally include other components. The data transmission module 111 may transmit data to the optical module 130 via the PHY chip 120, and the optical module 130 transmits the received data to an external device (not shown). When receiving data from an external device (not shown), the optical module 130 may transmit the data received from the external device to the data reception module 113 via the PHY chip 120. The flow control module 112 may control data transmission and reception of the data transmission module 111 and the data reception module 113.
As an example, the ethernet MAC controller 110 may be implemented by a PFGA, or may be implemented by hardware other than an FPGA.
In the prior art, the identification of the received data frame is mainly based on the receiving enabling signal and the preamble, but does not relate to the judgment of the continuity of the received data frame. In the prior art, Cyclic Redundancy Check (CRC) checking for MAC frames can only guarantee no bit errors, and cannot determine whether a frame is lost, so that a frame loss condition possibly caused by a transmission medium (e.g., an optical module) cannot be fed back in time, and thus, the transmission quality of data cannot be guaranteed.
Fig. 2 is a block diagram of a testing apparatus 200 of an ethernet MAC data communication optical module according to an embodiment of the present disclosure.
Referring to fig. 2, the testing apparatus 200 includes an ethernet MAC controller 210, a PHY chip 220, an optical module 230, an optical fiber 240, and an output apparatus 250, wherein the ethernet MAC controller 210 may include a flow control module 211, a transmission frame counter 212, a continuity determining module 213, a reception frame counter 214, a data transmission module 215, and a data reception module 216, wherein the transmission frame counter 212 is configured to count the number of data frames transmitted to the PHY chip 220, and the reception frame counter 214 is configured to count the number of data frames received from the PHY chip 220. Alternatively, the test device 200 may omit any of the above components or additionally add other components.
Referring to fig. 2, a data frame transmitted by the data transmission module 215 is transmitted to the data reception module 216 via the PHY chip 220, the optical module 230, the optical fiber 240, the optical module 230, and the PHY chip 220 in this order.
It should be noted that, in order to test whether the optical module is normal, it is necessary to ensure that other components for transceiving data besides the optical module are functioning normally, and the following description describes the testing of other components for transceiving data besides the optical module.
Firstly, testing a data receiving and sending program of the Ethernet, and setting a debug program on an FPGA chip with normal test for the data sending program of the Ethernet for testing; for an Ethernet data receiving program, on an FPGA chip which is tested normally, the test is carried out through self-loop inside the FPGA. That is, it is first ensured that the ethernet data transceiving procedure is normal.
Alternatively, the data transceiver of the ethernet may be tested on other hardware than the FPGA.
After determining that the data transceiving procedure of the ethernet is normal, a test may be performed with respect to the ethernet MAC controller 210.
Fig. 3 is a block diagram of a test apparatus of an ethernet MAC controller in an ethernet MAC data communication system according to an embodiment of the present disclosure.
The components in fig. 3 are the same as those in fig. 2, and are not described herein again.
Referring to fig. 3, the data sending module 215 directly sends data to the data receiving module 216, and determines whether the ethernet MAC controller 210 has a fault by comparing the data sent by the data sending module 215 with the data received by the data receiving module 216, and if the data sent by the data sending module 215 is consistent with the data received by the data receiving module 216, it indicates that the ethernet MAC controller 210 is normal; if the data sent by the data sending module 215 is not consistent with the data received by the data receiving module 216, it indicates that the ethernet MAC controller 210 has a failure.
Alternatively, the data transmitted by the data transmitting module 215 and the data received by the data receiving module 216 may be compared by the continuity judging module 213 to determine whether there is a failure in the ethernet MAC controller.
Alternatively, the data transmitted by the data transmission module 215 and the data received by the data reception module 216 may be compared by other components additionally included to determine whether there is a failure of the ethernet MAC controller.
Alternatively, an identifier indicating the determination result may be output by the output device.
If the ethernet MAC controller 210 is normal, the PHY chip continues to be tested; if there is a problem with the ethernet MAC controller 210, the ethernet MAC controller 210 is replaced and the test is performed again to prepare for testing the PHY chip 220.
Upon determining that ethernet MAC controller 210 is not faulty, PHY chip 220 is tested.
Fig. 4 is a block diagram of a test apparatus of a PHY chip in an ethernet MAC data communication system according to an embodiment of the present disclosure.
For PHY chip 220, PHY chip 220 may be tested by configuring PHY chip registers.
Specifically, the bmcr (basic Mode Control register) register of the PHY chip may be configured, and the contents of the register may be configured according to the actual situation of the test item.
Similar to the test ethernet MAC controller 210, the transmitted data is compared with the data that is returned by the PHY chip 220, and if the two are consistent, it indicates that the PHY chip 220 is normal; if they are not the same, the PHY chip 220 is indicated to have a problem.
Alternatively, the determination result may be displayed through the output device 250 or output through other components additionally included.
When it is determined that the PHY chip 220 has no failure, the optical module 230 may be directly tested; if there is a problem with the PHY chip 220, the PHY chip 220 is retested after the PHY chip 220 is replaced, and preparation is made for testing the optical module 230.
In the case where it is determined that components other than the optical module 230 are normal, a test is finally performed on the optical module 230.
The test apparatus for the ethernet MAC data communication optical module 230 has been described above with reference to fig. 2, and is not described herein again.
As an example, when testing the optical module 230, a finite state machine may be designed for the optical module 230 testing. The continuity judging module 213 may determine and/or update the state of the finite state machine based on the data frame received by the data receiving module 216 from the PHY chip 220, and then may judge whether the data frame transmitted and/or received by the optical module 230 is continuous based on the determined and/or updated state of the finite state machine.
As an example, continuity determining module 213 may determine the state of the finite state machine based on the time interval between the arrival times of the enable signals of two consecutive data frames received by data receiving module 216 from PHY chip 220 and/or the count of transmit frame counter 212 and the count of receive frame counter 214.
As an example, the finite state machine transitions between a first state, a second state, and a third state within one data frame period; wherein,
the first state and the second state represent that the data frame transmission and/or reception of the optical module is discontinuous;
the third state represents that the optical module transmits and/or receives data frames continuously.
In this example, a data frame period refers to a time taken for the data transmitting module to transmit a data frame, and then the data receiving module receives the data frame via the PHY chip and the optical module.
As an example, the continuity determination module 213 may be configured to: in the process of transmitting the data frame to the optical module 230 through the PHY chip 220 by the data transmission module 215, it is determined whether a time interval between arrival times of enable signals of two consecutive data frames received by the data reception module 216 is greater than a predetermined time interval, when the time interval between the arrival times of enable signals of two consecutive data frames received by the data reception module 216 is greater than the predetermined time interval, the state of the finite state machine is determined as a first state, and when the state of the finite state machine is the first state, it is determined that the optical module 230 does not transmit and/or receive the data frame.
Alternatively, when the state of the finite state machine is the first state, the determination of whether the transmission and/or reception of the data frame by the optical module 230 is continuous may be stopped, and/or the transmission of the data frame by the data transmission module 215 to the optical module 230 via the PHY chip 220 may be stopped.
As an example, the output device 250 may be used to: and when the state of the finite state machine is the first state, outputting a first identifier.
As an example, the continuity determination module 213 may be configured to: when it is determined that the time interval between the arrival times of the enable signals of every two consecutive data frames received by the data receiving module 216 is less than the predetermined time interval, and determines that the count of the transmission frame counter 212 reaches the predetermined number, determines whether the count of the reception frame counter 214 is the same as the predetermined number, when it is determined that the count of the reception frame counter 214 is not identical to the count of the transmission frame counter 214, the state of the finite state machine is determined as a second state, when the state of the finite state machine is the second state, it is determined that the transmission and/or reception of the data frame by the optical module 230 is not continuous, and/or, when it is determined that the count of the reception frame counter 214 is the same as the count of the transmission frame counter 212, the state of the finite state machine is determined as a third state, when the state of the finite state machine is the third state, it is determined that the optical module 230 transmits and/or receives data frames continuously.
As an example, the output device 250 may be used to: and when the state of the finite state machine is a second state, outputting a second identifier, and/or when the state of the finite state machine is a third state, outputting a third identifier.
As an example, N data frames may be transmitted by the data transmission module 215, and if the time interval between the arrival times of the enable signals when the data reception module 216 receives two consecutive data frames is greater than the predetermined time interval, it is determined that the optical module 230 transmits and/or receives the data frames discontinuously. At this time, the determination of the continuity of the data frame transmitted and/or received by the optical module 230 may be stopped, and/or the data frame transmitted by the data transmission module 215 to the optical module 230 via the PHY chip 220 may be stopped. Alternatively, an indication to display the situation may be output by the output device 250.
After the count of the transmission frame counter 212 reaches N, it is determined whether the time intervals between the arrival times of the enable signals of every two consecutive data frames received by the data receiving module 216 are both less than the predetermined time interval, if both are less than the predetermined time interval, it is determined whether the count 214 of the reception frame counter is equal to N, if equal to N, it is determined that the data frames transmitted and/or received by the optical module 230 are consecutive, optionally, an indication indicating this may be output by the output means 250, if the count of the reception frame counter 214 is not equal to N, it is determined that the data frames transmitted and/or received by the optical module 230 are not consecutive, optionally, an indication indicating this may be output by the output means 250.
In addition, for the correctness check of the received data frame, a data check state machine can be arranged on the basis of CRC check, so that the accuracy of data check is improved. As an example, received ethernet data with a bit width of 4 bits may be converted into data with a bit width of 8 bits, and the data is sent to a data verification state machine, where the data verification state machine mainly verifies data at a specific position, and if the data is consistent with preset data, it indicates that the received data is correct, and waits for the arrival of the next frame of data; if the data are inconsistent, the received data are incorrect, the judgment result can be identified by adopting an external device, the state machine enters a dead cycle, and the data are stopped being checked.
The test device for the ethernet MAC data communication optical module according to the exemplary embodiment of the present invention has been described above with reference to fig. 1 to 4. Hereinafter, a method for testing an ethernet MAC data communication optical module according to an exemplary embodiment of the present invention will be described with reference to fig. 5.
Fig. 5 is a flowchart of a method for testing an ethernet MAC data communication optical module according to an embodiment of the present disclosure.
Referring to fig. 5, a data frame is transmitted to an optical module by a data transmission module of an ethernet MAC controller via a PHY chip at step S101.
In step S102, a data frame transmitted by the data transmission module and transmitted back through the optical module and the optical fiber connected to the optical module is received by the data receiving module of the ethernet MAC controller via the PHY chip.
In step S103, a state of the finite state machine is determined, and whether data frames transmitted and/or received by the optical module are continuous is determined according to the state of the finite state machine, where the state of the finite state machine is determined based on the data frames received by the data receiving module from the PHY chip.
As an example, the step of determining the state of the finite state machine may comprise: and determining the state of the finite state machine based on the time interval between the arrival times of the enabling signals of the data receiving module for receiving two continuous data frames from the PHY chip and/or the number of the data frames transmitted by the data transmitting module and the number of the data frames received by the data receiving module.
As an example, the step of determining whether the data frames transmitted and/or received by the optical module are continuous according to the state of the finite state machine may include: determining whether a time interval between arrival times of enable signals of two consecutive data frames received by the data receiving module is greater than a predetermined time interval in transmitting a data frame to the optical module via the PHY chip by the data transmitting module; when the interval is larger than the preset interval, determining the state of the finite-state machine as a first state; and when the state of the finite state machine is a first state, determining that the data frame sent and/or received by the optical module is discontinuous.
Alternatively, when the state of the finite state machine is the first state, the determination of whether the data frames are transmitted and/or received continuously by the optical module may be stopped, and/or the data frames may be stopped from being transmitted to the optical module by the data transmission module of the ethernet MAC controller via the PHY chip.
As an example, the step of determining whether the data frames transmitted and/or received by the optical module are continuous may further include: and when the state of the finite state machine is the first state, outputting a first identifier.
As an example, the step of determining whether the data frames transmitted and/or received by the optical module are continuous based on the state of the finite state machine may include: when the time interval between the arrival times of the enabling signals of every two continuous data frames received by the data receiving module is smaller than the preset time interval and the number of the data frames transmitted by the data transmitting module is determined to reach the preset number, whether the number of the data frames received by the data receiving module is the same as the preset number or not is determined, when the number of the data frames received by the data receiving module is determined to be not the same as the preset number, the state of the finite state machine is determined to be a second state, when the state of the finite state machine is determined to be the second state, the data frames transmitted and/or received by the optical module are determined to be discontinuous, and/or when the number of the data frames received by the data receiving module is determined to be the same as the preset number, the state of the finite state machine is determined to be a third state, and when the state of the finite state machine is the third state, determining that the optical module transmits and/or receives data frames continuously.
As an example, the second identification may be output when the state of the finite state machine is a second state.
As an example, the third identification may be output when the state of the finite state machine is a third state.
As an example, the first logo, the second logo, and the third logo may be respectively represented by the LED lamps blinking in different colors.
As an example, the number of data frames transmitted by the data transmission module and the number of data frames received by the data reception module are counted by a transmission frame number counter and a reception frame number counter, respectively.
As described above, according to the exemplary embodiments of the present invention, it may be determined whether data frames transmitted and/or received by the optical module are consecutive, so that data transmission quality can be improved.
Exemplary embodiments of the present invention provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the test method of the ethernet MAC data communication optical module as described in the above exemplary embodiments. The computer readable storage medium is any data storage device that can store data which can be read by a computer system. Examples of computer-readable storage media include: read-only memory, random access memory, read-only optical disks, magnetic tapes, floppy disks, optical data storage devices, and carrier waves (such as data transmission through the internet via wired or wireless transmission paths).
The test device of the Ethernet MAC data communication optical module according to the exemplary embodiment of the invention can comprise: a processor and a memory, wherein the memory stores a computer program which, when executed by the processor, implements the method for testing the ethernet MAC data communication optical module according to the above exemplary embodiments.
Although a few exemplary embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.
Claims (11)
1. A testing apparatus for an ethernet MAC data communication optical module, the apparatus comprising:
a PHY chip;
the optical module is used for receiving the data frame from the PHY chip and transmitting the received data frame back to the PHY chip through an optical fiber connected with the optical module;
an ethernet MAC controller comprising:
the data sending module is used for sending a data frame to the PHY chip;
the data receiving module is used for receiving the data frame from the PHY chip;
a transmission frame counter for counting the number of data frames transmitted to the PHY chip;
a received frame counter for counting the number of data frames received from the PHY chip;
a continuity judging module for determining the state of the finite state machine in a data frame period and judging whether the data frames sent and/or received by the optical module are continuous or not based on the state of the finite state machine,
wherein the state of the finite state machine is determined based on the data frame received by the data receiving module from the PHY chip.
2. The apparatus of claim 1, wherein the finite state machine transitions between a first state, a second state, and a third state within a data frame period; wherein,
the first state and the second state represent that the data frame transmission and/or reception of the optical module is discontinuous;
the third state represents that the optical module transmits and/or receives data frames continuously.
3. The apparatus of claim 1, wherein the continuity determination module is to:
based on the time interval between the arrival times of the enabling signals of the two continuous data frames received by the data receiving module from the PHY chip, and/or
The count of the transmit frame counter and the count of the receive frame counter determine the state of the finite state machine.
4. The apparatus of claim 3, wherein the continuity determination module is to:
determining whether a time interval between arrival times of enable signals of the data reception module to receive two consecutive data frames is greater than a predetermined time interval during transmission of the data frames to the optical module by the data transmission module via the PHY chip,
when the time interval between the arrival times of the enabling signals of two continuous data frames received by the data receiving module is larger than a preset interval, determining the state of the finite-state machine as a first state,
and when the state of the finite state machine is a first state, determining that the data frame sent and/or received by the optical module is discontinuous.
5. The apparatus of claim 3, wherein the continuity determination module is to:
when it is determined that the time interval between the arrival times of the enable signals for every two consecutive data frames received by the data reception module is less than the predetermined time interval and it is determined that the count of the transmission frame counter reaches the predetermined number, it is determined whether the count of the reception frame counter is the same as the predetermined number,
determining the state of the finite state machine as a second state when it is determined that the count of the received frame counter is not identical to the predetermined number,
when the state of the finite state machine is a second state, determining that the data frame transmission and/or reception of the optical module is discontinuous,
and/or when the counting number of the receiving frame counter is the same as the preset number, determining the state of the finite state machine as a third state, and when the state of the finite state machine is the third state, determining that the data frames sent and/or received by the optical module are continuous.
6. A test method for Ethernet MAC data communication optical module is characterized in that,
transmitting, by a data transmission module of the ethernet MAC controller, the data frame to the optical module via the PHY chip;
receiving, by a data receiving module of the ethernet MAC controller via a PHY chip, a data frame transmitted back via the optical module and an optical fiber connected to the optical module and transmitted by the data transmitting module; and
determining the state of the finite state machine in a data frame period, and judging whether the data frames sent and/or received by the optical module are continuous or not according to the state of the finite state machine,
wherein the state of the finite state machine is determined based on the data frame received by the data receiving module from the PHY chip.
7. The method of claim 6, wherein the finite state machine transitions between a first state, a second state, and a third state within one data frame period; wherein,
the first state and the second state represent that the data frame transmission and/or reception of the optical module is discontinuous;
the third state represents that the optical module transmits and/or receives data frames continuously.
8. The method of claim 6, wherein the step of determining the state of the finite state machine comprises:
based on the time interval between the arrival times of the enabling signals of the two continuous data frames received by the data receiving module from the PHY chip, and/or
And the number of the data frames sent by the data sending module and the number of the data frames received by the data receiving module determine the state of the finite-state machine.
9. The method as claimed in claim 8, wherein the step of determining whether the data frames transmitted and/or received by the optical module are consecutive according to the state of the finite state machine comprises:
determining whether a time interval between arrival times of enable signals of the data reception module to receive two consecutive data frames is greater than a predetermined time interval during transmission of the data frames to the optical module by the data transmission module via the PHY chip,
when the time interval is greater than the predetermined interval, determining the state of the finite state machine as a first state,
and when the state of the finite state machine is a first state, determining that the data frame sent and/or received by the optical module is discontinuous.
10. The method of claim 8, wherein the step of determining whether the optical module transmits and/or receives data frames consecutively based on the state of a finite state machine comprises:
when it is determined that the time interval between the arrival times of the enable signals of every two consecutive data frames received by the data receiving module is less than the predetermined time interval and it is determined that the number of data frames transmitted by the data transmitting module reaches the predetermined number, it is determined whether the number of data frames received by the data receiving module is the same as the predetermined number,
determining the state of the finite state machine as a second state when it is determined that the number of data frames received by the data receiving module is not the same as the predetermined number,
when the state of the finite state machine is a second state, determining that the data frame transmission and/or reception of the optical module is discontinuous,
and/or determining the state of the finite state machine as a third state when it is determined that the number of data frames received by the data receiving module is the same as the predetermined number,
and when the state of the finite state machine is a third state, determining that the data frames sent and/or received by the optical module are continuous.
11. The method of claim 8, wherein the number of data frames transmitted by the data transmission module and the number of data frames received by the data reception module are counted by a transmission frame number counter and a reception frame number counter, respectively.
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