CN112838124A - 横向扩散金属-氧化物半导体晶体管及其形成方法 - Google Patents
横向扩散金属-氧化物半导体晶体管及其形成方法 Download PDFInfo
- Publication number
- CN112838124A CN112838124A CN202011312930.2A CN202011312930A CN112838124A CN 112838124 A CN112838124 A CN 112838124A CN 202011312930 A CN202011312930 A CN 202011312930A CN 112838124 A CN112838124 A CN 112838124A
- Authority
- CN
- China
- Prior art keywords
- region
- sidewall
- trench
- semiconductor substrate
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 18
- 229910044991 metal oxide Inorganic materials 0.000 title description 7
- 150000004706 metal oxides Chemical class 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 239000004020 conductor Substances 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims description 76
- 210000000746 body region Anatomy 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000009958 sewing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本公开涉及横向扩散金属‑氧化物半导体晶体管及其形成方法。一种晶体管包括在半导体衬底中形成的沟槽,其中所述沟槽具有第一侧壁和第二侧壁。栅极区包括填充于所述沟槽中的导电材料。具有第一导电类型的漂移区邻近所述第二侧壁形成于所述半导体衬底中。漏极区形成于所述漂移区中并且与所述第二侧壁间隔开第一距离。电介质层形成于所述半导体衬底的顶表面处,覆盖所述栅极区和所述第二侧壁与所述漏极区之间的所述漂移区。场板形成于所述电介质层上方并且借助于所述电介质层与所述导电材料和所述漂移区隔离。
Description
技术领域
本公开大体上涉及半导体装置,且更具体地说,涉及横向扩散金属-氧化物半导体(LDMOS)晶体管及其形成方法。
背景技术
传统的半导体装置和半导体装置制造工艺正在不断发展。例如,金属氧化物半导体场效应晶体管(MOSFET)用于各种不同的应用和电子产品-从缝纫机到洗衣机、从汽车到蜂窝电话等等。随着工艺技术的进步,预期这些半导体装置在减小大小和成本的同时提高性能。然而,在平衡大小、成本和性能方面存在挑战。
发明内容
总的来说,提供一种晶体管,其包括:沟槽,其形成于半导体衬底中,所述沟槽具有第一侧壁和第二侧壁;栅极区,其包括填充于沟槽中的导电材料;漂移区,其邻近第二侧壁形成于半导体衬底中,所述漂移区具有第一导电类型;漏极区,其形成于漂移区中,所述漏极区与第二侧壁间隔开第一距离;电介质层,其形成于半导体衬底的顶表面处,覆盖栅极区和第二侧壁与漏极区之间的漂移区;以及场板,其形成于电介质层上方,所述场板借助于电介质层与导电材料和漂移区隔离。场板的第一边缘可与栅极区的一部分重叠,并且场板的第二边缘可在漂移区上方延伸第二距离,所述第二距离小于第一距离。场板可包括水平部分和竖直部分,水平部分通过层间电介质(ILD)与电介质层间隔开,并且竖直部分在第一边缘附近与水平部分接触且从水平部分的底表面延伸到电介质层的顶表面。所述晶体管可另外包括安置于沟槽的侧壁和底部处的栅极电介质,所述栅极电介质将导电材料与半导体衬底隔离。导电材料可由多晶硅材料形成,并且场板可由金属材料形成。所述晶体管可另外包括邻近第一侧壁形成于半导体衬底中的源极区,电介质层的一部分与源极区重叠。所述晶体管可另外包括邻近第一侧壁形成于半导体衬底中的具有第二导电类型的主体区,源极区形成于主体区中。所述晶体管可另外包括形成于漏极区和源极区的顶表面处的自对准硅化物层,并且其中电介质层由氮化物材料形成且被配置成充当自对准硅化物层的掩模。所述晶体管可另外包括与源极区接触的源极端,源极端借助于金属层连接到场板。
在另一实施例中,提供一种方法,其包括:在半导体衬底中蚀刻沟槽,所述沟槽具有第一侧壁和第二侧壁;用导电材料填充沟槽以形成栅极区;在半导体衬底中邻近第二侧壁形成漂移区,所述漂移区具有第一导电类型;在漂移区中形成漏极区,所述漏极区与第二侧壁间隔开第一距离;将在半导体衬底的顶表面处的电介质层图案化以覆盖栅极区和在第二侧壁与漏极区之间的漂移区;以及在电介质层上方形成场板,所述场板借助于电介质层与导电材料和漂移区隔离。场板的第一边缘可与栅极区的一部分重叠,并且场板的第二边缘可在漂移区上方延伸第二距离,所述第二距离小于第一距离。导电材料可由多晶硅材料形成,并且场板可由金属材料形成。形成场板可包括:形成竖直部分,所述竖直部分具有与电介质层的顶表面接触的底表面和延伸穿过层间电介质(ILD)的顶表面;以及形成水平部分,所述水平部分与竖直部分的顶表面接触,所述水平部分通过ILD与电介质层间隔开。所述方法可另外包括在用导电材料填充沟槽之前在沟槽的侧壁和底部处形成栅极电介质,所述栅极电介质将导电材料与半导体衬底隔离。所述方法可另外包括在半导体衬底中邻近第一侧壁形成源极区,电介质层的一部分与源极区重叠。所述方法可另外包括在半导体衬底中邻近第一侧壁形成具有第二导电类型的主体区,源极区形成于主体区中。所述方法可另外包括形成与栅极区接触的栅极端,以及借助于金属层将栅极端连接到场板。
在又一实施例中,提供一种晶体管,其包括:沟槽,其形成于半导体衬底中,所述沟槽具有第一侧壁和第二侧壁;栅极区,其包括填充于沟槽中的导电材料;栅极电介质,其安置于沟槽的侧壁和底部处,栅极电介质将导电材料与半导体衬底隔离;漂移区,其邻近第二侧壁形成于半导体衬底中,漂移区具有第一导电类型;漏极区,其形成于漂移区中,漏极区与第二侧壁间隔开第一距离;主体区,其邻近第一侧壁形成于半导体衬底中,主体区具有第二导电类型;电介质层,其形成于半导体衬底的顶表面处,覆盖栅极区和第二侧壁与漏极区之间的漂移区;以及场板,其形成于电介质层上方,场板借助于电介质层与导电材料和漂移区隔离。场板的第一边缘可与栅极区的一部分重叠,并且场板的第二边缘可在漂移区上方延伸第二距离,所述第二距离小于第一距离。晶体管可另外包括邻近第一侧壁形成于主体区中的具有第一导电类型的源极区,电介质层的一部分与源极区重叠。
附图说明
本发明借助于例子示出且不受附图的限制,附图中的类似标记指示类似元件。为简单和清晰起见示出图中的元件,并且元件不一定按比例绘制。
图1至图7以简化的横截面视图示出根据实施例的示例横向扩散金属-氧化物半导体(LDMOS)晶体管的各个制造阶段。
图8和图9以简化的平面视图示出根据实施例的处于制造阶段的示例LDMOS晶体管。
具体实施方式
近年来,汽车,工业和消费者应用对智能功率技术的需求不断增长,智能功率技术将数字、模拟和高压功率晶体管集成在单个芯片上,旨在降低制造成本。在半导体制造中,硅面积非常宝贵。本文所述的基于沟槽的晶体管中发生的技术改进的一个例子是:硅面积影响减小的功率晶体管的合乎需要的改进的导通电阻*面积(RonA)值。
总的来说,提供一种基于沟槽的横向扩散金属-氧化物半导体(LDMOS)晶体管。形成于半导体衬底中的沟槽填充有导电材料以形成栅极区。栅极电介质形成为沟槽中的内衬,从而将栅极区与衬底隔离。源极区邻近沟槽形成于半导体衬底的表面处。漏极区与沟槽间隔开预定距离形成于半导体衬底的表面处。电介质层形成于栅极区上方且在沟槽与漏极区之间的漂移区上方跨越预定距离。场板形成于电介质层的一部分上方。选择场板和电介质层的尺寸以实现较高击穿电压和改进的RonA。
图1至图7以简化的横截面视图示出根据实施例形成的示例横向扩散金属-氧化物半导体(LDMOS)晶体管100的各个制造阶段。
图1以简化的横截面视图示出根据实施例的处于制造阶段的示例LDMOS晶体管100。在此阶段,晶体管100包括硅基衬底102、形成于衬底102上方的图案化硬掩模116、形成于衬底102中的沟槽104,以及形成于沟槽104的侧壁和底部处的栅极电介质106。在此实施例中,衬底102形成为具有P型导电类型的P型掺杂硅衬底。衬底102可形成为具有N型外延层的P型掺杂硅衬底。举例来说,衬底102可替代地由其它合适的硅基基质形成,所述硅基基质例如砷化镓、锗化硅、绝缘体硅(SOI)、硅、单晶硅等,以及其组合等。
在此实施例中,氧化物层112形成于上衬底102上,且氮化物层114形成于氧化物层112上。将氮化物/氧化物层一起图案化以形成硬掩模116。在其它实施例中,其它适合的材料和其组合可用于形成硬掩模116。在此实施例中,沟槽104包括第一侧壁108、第二侧壁110和底表面。举例来说,可采用例如反应离子蚀刻(RIE)等蚀刻技术以形成沟槽104。在此实施例中,栅极电介质106形成于沟槽104的暴露表面上,从而在沟槽104的侧壁108-110和底表面处基本上形成内衬层。栅极电介质106可由任何合适的栅极电介质材料(例如,二氧化硅)形成。栅极电介质106可形成为生长层、沉积层或其组合。
图2以简化的横截面视图示出根据实施例的处于后续制造阶段的示例LDMOS晶体管100。在此阶段,使导电材料沉积以大体上填满沟槽104并且形成栅极区202。进行平坦化操作以使导电材料与114层持平。在此实施例中,平坦化操作可包括化学机械平坦化(CMP)工艺。在其它实施例中,平坦化操作可包括湿式蚀刻工艺。可进行后续蚀刻操作以使导电材料与衬底的顶表面大体上持平,从而形成栅极区202。举例来说,栅极区202可由例如多晶硅材料或金属材料等合适的导电材料形成。在此实施例中,栅极区202被配置并布置成充当示例LDMOS晶体管100的栅极电极。在其它实施例中,栅极区202可由其它导电材料形成。
图3以简化的横截面视图示出根据实施例的处于后续制造阶段的示例LDMOS晶体管100。在此阶段,形成衬底102的平面顶表面306,且形成主体区302和漂移区304。
在图3中所描绘的实施例中,除去衬底102的顶表面处的硬掩模116,从而形成平面顶表面306。在此实施例中,栅极区202与平面顶表面306大体上是平面的。在其它实施例中,栅极区202可从平面顶表面306稍微凹入或稍微凸出。保留在沟槽中的栅极电介质106用以将栅极区202与衬底102隔离。
在此实施例中,主体区302邻近侧壁108形成为衬底102中的P型阱掺杂剂注入区。主体区302可表征为P-(减)主体区。漂移区304邻近侧壁110形成为衬底102中的N型阱掺杂剂注入区。漂移区304可表征为N-(减)漂移区。在一些实施例中,漂移区304可由衬底102的N型外延层形成。
图4以简化的横截面视图示出根据实施例的处于后续制造阶段的示例LDMOS晶体管100。在此阶段,电介质层402形成于衬底102的顶表面处。沉积和图案化形成于衬底102的顶表面处的电介质层402,以覆盖栅极区202以及主体区302和漂移区304的部分。在此实施例中,电介质层402可由电介质材料(例如,氮化硅)形成,所述电介质材料适合于在形成后续工艺结构(例如,源极/漏极区、自对准硅化物层)时充当自对准掩模。可针对最优减小表面场(RESURF)选择电介质层402的尺寸(例如,厚度、宽度、长度)。
图5以简化的横截面视图示出根据实施例的处于后续制造阶段的示例LDMOS晶体管100。在此阶段,形成源极区502和漏极区504,且形成主体连接区506。在形成主体区302和漂移区304之后,注入N型掺杂剂以分别形成源极区502和漏极区504。源极区502和漏极区504可分别表征为N+(加)源极/漏极区。邻近侧壁108形成源极区502,且注入P型掺杂剂以形成主体连接区506,从而允许与主体区302电连接。主体连接区506可表征为P+(加)主体连接区。在此实施例中,主体连接区506邻接源极区502。与侧壁110间隔开横向距离508形成漏极区504。随着横向距离508增大,对应的击穿电压增大。在此实施例中,举例来说,侧壁110与漏极区504之间的横向距离508可在0.5微米至10.0微米的范围内。在一些实施例中,横向距离508可小于0.5微米或大于10.0微米。
图6以简化的横截面视图示出根据实施例的处于后续制造阶段的示例LDMOS晶体管100。在此阶段,在源极区502和漏极区504以及主体连接区506的顶表面处形成自对准硅化物区602。沉积金属薄膜层(例如,钛、铂、钨)并且使所述金属薄膜层与源极区502和漏极区504以及主体连接区506的暴露顶表面反应以形成自对准硅化物区602。自对准硅化物区用以在源极区502和漏极区504以及主体连接区506的顶表面处形成高导电性接触区。在此实施例中,本文所使用的术语自对准硅化物(salicide)还可以指自对准的硅化物(self-aligned silicide)。
图7以简化的横截面视图示出根据实施例的处于后续制造阶段的示例LDMOS晶体管100。在此阶段,示例LDMOS晶体管100包括接触件702-708、电极端710-714和水平场板716。在此实施例中,水平场板716和接触件708一起形成如图7中所描绘的伪L形场板。
在此实施例中,在电介质层402和自对准硅化物区602上方形成层间电介质(ILD)区720。ILD区720可由一系列沉积的氧化物层形成,所述氧化物例如原硅酸四乙酯(TEOS)。举例来说,可以沉积、图案化和蚀刻ILD区720的第一氧化物层以暴露栅极区202、自对准硅化物区602和电介质层402的部分。在图案化和蚀刻第一氧化物层之后,形成接触件702-708。举例来说,接触件702-708可由例如铜、金、银、铝、镍、钨及其合金等任何合适的导电材料形成。接触件702-706分别提供到源极区502和主体连接区506、栅极区202以及漏极区504的导电连接。形成接触件708以使得接触件708的底表面邻接电介质层402的顶表面。在此实施例中,接触件708充当具有第一边缘718的竖直场板部分,所述第一边缘718在侧壁110处与栅极区202的一部分重叠。
在形成接触件702-708之后,沉积、图案化和蚀刻导电层以形成电极端710-714和水平场板716。电极端710-714和水平场板716可由例如铜、金、银、铝、镍、钨和其合金等任何合适的导电材料形成。在此实施例中,源极电极端710借助于接触件702和自对准硅化物区602连接到源极区502和主体连接区506,栅极电极端712借助于接触件704连接到栅极区202,并且漏极电极端714借助于接触件706和自对准硅化物区602连接到漏极区504。
水平场板716直接连接到接触件708,从而形成伪L形场板。水平场板716的一部分与栅极区202与漏极区504之间的下层漂移区304重叠一定重叠距离726。可针对最优RESURF选择重叠距离726。在此实施例中,举例来说,重叠距离726可在横向距离508的40%至60%的范围内。在一些实施例中,重叠距离726可小于横向距离508的40%或大于横向距离508的60%。在此实施例中,场板借助于电介质层402与衬底电隔离。在一些实施例中,举例来说,场板可借助于金属互连层连接到源极电极端710或栅极电极端712。
在图7中所描绘的实施例中,电极端710-714和水平场板716由相同导电层形成。在其它实施例中,电极端710-714和水平场板716可由不同导电层形成。在形成电极端710-714和水平场板716之后,可沉积ILD区720的后续氧化物层(例如TEOS)以覆盖电极端710-714、水平场板716和第一氧化物层的暴露表面。
图8以简化的平面视图示出根据实施例的处于制造阶段的示例LDMOS晶体管100。在图8中所描绘的实施例中,LDMOS晶体管100形成为椭圆形晶体管,所述椭圆形晶体管具有源极区802、漏极区804、栅极区806和电介质层808,分别对应于图7的源极区502、漏极区504、栅极区202和电介质层402。电介质层808示为允许下层细节可见的透明区。在此实施例中,源极区802被栅极区806包围。漏极区804与栅极区806分开形成,且漏极区804以如图7中所描绘的横向距离508包围栅极区806。形成电介质层808,从而覆盖栅极区806、源极区802和漏极区804的部分以及栅极区806与漏极区804之间的漂移区(未示出)。虚线轮廓区域810和812描绘电介质层808中的开口。举例来说,示例接触件814提供到源极、漏极和栅极区802-806的连接。未示出例如电极端和场板等特征。
图9以简化的平面视图示出根据实施例的处于制造阶段的示例LDMOS晶体管100。在图9中所描绘的实施例中,示出图8的LDMOS晶体管100,其中电介质层808为不透明(阴影)区,从而防止下层细节可见。在此实施例中,源极区部分902经由电介质层808的开口812可见,且栅极区904经由电介质层808的开口810可见。
到目前为止应了解,提供了一种基于沟槽的LDMOS晶体管。形成于半导体衬底中的沟槽填充有导电材料以形成栅极区。栅极电介质形成为沟槽中的内衬,从而将栅极区与衬底隔离。源极区邻近沟槽形成于半导体衬底的表面处。漏极区与沟槽间隔开预定距离形成于半导体衬底的表面处。电介质层形成于栅极区上方且在沟槽与漏极区之间的漂移区上方跨越预定距离。场板形成于电介质层的一部分上方。选择场板和电介质层的尺寸以实现较高击穿电压和改进的RonA。
虽然本文中参考具体实施例描述了本发明,但是可以在不脱离如所附权利要求书中所阐述的本发明的范围的情况下进行各种修改和改变。因此,说明书和图式应在说明性而非限制性意义上看待,并且预期所有这些修改都包括在本发明的范围内。并不意图将本文中关于具体实施例所描述的任何益处、优点或针对问题的解决方案理解为任何或所有权利要求的关键、必需或必不可少的特征或要素。
此外,如本文中所使用,术语“一”被限定为一个或大于一个。另外,权利要求书中对例如“至少一个”和“一个或多个”等引导性短语的使用不应被解释为暗示由不定冠词“一”引导的另一权利要求要素将含有此类引导的权利要求要素的任何特定权利要求限制于仅含有一个此类要素的发明,即使是当同一权利要求包括引导性短语“一个或多个”或“至少一个”和例如“一”等不定冠词时也如此。这同样适用于定冠词的使用。
除非另有陈述,否则例如“第一”和“第二”等术语用于任意地区别此类术语所描述的要素。因此,这些术语未必意图指示此类要素的时间上的优先级或其它优先级。
Claims (10)
1.一种晶体管,其特征在于,包括:
沟槽,其形成于半导体衬底中,所述沟槽具有第一侧壁和第二侧壁;
栅极区,其包括填充于所述沟槽中的导电材料;
漂移区,其邻近所述第二侧壁形成于所述半导体衬底中,所述漂移区具有第一导电类型;
漏极区,其形成于所述漂移区中,所述漏极区与所述第二侧壁间隔开第一距离;
电介质层,其形成于所述半导体衬底的顶表面处,覆盖所述栅极区和所述第二侧壁与所述漏极区之间的所述漂移区;以及
场板,其形成于所述电介质层上方,所述场板借助于所述电介质层与所述导电材料和所述漂移区隔离。
2.根据权利要求1所述的晶体管,其特征在于,所述场板的第一边缘与所述栅极区的一部分重叠,并且所述场板的第二边缘在所述漂移区上方延伸第二距离,所述第二距离小于所述第一距离。
3.根据权利要求1所述的晶体管,其特征在于,另外包括安置于所述沟槽的侧壁和底部处的栅极电介质,所述栅极电介质将所述导电材料与所述半导体衬底隔离。
4.根据权利要求1所述的晶体管,其特征在于,另外包括邻近所述第一侧壁形成于所述半导体衬底中的源极区,所述电介质层的一部分与所述源极区重叠。
5.一种方法,其特征在于,包括:
在半导体衬底中蚀刻沟槽,所述沟槽具有第一侧壁和第二侧壁;
用导电材料填充所述沟槽以形成栅极区;
在所述半导体衬底中邻近所述第二侧壁形成漂移区,所述漂移区具有第一导电类型;
在所述漂移区中形成漏极区,所述漏极区与所述第二侧壁间隔开第一距离;
将在所述半导体衬底的顶表面处的电介质层图案化以覆盖所述栅极区和在所述第二侧壁与所述漏极区之间的所述漂移区;以及
在所述电介质层上方形成场板,所述场板借助于所述电介质层与所述导电材料和所述漂移区隔离。
6.根据权利要求5所述的方法,其特征在于,形成所述场板包括:
形成竖直部分,所述竖直部分具有与所述电介质层的顶表面接触的底表面和延伸穿过层间电介质(ILD)的顶表面;以及
形成水平部分,所述水平部分与所述竖直部分的所述顶表面接触,所述水平部分通过所述ILD与所述电介质层间隔开。
7.根据权利要求5所述的方法,其特征在于,另外包括在用所述导电材料填充所述沟槽之前在所述沟槽的侧壁和底部处形成栅极电介质,所述栅极电介质将所述导电材料与所述半导体衬底隔离。
8.根据权利要求5所述的方法,其特征在于,另外包括在所述半导体衬底中邻近所述第一侧壁形成源极区,所述电介质层的一部分与所述源极区重叠。
9.一种晶体管,其特征在于,包括:
沟槽,其形成于半导体衬底中,所述沟槽具有第一侧壁和第二侧壁;
栅极区,其包括填充于所述沟槽中的导电材料;
栅极电介质,其安置于所述沟槽的侧壁和底部处,所述栅极电介质将所述导电材料与所述半导体衬底隔离;
漂移区,其邻近所述第二侧壁形成于所述半导体衬底中,所述漂移区具有第一导电类型;
漏极区,其形成于所述漂移区中,所述漏极区与所述第二侧壁间隔开第一距离;
主体区,其邻近所述第一侧壁形成于所述半导体衬底中,所述主体区具有第二导电类型;
电介质层,其形成于所述半导体衬底的顶表面处,覆盖所述栅极区和所述第二侧壁与所述漏极区之间的所述漂移区;以及
场板,其形成于所述电介质层上方,所述场板借助于所述电介质层与所述导电材料和所述漂移区隔离。
10.根据权利要求9所述的晶体管,其特征在于,所述场板的第一边缘与所述栅极区的一部分重叠,并且所述场板的第二边缘在所述漂移区上方延伸第二距离,所述第二距离小于所述第一距离。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/692,126 | 2019-11-22 | ||
US16/692,126 US11227921B2 (en) | 2019-11-22 | 2019-11-22 | Laterally-diffused metal-oxide semiconductor transistor and method therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
CN112838124A true CN112838124A (zh) | 2021-05-25 |
Family
ID=75923219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202011312930.2A Pending CN112838124A (zh) | 2019-11-22 | 2020-11-20 | 横向扩散金属-氧化物半导体晶体管及其形成方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US11227921B2 (zh) |
CN (1) | CN112838124A (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117276329A (zh) * | 2023-11-20 | 2023-12-22 | 深圳天狼芯半导体有限公司 | 一种具有沟槽栅的ldmos及制备方法 |
CN117457749A (zh) * | 2023-12-22 | 2024-01-26 | 深圳天狼芯半导体有限公司 | 一种栅极下方具有P型空间层的SiC LMOS及制备方法 |
CN117727634A (zh) * | 2024-02-08 | 2024-03-19 | 粤芯半导体技术股份有限公司 | 金属氧化物半导体器件及其制备方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111092123A (zh) * | 2019-12-10 | 2020-05-01 | 杰华特微电子(杭州)有限公司 | 横向双扩散晶体管及其制造方法 |
US11515416B2 (en) | 2020-09-23 | 2022-11-29 | Nxp Usa, Inc. | Laterally-diffused metal-oxide semiconductor transistor and method therefor |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0173111B1 (ko) | 1988-06-02 | 1999-02-01 | 야마무라 가쯔미 | 트렌치 게이트 mos fet |
US5640034A (en) | 1992-05-18 | 1997-06-17 | Texas Instruments Incorporated | Top-drain trench based resurf DMOS transistor structure |
KR100370957B1 (ko) * | 2000-07-28 | 2003-02-06 | 주식회사 하이닉스반도체 | 트렌치구조의 폴리실리콘 영역을 구비하는 고전압소자 및그 제조방법 |
US6552389B2 (en) | 2000-12-14 | 2003-04-22 | Kabushiki Kaisha Toshiba | Offset-gate-type semiconductor device |
US7719054B2 (en) * | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
US7033891B2 (en) | 2002-10-03 | 2006-04-25 | Fairchild Semiconductor Corporation | Trench gate laterally diffused MOSFET devices and methods for making such devices |
US7576388B1 (en) * | 2002-10-03 | 2009-08-18 | Fairchild Semiconductor Corporation | Trench-gate LDMOS structures |
US7737526B2 (en) * | 2007-03-28 | 2010-06-15 | Advanced Analogic Technologies, Inc. | Isolated trench MOSFET in epi-less semiconductor sustrate |
US7719076B2 (en) * | 2007-08-10 | 2010-05-18 | United Microelectronics Corp. | High-voltage MOS transistor device |
US8350327B2 (en) * | 2008-08-29 | 2013-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage device with reduced leakage |
US20130020632A1 (en) * | 2011-07-18 | 2013-01-24 | Disney Donald R | Lateral transistor with capacitively depleted drift region |
US8999769B2 (en) * | 2012-07-18 | 2015-04-07 | Globalfoundries Singapore Pte. Ltd. | Integration of high voltage trench transistor with low voltage CMOS transistor |
US8860136B2 (en) * | 2012-12-03 | 2014-10-14 | Infineon Technologies Ag | Semiconductor device and method of manufacturing a semiconductor device |
US8962402B1 (en) * | 2013-08-14 | 2015-02-24 | International Business Machines Corporation | Lateral diffusion metal oxide semiconductor (LDMOS) device with tapered drift electrode |
US20160211348A1 (en) | 2015-01-21 | 2016-07-21 | Maxchip Electronics Corp. | Trench lateral diffusion metal oxide semiconductor device and manufacturing method of the same |
KR102286013B1 (ko) * | 2015-10-07 | 2021-08-05 | 에스케이하이닉스 시스템아이씨 주식회사 | 트랜치 절연 필드플레이트 및 금속 필드플레이트를 갖는 수평형 고전압 집적소자 |
US9818862B2 (en) * | 2016-01-05 | 2017-11-14 | Nxp Usa, Inc. | Semiconductor device with floating field plates |
US10424646B2 (en) | 2017-09-26 | 2019-09-24 | Nxp Usa, Inc. | Field-effect transistor and method therefor |
US10522677B2 (en) | 2017-09-26 | 2019-12-31 | Nxp Usa, Inc. | Field-effect transistor and method therefor |
US10600911B2 (en) | 2017-09-26 | 2020-03-24 | Nxp Usa, Inc. | Field-effect transistor and method therefor |
-
2019
- 2019-11-22 US US16/692,126 patent/US11227921B2/en active Active
-
2020
- 2020-11-20 CN CN202011312930.2A patent/CN112838124A/zh active Pending
-
2021
- 2021-12-06 US US17/457,801 patent/US11777002B2/en active Active
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117276329A (zh) * | 2023-11-20 | 2023-12-22 | 深圳天狼芯半导体有限公司 | 一种具有沟槽栅的ldmos及制备方法 |
CN117457749A (zh) * | 2023-12-22 | 2024-01-26 | 深圳天狼芯半导体有限公司 | 一种栅极下方具有P型空间层的SiC LMOS及制备方法 |
CN117457749B (zh) * | 2023-12-22 | 2024-04-09 | 深圳天狼芯半导体有限公司 | 一种栅极下方具有P型空间层的SiC LMOS及制备方法 |
CN117727634A (zh) * | 2024-02-08 | 2024-03-19 | 粤芯半导体技术股份有限公司 | 金属氧化物半导体器件及其制备方法 |
CN117727634B (zh) * | 2024-02-08 | 2024-05-07 | 粤芯半导体技术股份有限公司 | 金属氧化物半导体器件及其制备方法 |
Also Published As
Publication number | Publication date |
---|---|
US11777002B2 (en) | 2023-10-03 |
US20220093752A1 (en) | 2022-03-24 |
US11227921B2 (en) | 2022-01-18 |
US20210159319A1 (en) | 2021-05-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10608092B2 (en) | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts | |
EP3460852B1 (en) | Field-effect transistor and method therefor | |
US8252645B2 (en) | Method of manufacturing trenched MOSFETs with embedded Schottky in the same cell | |
US11777002B2 (en) | Laterally-diffused metal-oxide semiconductor transistor and method therefor | |
US8779510B2 (en) | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts | |
US10600911B2 (en) | Field-effect transistor and method therefor | |
US20070004116A1 (en) | Trenched MOSFET termination with tungsten plug structures | |
US7786528B2 (en) | Metal schemes of trench MOSFET for copper bonding | |
US10424646B2 (en) | Field-effect transistor and method therefor | |
US9991378B2 (en) | Trench power semiconductor device | |
US20170200822A1 (en) | Double gate trench power transistor and manufacturing method thereof | |
US20210234023A1 (en) | Lateral trench transistor device | |
EP3955316A2 (en) | Transistor device with buried field electrode connection | |
US11961907B2 (en) | Laterally-diffused metal-oxide semiconductor transistor and method therefor | |
US11335803B2 (en) | Source-down transistor with vertical field plate | |
CN117995839A (zh) | 半导体装置及其形成方法 | |
CN116741797A (zh) | 半导体结构以及埋入式场板结构的制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |