CN112838056A - Method for producing semiconductor chip - Google Patents
Method for producing semiconductor chip Download PDFInfo
- Publication number
- CN112838056A CN112838056A CN202011643856.2A CN202011643856A CN112838056A CN 112838056 A CN112838056 A CN 112838056A CN 202011643856 A CN202011643856 A CN 202011643856A CN 112838056 A CN112838056 A CN 112838056A
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- CN
- China
- Prior art keywords
- semiconductor
- semiconductor chip
- wafer
- manufacturing
- etching step
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor chip, which comprises the following steps: the invention provides a method for manufacturing a semiconductor device, comprising the steps of filling a circuit pattern having irregularities on a wafer with a liquid photocurable adhesive, curing the photocurable adhesive on the wafer to form an adhesive layer, forming a recess at the transition between a first main face and each side face of each semiconductor chip, disposing a metal layer on a second main face and on the plurality of side faces, wherein the metal layer is not deposited on the curved surface inside the recess, by performing a series of steps of back-surface grinding and then cutting the semiconductor wafer on a light-transmitting support to divide the semiconductor wafer into semiconductor chips, fixing the semiconductor wafer on a hard light-transmitting support through the adhesive layer, whereby the wafer can be ground to a very small thickness without causing any damage and can also be cut without generating debris.
Description
Technical Field
The invention relates to the technical field of semiconductor chip manufacturing, in particular to a method for manufacturing a semiconductor chip.
Background
In the semiconductor industry, in response to thinning of packages or high-density packages, thinning of semiconductor wafers is performed by the stacked-chip technique, thinning is performed by so-called back-surface grinding in which the surface of the wafer is ground in the side opposite to the pattern forming surface (circuit surface), and, in general, in the conventional method and transport of performing the back-surface thinning, although the wafer is held only by the back-grinding protective tape, thinning can be practically accomplished only to a thickness of about 150 μm, because of the problem that the wafer having the protective tape after grinding is warped or the thickness uniformity at the grinding place is low, in order to solve these problems, polyethylene terephthalate (PET) having high hardness and large thickness (from 100 to 200 μm) was used as a substrate of the post-grinding protective tape, whereby a semiconductor wafer having a thickness of about 50 μm could be manufactured.
Meanwhile, the thinned semiconductor wafer is cut into individual chips by a cutting step called a dicing process, and particularly, in obtaining chips from a semiconductor wafer thinned to a very small thickness of 50 μm or less, low yield in the dicing process becomes a problem because chipping is generated at the cut portion of the semiconductor wafer in contact with the pressure-sensitive adhesive sheet in a general method of cutting the semiconductor wafer thinned by back-surface grinding and laminated to a pressure-sensitive adhesive tape called a dicing tape.
Disclosure of Invention
An object of the present invention is to provide a method for manufacturing a semiconductor chip to solve the problems set forth in the above background art.
In order to achieve the purpose, the invention provides the following technical scheme: a method for fabricating a semiconductor chip, the method comprising: structuring a semiconductor substrate to produce a plurality of semiconductor chips, such that each semiconductor chip comprises a first main face and a plurality of side faces, coating a photothermal conversion layer comprising a light absorber and a thermally decomposable resin on a light-transmissive support, filling a liquid photocurable adhesive in the circuit pattern of the irregularities on the wafer, curing the photocurable adhesive on the wafer to form an adhesive layer, forming recesses at the transition between the first main face and the respective side faces of each semiconductor chip, arranging a metal layer onto the second main face and onto the plurality of side faces, wherein the metal layer is not deposited onto the curved surfaces within the recesses.
Preferably, a die bonding tape is secured to the semiconductor wafer prior to dicing the ground semiconductor wafer.
Preferably, the photothermal conversion layer comprises carbon black and/or a transparent filler.
Preferably, laminating the semiconductor wafer and the light-transmitting support by the photocurable adhesive is performed in vacuum.
Preferably, the forming a recess comprises performing an etching step, the etching step comprising an isotropic etching step, the structuring the semiconductor substrate comprises performing an etching step, the etching step comprising an anisotropic etching step.
Preferably, the semiconductor wafer is ground to a thickness of 50 μm or less.
Preferably, the semiconductor substrate is polished, and the semiconductor chip is polished after structuring the semiconductor substrate.
Compared with the prior art, the invention has the beneficial effects that:
1. a series of steps of performing back surface grinding and then cutting the semiconductor wafer on the light-transmitting support to divide the semiconductor wafer into semiconductor chips, fixing the semiconductor wafer on the hard light-transmitting support through an adhesive layer, whereby the wafer can be ground to a very small thickness without causing any damage and can also be cut without generating chips.
2. A photothermic conversion layer is disposed between the semiconductor chip and the light-transmissive support, which decomposes under irradiation of radiant energy, such as laser light, and enables separation of the semiconductor chip from the support with minimal or no damage.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "front", "rear", "both ends", "one end", "the other end", etc., indicate orientations or positional relationships based on specific indicated orientations or positional relationships, and are only used for convenience of description and simplification of description, but do not indicate or imply that the indicated device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "disposed," "connected," and the like are to be construed broadly, such as "connected," which may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As shown below, which illustrate specific embodiments of the present invention: structuring a semiconductor substrate to produce a plurality of semiconductor chips such that each semiconductor chip includes a first main face and a plurality of side faces, coating a photothermal conversion layer including a light absorber and a thermally decomposable resin on a light-transmitting support, the photothermal conversion layer being capable of converting radiation into heat upon irradiation of radiant energy, filling a liquid photocurable adhesive in the circuit pattern of the unevenness on the wafer, curing the photocurable adhesive on the wafer to form an adhesive layer, thereby forming a laminated body having a non-circuit surface on an outer surface to separate the semiconductor chips from the support, forming recesses at transition points between the first main face and the respective side faces of each semiconductor chip, arranging a metal layer onto a second main face and onto the plurality of side faces, wherein the metal layer is not deposited onto curved surfaces in the recesses, by providing the recess, no problems will occur with the subsequent deposition of the metal layer, since the metal layer cannot be deposited on the masked surface area of the recess, so that the metal layer will not be deposited as a contiguous layer mechanically connecting adjacent semiconductor chips.
Preferably, the die bonding tape is fixed to the semiconductor wafer before the ground semiconductor wafer is diced, which can effectively prevent damage to the semiconductor wafer during dicing.
Preferably, the photothermal conversion layer contains carbon black capable of significantly reducing the peeling force, i.e., the force required to separate the semiconductor chip from the support after irradiation of radiant energy, while accelerating the separation, and/or a transparent filler for preventing re-adhesion of the photothermal conversion layer separated by the void layer formed by thermal decomposition of the thermally decomposable resin.
Preferably, the lamination of the semiconductor wafer and the light-transmitting support by the photocurable adhesive is performed in vacuum, the light-transmitting support must be a material capable of transmitting radiant energy such as laser used in the present invention or light for curing the photocurable adhesive, holding the semiconductor wafer in a flat state and without damage during grinding or transportation, and the main function of the support is to enhance the strength of the wafer.
Preferably, the forming of the recess includes performing an etching step, the etching step includes an isotropic etching step, and the structuring of the semiconductor substrate includes performing an etching step, the etching step includes an anisotropic etching step, so that the semiconductor is formed into an effect of concave-convex or hollow-out molding.
Preferably, the semiconductor wafer is polished to a thickness of 50 μm or less in order to obtain thickness uniformity of the semiconductor wafer after polishing.
Preferably, the semiconductor substrate is polished, and after the semiconductor substrate is structured, the semiconductor chip is polished to remove a trace amount of material from the surface of the processed chip, so that the dimensional accuracy of the workpiece can meet the requirement.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A method for fabricating a semiconductor chip, the method comprising: structuring a semiconductor substrate to produce a plurality of semiconductor chips, such that each semiconductor chip comprises a first main face and a plurality of side faces, coating a photothermal conversion layer comprising a light absorber and a thermally decomposable resin on a light-transmissive support, filling a liquid photocurable adhesive in the circuit pattern of the irregularities on the wafer, curing the photocurable adhesive on the wafer to form an adhesive layer, forming recesses at the transition between the first main face and the respective side faces of each semiconductor chip, arranging a metal layer onto the second main face and onto the plurality of side faces, wherein the metal layer is not deposited onto the curved surfaces within the recesses.
2. A method for manufacturing a semiconductor chip according to claim 1, characterized in that: before cutting the ground semiconductor wafer, a die bonding tape is secured to the semiconductor wafer.
3. A method for manufacturing a semiconductor chip according to claim 2, characterized in that: the photothermal conversion layer comprises carbon black and/or a transparent filler.
4. A method for manufacturing a semiconductor chip according to claim 1, characterized in that: laminating the semiconductor wafer and the light-transmitting support by a light curable adhesive is performed in vacuum.
5. A method for manufacturing a semiconductor chip according to claim 1, characterized in that: the forming a recess comprises performing an etching step, the etching step comprising an isotropic etching step, the structuring the semiconductor substrate comprises performing an etching step, the etching step comprising an anisotropic etching step.
6. A method for manufacturing a semiconductor chip according to claim 5, characterized in that: the semiconductor wafer is ground to a thickness of 50 μm or less.
7. A method for manufacturing a semiconductor chip according to claim 1, characterized in that: the semiconductor substrate is ground, and the semiconductor chip is ground after the semiconductor substrate is structured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011643856.2A CN112838056A (en) | 2020-12-31 | 2020-12-31 | Method for producing semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011643856.2A CN112838056A (en) | 2020-12-31 | 2020-12-31 | Method for producing semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112838056A true CN112838056A (en) | 2021-05-25 |
Family
ID=75927162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011643856.2A Pending CN112838056A (en) | 2020-12-31 | 2020-12-31 | Method for producing semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112838056A (en) |
-
2020
- 2020-12-31 CN CN202011643856.2A patent/CN112838056A/en active Pending
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