CN112820639A - Improved preparation process of silicon carbide MOSFET device - Google Patents
Improved preparation process of silicon carbide MOSFET device Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 16
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 79
- 229910052757 nitrogen Inorganic materials 0.000 claims description 40
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 32
- 238000006243 chemical reaction Methods 0.000 claims description 28
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- 238000000137 annealing Methods 0.000 claims description 18
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- 239000000243 solution Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910052681 coesite Inorganic materials 0.000 claims description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims description 9
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- 238000004519 manufacturing process Methods 0.000 claims description 7
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- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 3
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- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/045—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide passivating silicon carbide surfaces
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
The invention belongs to the technical field of microelectronic device preparation, and discloses an improved preparation process of a silicon carbide MOSFET device, which comprises the following steps: (1) cleaning a SiC wafer by adopting an RCA process, (2) carrying out plasma surface treatment on the silicon carbide wafer cleaned in the step (1), (3) depositing a silicon film on the surface of the treated silicon carbide wafer, (4) oxidizing the deposited silicon film to prepare a gate oxide film, and (5) finishing the preparation of the silicon carbide MOSFET device by gluing, photoetching, corrosion, photoresist removal, ion implantation and electrode evaporation. The compactness and the breakdown resistance of the gate oxide film prepared by the process are obviously enhanced, the defect state density of the interface of a semiconductor and an oxide layer is obviously reduced, the voltage stability of an MOS (metal oxide semiconductor) device is improved, and the defects of poor interface quality, incapability of accurately controlling the thickness of the oxide film and the like caused by direct oxidation of SiC are avoided to a certain extent.
Description
Technical Field
The invention relates to a preparation process of an improved silicon carbide MOSFET device, belonging to the technical field of microelectronic device preparation.
Background
The silicon carbide semiconductor has large forbidden band width (3.26eV), high critical breakdown field strength (3MV/cm) and high thermal conductivity (3.3-4.9W cm)-1K-1) High carrier saturation drift velocity (2X 10)7cm/s) and the like, and have attracted extensive attention from researchers. With the continuous development and commercialization of silicon carbide power devices in recent years, silicon carbide MOSFETs are widely used in important fields such as new energy power automobiles, power systems, rail transit, aerospace and the like.
Silicon carbide MOSFET devices are expected to be low-loss fast power conversion devices, and although commercialization has been achieved at present, the quality of the interface between the silicon carbide and the oxide layer greatly limits device performance. The interface state density of the silicon carbide and the oxidation layer reaches 1013eV-1cm-2Above, even after NO annealing, which is currently the mainstream in industry, the density of interface defect states is 1011–1012eV-1cm-2This is 1-2 orders of magnitude higher than the silicon and silicon dioxide interface state density. The high density of interface defects can trap carriers in the channel, and seriously affect the channel mobility and voltage stability of the device. In addition, the compactness, the breakdown resistance and the like of the gate oxide layer are also closely related to the performance of the device. The quality and the interface characteristics of the oxide layer are not only related to the processing mode in the oxidation process, but also necessarily related to the preparation mode of the gate oxide layer. The effective and common preparation method of the gate oxide layer at the present stage is realized by direct thermal oxidation of silicon carbide, and then an annealing process after oxidation is adopted to optimize the interface characteristic and the quality of an oxide film, so that although the state density of the interface defect can be reduced to a certain degree, negative effects can be generated on the threshold voltage stability and the oxide layer insulation characteristic of a device. Based on liu ice et al [ published: CN105355561B]The developed N and H mixed plasma surface treatment technology proposes surface plasma treatmentThe self-stop oxidation technology of the deposited silicon film is combined, the defects that the interface quality is poor, the thickness of the oxide film cannot be accurately controlled and the like caused by direct oxidation of SiC are overcome, the quality of the oxide film is obviously improved, the interface state defect is reduced, and the voltage stability of an MOS device is improved.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide an improved preparation process of a silicon carbide MOSFET device. The process avoids the defects of poor interface quality, incapability of accurately controlling the thickness of the oxide film and the like caused by direct oxidation of SiC to a certain extent, improves the compactness and the breakdown resistance of the oxide film, obviously reduces the defect state density of the interface of a semiconductor and an oxide layer, and improves the voltage stability and the reliability of an MOS device.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention is as follows: a preparation process of an improved silicon carbide MOSFET device comprises the following steps:
(a) placing the silicon carbide wafer in a mixed solution of concentrated sulfuric acid and hydrogen peroxide, cleaning for 15-60 min at 70-100 ℃, and leaching the surface of the silicon carbide wafer for several times by using deionized water, wherein the volume ratio of the concentrated sulfuric acid to the hydrogen peroxide is 1: 1;
(b) taking out the silicon carbide wafer in the substep (a), placing the silicon carbide wafer in a first cleaning solution, cleaning for 3-10 min at 70-85 ℃, then cleaning with a hydrofluoric acid aqueous solution with the concentration of 0.1-10%, and rinsing the surface of the silicon carbide wafer for several times with deionized water, wherein the first cleaning solution is a mixed solution composed of water, hydrogen peroxide and ammonia water according to the volume ratio of 5:1: 1-7: 2: 1;
(c) taking out the silicon carbide wafer in the substep (b), placing the silicon carbide wafer in a second cleaning solution, cleaning for 3-10 min at 70-85 ℃, then cleaning with a hydrofluoric acid aqueous solution with the concentration of 0.1-10%, and rinsing the surface of the silicon carbide wafer for several times with deionized water, wherein the second cleaning solution is a mixed solution composed of water, hydrogen peroxide and hydrochloric acid according to the volume ratio of 5:1: 1-8: 2: 1;
(d) taking out the silicon carbide wafer in the substep (c), and drying the surface of the silicon carbide wafer by using an infrared lamp;
The invention has the beneficial effects that: a preparation process of an improved silicon carbide MOSFET device comprises the following steps: (1) cleaning a SiC wafer by adopting an RCA process, (2) carrying out plasma surface treatment on the silicon carbide wafer cleaned in the step (1), (3) depositing a silicon film on the surface of the treated silicon carbide wafer, (4) oxidizing the deposited silicon film to prepare a gate oxide film, and (5) finishing the preparation of the silicon carbide MOSFET device by gluing, photoetching, corrosion, photoresist removal, ion implantation and electrode evaporation. The compactness and the breakdown resistance of the gate oxide film prepared by the process are obviously enhanced, the defect state density of the interface of a semiconductor and an oxide layer is obviously reduced, the voltage stability of an MOS (metal oxide semiconductor) device is improved, and the defects of poor interface quality, incapability of accurately controlling the thickness of the oxide film and the like caused by direct oxidation of SiC are avoided to a certain extent.
Drawings
FIG. 1 is a flow chart of the process steps of the present invention.
FIG. 2 is a J-E characteristic graph of the SiC MOS capacitor.
FIG. 3 is a graph of interface state density extracted by the hi-lo method.
FIG. 4 is a graph of the C-V test for stress at 423K.
In the figure: (a) the curve diagram of the device prepared by directly depositing the Si film after RCA cleaning, (b) the curve diagram of the device prepared by combining RCA cleaning with N plasma treatment and then depositing the Si film, and (C) the curve diagram of the device prepared by combining RCA cleaning with NH plasma treatment and then depositing the Si film.
Fig. 5 is a graph of transfer characteristics of a SiC MOSFET.
Detailed Description
The present invention will be further described with reference to the following examples.
Example 1
As shown in fig. 1, a process for fabricating an improved silicon carbide MOSFET device comprises the steps of:
(a) placing the silicon carbide wafer in a mixed solution of concentrated sulfuric acid and hydrogen peroxide, cleaning for 20min at 80 ℃, and leaching the surface of the silicon carbide wafer for several times by using deionized water, wherein the volume ratio of the concentrated sulfuric acid to the hydrogen peroxide is 1: 1;
(b) taking out the silicon carbide wafer in the substep (a), placing the silicon carbide wafer in a first cleaning solution, cleaning for 5min at 80 ℃, then cleaning with a hydrofluoric acid aqueous solution with the concentration of 1%, and rinsing the surface of the silicon carbide wafer for a plurality of times by using deionized water, wherein the first cleaning solution is a mixed solution composed of water, hydrogen peroxide and ammonia water according to the volume ratio of 7:2: 1;
(c) taking out the silicon carbide wafer in the substep (b), placing the silicon carbide wafer in a second cleaning solution, cleaning for 5min at 80 ℃, then cleaning with a hydrofluoric acid aqueous solution with the concentration of 1%, and rinsing the surface of the silicon carbide wafer for a plurality of times with deionized water, wherein the second cleaning solution is a mixed solution composed of water, hydrogen peroxide and hydrochloric acid according to the volume ratio of 8:2: 1;
(d) taking out the silicon carbide wafer in the substep (c), and drying the surface of the silicon carbide wafer by using an infrared lamp;
And 3, transferring the silicon carbide wafer treated in the step 2 into a CVD reaction chamber, and introducing high-purity silane and argon, wherein the flow rate of silane gas is 60sccm, the flow rate ratio of silane to argon is 1:50, and the vacuum degree of the reaction chamber is 10-6And Torr, the reaction temperature is 700 ℃, the reaction time is 15min, and the thickness of the deposited silicon film is tested to be 35nm by a step meter.
And 4, transferring the silicon carbide wafer in the step 3 to a high-temperature oxidation furnace for oxidation at the oxidation temperature of 700 ℃ for 300min, introducing nitrogen with the flow of 450sccm after oxidation for annealing treatment for 30min, and then cooling to room temperature under the atmosphere of nitrogen.
Example 2
And 3, transferring the silicon carbide wafer treated in the step 2 into a CVD reaction chamber, and introducing high-purity silane and argon, wherein the flow rate of silane gas is 60sccm, the flow rate ratio of silane to argon is 1:50, and the vacuum degree of the reaction chamber is 10-6And Torr, the reaction temperature is 700 ℃, the reaction time is 15min, and the thickness of the deposited silicon film is tested to be 35nm by a step meter.
And 4, transferring the silicon carbide wafer in the step 3 to a high-temperature oxidation furnace for oxidation at the oxidation temperature of 700 ℃ for 300min, introducing nitrogen with the flow of 450sccm after oxidation for annealing treatment for 30min, and then cooling to room temperature under the atmosphere of nitrogen.
Example 3
And 3, transferring the silicon carbide wafer treated in the step 2 into a CVD reaction chamber, and introducing high-purity silane and argon, wherein the flow rate of silane gas is 60sccm, the flow rate ratio of silane to argon is 1:50, and the vacuum degree of the reaction chamber is 10-6And Torr, the reaction temperature is 700 ℃, the reaction time is 15min, and the thickness of the deposited silicon film is tested to be 35nm by a step meter.
And 4, transferring the silicon carbide wafer in the step 3 to a high-temperature oxidation furnace for oxidation at the oxidation temperature of 700 ℃ for 300min, introducing nitrogen with the flow of 450sccm after oxidation for annealing treatment for 30min, and then cooling to room temperature under the atmosphere of nitrogen.
By analyzing the results of the first three examples, it is found that when N is present2When the plasma processing temperature is 400 ℃, the quality of the grown surface silicon film is better, the surface is smoother, and the prepared SiC/SiO2The interface quality is better, and the density of interface defect states is obviously reduced.
Example 4
And 3, transferring the silicon carbide wafer treated in the step 2 into a CVD reaction chamber, and introducing high-purity silane and argon, wherein the flow rate of silane gas is 60sccm, the flow rate ratio of silane to argon is 1:50, and the vacuum degree of the reaction chamber is 10-6And Torr, the reaction temperature is 700 ℃, the reaction time is 15min, and the thickness of the deposited silicon film is tested to be 35nm by a step meter.
And 4, transferring the silicon carbide wafer in the step 3 to a high-temperature oxidation furnace for oxidation at the oxidation temperature of 700 ℃ for 300min, introducing nitrogen with the flow of 450sccm after oxidation for annealing treatment for 30min, and then cooling to room temperature under the atmosphere of nitrogen.
Example 5
And 3, transferring the silicon carbide wafer treated in the step 2 into a CVD reaction chamber, and introducing high-purity silane and argon, wherein the flow rate of silane gas is 60sccm, the flow rate control ratio of silane to argon is 1:50, and the vacuum degree of the reaction chamber is 10-6And Torr, the reaction temperature is 700 ℃, the reaction time is 15min, and the thickness of the deposited silicon film is tested to be 35nm by a step meter.
In the step 4, the wafer in the step 3 is transferred to a high-temperature oxidation furnace for oxidation at the oxidation temperature of 700 ℃ for 300min, nitrogen with the flow of 450sccm is introduced for annealing treatment for 30min after oxidation, and then the temperature is reduced to room temperature under the atmosphere of nitrogen.
As can be seen from example 5, when H is used2：N2The mixed gas of 10:1 is used for carrying out plasma treatment on the surface of SiC, and when the treatment temperature is 400 ℃, the deposited Si film has better quality and lower roughness. Therefore, the interface defect state density of the prepared MOS device is also lower, and the device performance is obviously improved.
Example 6
And 3, transferring the silicon carbide wafer treated in the step 2 into a CVD reaction chamber, and introducing high-purity silane and argon, wherein the flow rate of silane gas is 60sccm, the flow rate control ratio of silane to argon is 1:50, and the vacuum degree of the reaction chamber is 10-6And Torr, the reaction temperature is 700 ℃, the reaction time is 15min, and the thickness of the deposited silicon film is tested to be 35nm by a step meter. In addition to the above-mentioned CVD method for depositing silicon thin films, Physical Vapor Deposition (PVD), plasma enhanced ESPD, and the like can be used. The reaction source can be silane or SiCl4Which isThe reaction temperature of the molecular beam epitaxy is higher than that of PVD and ESPD, and basically needs to be more than 950 ℃, and the reaction temperature of PVD and ESPD can be carried out at 400 ℃.
And 4, transferring the wafer in the step 3 to a high-temperature oxidation furnace for oxidation at 700 ℃ for 300min, introducing nitrogen with the flow of 450sccm after oxidation for annealing treatment for 30min, and then cooling to room temperature under the atmosphere of nitrogen.
Example 7
The reliability of the oxide film was evaluated by the I-V characteristics of the SiC MOS device, as shown in fig. 2; the interface state defect density was extracted by the hi-lo method, in which the frequency of the high-frequency C-V test was set to 1MHz, and the test results are shown in fig. 3. Finally, the electrical properties of the device were evaluated, and the C-V curves of the MOS capacitor under stress and the transfer curves of the MOSFET device were tested, respectively, with the results shown in fig. 4 and 5.
Example 8
According to the improved preparation process of the silicon carbide MOSFET device disclosed by the invention, the atmosphere of surface plasma treatment can also use Cl2、HCl、POCl3、BH3、NH3Etc. combinations of atmospheres may also be used, with possible combinations as shown in table 1.
TABLE 1
The invention has the advantages that: an improved preparation process of a silicon carbide MOSFET device is characterized in that the traditional SiC direct oxidation process is improved by combining surface plasma treatment with self-stop oxidation of a deposited silicon film, and the performance of the silicon carbide MOS device is greatly improved. SiC tables after different kinds of plasma treatmentDepositing a thin layer Si on the surface, and completely oxidizing the thin layer Si by a low-temperature thermal oxidation process to obtain a high-quality gate oxide layer and SiO with low defect state density2the/SiC interface. The interface defect state density can be obviously reduced by combining surface plasma treatment with thermal oxidation of a deposited thin layer Si, and meanwhile, the gate oxide reliability and the threshold voltage stability of the SiC MOS device are improved.
Claims (1)
1. An improved process for fabricating a silicon carbide MOSFET device, comprising the steps of:
step 1, cleaning the SiC wafer by adopting an RCA process, which specifically comprises the following substeps:
(a) placing the silicon carbide wafer in a mixed solution of concentrated sulfuric acid and hydrogen peroxide, cleaning for 15-60 min at 70-100 ℃, and leaching the surface of the silicon carbide wafer for several times by using deionized water, wherein the volume ratio of the concentrated sulfuric acid to the hydrogen peroxide is 1: 1;
(b) taking out the silicon carbide wafer in the substep (a), placing the silicon carbide wafer in a first cleaning solution, cleaning for 3-10 min at 70-85 ℃, then cleaning with a hydrofluoric acid aqueous solution with the concentration of 0.1-10%, and rinsing the surface of the silicon carbide wafer for several times with deionized water, wherein the first cleaning solution is a mixed solution composed of water, hydrogen peroxide and ammonia water according to the volume ratio of 5:1: 1-7: 2: 1;
(c) taking out the silicon carbide wafer in the substep (b), placing the silicon carbide wafer in a second cleaning solution, cleaning for 3-10 min at 70-85 ℃, then cleaning with a hydrofluoric acid aqueous solution with the concentration of 0.1-10%, and rinsing the surface of the silicon carbide wafer for several times with deionized water, wherein the second cleaning solution is a mixed solution composed of water, hydrogen peroxide and hydrochloric acid according to the volume ratio of 5:1: 1-8: 2: 1;
(d) taking out the silicon carbide wafer in the substep (c), and drying the surface of the silicon carbide wafer by using an infrared lamp;
step 2, transferring the silicon carbide wafer cleaned in the step 1 to an electron cyclotron resonance microwave plasma chamber for plasma surface treatment; firstly, a mechanical pump and a molecular pump are adopted to vacuumize a discharge chamber, and when the vacuum degree reaches (1.2-1.5) 10-4Heating to 400-600 ℃ when Pa is needed; subsequently, nitrogen gas is introduced into the discharge chamberThe flow rate is controlled at 40-60 sccm, or hydrogen is introduced, the flow rate is controlled at 40-60 sccm, or mixed gas of nitrogen and hydrogen is introduced, wherein: controlling the flow of hydrogen at 40-60 sccm, controlling the flow control ratio of nitrogen to hydrogen at 1: 5-10, adjusting the microwave power to 600-800W, and then starting a microwave discharge source button of the electron cyclotron resonance microwave plasma for 3-10 min;
step 3, depositing a silicon film on the surface of the treated silicon carbide wafer, transferring the silicon carbide wafer treated in the step 2 into a CVD/PVD/ESPD reaction chamber, wherein the vacuum degree of the reaction chamber is 10-5～10-7Torr is introduced, high-purity silane and argon gas are introduced, the flow ratio of the high-purity silane to the argon gas is controlled to be 1: 50-60, the flow of silane gas is 50-100 sccm, the reaction temperature is 600-800 ℃, the reaction time is controlled to be 10-20 min, and the thickness of the deposited silicon film is 30-40 nm;
step 4, transferring the silicon carbide wafer in the step 3 to a high-temperature oxidation furnace for oxidation, controlling the oxidation temperature at 600-1100 ℃, controlling the oxidation time at 180-300 min, introducing nitrogen with the flow of 400-500 sccm after oxidation for annealing treatment for 20-40 min, and then cooling to room temperature under the atmosphere of nitrogen;
step 5, in the presence of SiO2Gluing, photoetching, corroding, removing glue and injecting ions on the thin silicon carbide wafer to form a source region and a drain region, depositing a metal Al electrode, heating to 350-500 ℃ under the protection of nitrogen, annealing for 10-45 min, and cooling to room temperature to complete the manufacture of the SiC MOSFET.
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