CN112802536A

CN112802536A - Chip testing device and chip testing system

Info

Publication number: CN112802536A
Application number: CN201911106189.1A
Authority: CN
Inventors: 蔡振龙; 基因·罗森塔尔
Original assignee: First Inspection Co Ltd
Current assignee: First Inspection Co Ltd
Priority date: 2019-11-13
Filing date: 2019-11-13
Publication date: 2021-05-14

Abstract

The invention discloses a chip testing device and a chip testing system. The chip testing system comprises a chip testing device and an environment control device. One side of the circuit board of the chip testing device is provided with a plurality of electric connecting seats, and the other side of the circuit board is provided with a plurality of testing modules. The circuit board is clamped by the first fixing component and the second fixing component, and the first fixing component and the second fixing component clamp and fix the electric connection seats on one side of the circuit board, and the electric connection seats and the circuit board are not required to be mutually locked through locking components. When the chip testing device obtains electric power, each testing module can test the chip carried by the electric connection seat connected with the testing module. After the chips are arranged on the electric connection seat, the chips can be arranged in a high-temperature environment or a low-temperature environment together with the chip testing device for testing, and the chips do not need to be repeatedly disassembled and assembled.

Description

Chip testing device and chip testing system

Technical Field

The present invention relates to a chip testing apparatus and a chip testing system, and more particularly, to a chip testing apparatus and a chip testing system suitable for testing a memory.

Background

Generally, before the memory is shipped, the memory must pass a high temperature test, a Burn-In (Burn-In) test, or a high temperature test, a Burn-In test, and a low temperature test. In the existing memory test equipment, when a memory is subjected to high-temperature test, pre-burning test or low-temperature test, the memory must be repeatedly plugged into and pulled out of different electric connection seats, so that the memory pins are easily damaged, and the repeated plugging and pulling wastes a large amount of time, thereby causing the problem of low test efficiency.

Disclosure of Invention

Embodiments of the present invention provide a chip testing apparatus and a chip testing system, which are used to improve the problems that when an existing memory device is tested in different temperature environments, the chip must be repeatedly disassembled and assembled, which results in low testing efficiency and easily causes damage to pins of the memory.

One embodiment of the present invention is a chip testing apparatus for carrying a plurality of chips, the chip testing apparatus being capable of being carried by a carrier and transferred between a plurality of workstations, the chip testing apparatus comprising: the circuit board, its opposite both sides define a first side and a second side separately; the circuit board is provided with a plurality of positioning holes and a plurality of circuit board locking holes, each positioning hole does not penetrate through the circuit board, and each circuit board locking hole penetrates through the circuit board; the fixing assembly comprises a first fixing component and a second fixing component, the first fixing component is arranged on the first side surface, the second fixing component is fixedly arranged on the second side surface, the first fixing component is provided with a plurality of first locking holes, the second fixing component is provided with a plurality of second locking holes, and the plurality of first locking holes, the plurality of circuit board locking holes and the plurality of second locking holes are correspondingly arranged; the circuit board is fixed between the first fixing component and the second fixing component; each electric connecting seat is provided with an electric connecting seat body; one side of each electric connection seat body is used for bearing a chip, the other side of the electric connection seat body is provided with at least two positioning pieces, each positioning piece is mutually clamped with the plurality of positioning holes, and each electric connection seat is fixedly arranged on the first side surface of the circuit board; the first fixing member comprises a plurality of pressing structures which are correspondingly pressed against a part of the electric connection seats, each electric connection seat is pressed by the first fixing member and fixed on the first side surface of the electric connection seat, the first fixing member comprises a plurality of through holes, and a part of each electric connection seat is correspondingly exposed out of one through hole; the control unit is arranged on the second side face of the circuit board and comprises a plurality of test modules, and each test module is connected with one part of the electric connecting seats; the second fixing piece is provided with a plurality of avoidance holes, and a part of the plurality of test modules penetrates through the plurality of avoidance holes; at least one power supply component connected with the circuit board; the chip testing device is connected with a power supply device through a power supply component to obtain the power required by the operation of each testing module; the power supply equipment is connected with at least one work station; when the chip testing device obtains power from the power supply equipment through the power supply component, each testing module can perform a preset testing program on the chips on the plurality of electric connection seats connected with the testing module.

Preferably, each test module comprises: a Pattern Generator (PG), a Device Power supply module (DPS), and a Driver circuit (Driver); the chip is a memory, and the predetermined test program comprises: at least one of a read test, a write test, and an electrical test; the plurality of electric connection seats are divided into a plurality of electric connection seat groups, and each electric connection seat group comprises at least one electric connection seat; the plurality of test modules are connected with the plurality of electric connection seat groups, and each test module is connected with all the electric connection seats in the corresponding electric connection seat group; the plurality of test modules are connected with the plurality of electric connection seat groups, and each test module is connected with all the electric connection seats in the corresponding electric connection seat group.

Preferably, each of the pressing structures is detachably fixed to the first fixing member, each of the first fixing members has a plurality of group receiving holes, and each of the group receiving holes is configured to receive a plurality of electrical connectors in the same electrical connector group.

Preferably, the circuit board is formed with a plurality of first contact structures on the second side, each test module has at least one second contact structure, and the second contact structure of each test module can detachably contact with one of the first contact structures.

Preferably, the power supply member includes a plurality of connection terminals, the plurality of connection terminals are disposed on the first side surface of the circuit board, and the plurality of connection terminals are exposed from the first fixing member; the plurality of connecting terminals are used for being connected with the plurality of accommodating chamber terminals of one of the workstations; when the plurality of connecting terminals and the plurality of accommodating chamber terminals are connected with each other, the power supply equipment can supply power to the chip testing device.

Preferably, the power supply member is a receiving antenna for coupling with a transmitting antenna of the power supply device, and the chip testing apparatus can wirelessly receive the power transmitted by the power supply device through the receiving antenna.

Preferably, the chip testing device further includes at least one first data transmission terminal disposed on the circuit board and exposed from the first fixing member, the first data transmission terminal being configured to contact with at least one second data transmission terminal of one of the workstations for mutual data transmission.

Preferably, the chip testing device further comprises at least one first data transmission antenna, and the first data transmission antenna is used for wirelessly transmitting data with at least one second data transmission antenna of one of the workstations.

Preferably, after each test module completes a predetermined test program for the chips on the plurality of electrical sockets connected thereto, the test module writes test result data and test parameter data of each chip into the chip, so that the test result data and the test parameter data are stored in each chip.

Preferably, each electrical connection socket comprises: the electric connecting seat body is provided with a top wall and an annular side wall, the top wall is provided with an opening, one end of the annular side wall is connected with the periphery of the top wall, the other end of the annular side wall is abutted against the circuit board, and the top wall, the annular side wall and the circuit board form a containing groove together; two opposite side surfaces of the top wall are defined as an outer side surface and an inner side surface, and the inner side surface is positioned in the accommodating groove; the supporting structure is abutted against the circuit board and is positioned in the accommodating groove, the supporting structure comprises a plurality of positioning holes, and each positioning hole is provided with a positioning piece; the lifting structure is arranged in the accommodating groove and is provided with a base part and a bearing part, the base part is positioned in the accommodating groove, the base part extends towards one side to form the bearing part, and at least one part of the bearing part is positioned in the opening; the bearing part extends to one side far away from the base part to form a plurality of limiting parts, at least one part of the limiting parts penetrates through the hole, and a chip containing groove is formed by the limiting parts and the bearing part together and is used for containing a chip; the lifting structure is also provided with a plurality of connecting holes which penetrate through the base part and the bearing part; the elastic components are arranged in the accommodating groove, one end of each elastic component is fixed to the lifting structure, the other end of each elastic component is fixed to the supporting structure, the elastic restoring force generated by the compression of the elastic components enables the base part to abut against the inner side surface of the top wall, and a gap is formed between the lifting structure and the supporting structure; one end of each probe assembly is fixedly arranged on the supporting structure, the other end of each probe assembly abuts against the contact structure of the circuit board, and the other ends of the probe assemblies penetrate through the connecting holes; when the chip accommodating groove is provided with the chip and the limiting part is not pressed by a pressing device, the probe assemblies positioned in the connecting holes are not connected with the contact parts of the chip; when the chip accommodating groove is provided with the chip, and the limiting part is pressed by the pressing device and is retracted towards the electric connection seat body, the probe assemblies abut against the contact parts, and the probe assemblies and the chip are connected with each other.

One embodiment of the present disclosure is a chip testing system, which includes: a chip testing device, comprising: the circuit board, its opposite both sides define a first side and a second side separately; the circuit board is provided with a plurality of positioning holes and a plurality of circuit board locking holes, each positioning hole does not penetrate through the circuit board, and each circuit board locking hole penetrates through the circuit board; the fixing assembly comprises a first fixing component and a second fixing component, the first fixing component is arranged on the first side surface, the second fixing component is fixedly arranged on the second side surface, the first fixing component is provided with a plurality of first locking holes, the second fixing component is provided with a plurality of second locking holes, and the plurality of first locking holes, the plurality of circuit board locking holes and the plurality of second locking holes are correspondingly arranged; the circuit board is fixed between the first fixing component and the second fixing component; each electric connecting seat is provided with an electric connecting seat body; one side of each electric connection seat body is used for bearing a chip, the other side of the electric connection seat body is provided with at least two positioning pieces, each positioning piece is mutually clamped with the plurality of positioning holes, and each electric connection seat is fixedly arranged on the first side surface of the circuit board; the first fixing member comprises a plurality of pressing structures which are correspondingly pressed against a part of the electric connection seats, each electric connection seat is pressed by the first fixing member and fixed on the first side surface of the electric connection seat, the first fixing member comprises a plurality of through holes, and a part of each electric connection seat is correspondingly exposed out of each through hole; the control unit is arranged on the second side face of the circuit board and comprises a plurality of test modules, and each test module is connected with one part of the electric connecting seats; the second fixing component is provided with a plurality of avoidance holes, and one part of the plurality of test modules penetrates through one avoidance hole; at least one power supply component connected with the circuit board; a central control device; an environmental control apparatus, comprising: the equipment body comprises a plurality of accommodating chambers and is connected with power supply equipment; another power supply component is arranged in each accommodating chamber, and the power supply component in each accommodating chamber is connected with power supply equipment; the air extracting device is connected with each accommodating chamber and is connected with the central control device; the air extracting device can be controlled by the central control device to extract the air around the chips carried by the chip testing device outwards; a plurality of temperature adjusting devices arranged on the equipment body, wherein each accommodating chamber is provided with one temperature adjusting device; each temperature adjusting device can be controlled by the central control device to increase or decrease the temperature around the plurality of chips carried by the chip testing device; when the chip testing device is arranged in one of the accommodating chambers, the power supply equipment can provide power for the chip testing device through the power supply component in the accommodating chamber and the power supply component of the chip testing device; when the power supply equipment supplies power to the chip testing device, each testing module can perform a preset testing program on the chips borne by the plurality of electric connection seats connected with the testing module.

Preferably, each abutting structure is detachably fixed with the first fixing member, each first fixing member is provided with a plurality of group containing holes, and each group containing hole is used for containing a plurality of electric connecting seats in the same electric connecting seat group; each abutting structure body is in a fence shape, each abutting structure body is provided with a plurality of through holes, and one part of each electric connecting seat is correspondingly exposed out of each through hole.

Preferably, the power supply member includes a plurality of connection terminals, the plurality of connection terminals are disposed on the first side surface of the circuit board, and the plurality of connection terminals are exposed from the first fixing member; a plurality of accommodating chamber terminals are arranged in each accommodating chamber; when the plurality of connecting terminals are connected with the plurality of accommodating chamber terminals in one accommodating chamber, the power supply equipment can supply power to the chip testing device.

Preferably, the chip testing device further comprises at least one first data transmission terminal, the first data transmission terminal is arranged on the circuit board and exposed out of the first fixing member, each accommodating chamber comprises at least one second data transmission terminal, and the second data transmission terminal is connected with the central control device; the first data transmission terminals can be in contact with the second data transmission terminals in the respective receiving chambers, and the chip testing device can transmit information to the central control device.

Preferably, the chip testing device further comprises at least one first data transmission antenna, the equipment body is provided with at least one second data transmission antenna, and the second data transmission antenna is connected with the central control device; the chip testing device can wirelessly transmit data with the central control device through the first data transmission antenna and the second data transmission antenna.

Preferably, each accommodating chamber is also provided with a cover body; when the chip testing device is arranged in one of the accommodating chambers and the chip testing device is powered on, the cover body in the accommodating chamber is correspondingly covered on the first fixing member, the cover body, the first fixing member and the circuit board form a closed space together, the plurality of electric connection seats are correspondingly positioned in the closed space, and the air exhaust device can be controlled to exhaust air in the closed space outwards.

Preferably, each accommodating chamber is also provided with a lifting device, and each lifting device is connected with the central control device; each lifting device can be controlled by the central control device so as to enable the chip testing device to approach or move away from the cover body.

To sum up, the chip testing device and the chip testing system including the chip testing device disclosed in the embodiments of the present invention are applied to the memory testing operation, and the chip testing device and the chips carried by the chip testing device can be disposed in a high temperature environment or a low temperature environment (for example, in a containing chamber of an environmental control device) through the related robot arm, and then the chip testing device is powered on, so that the chips can be tested, that is, the chips are not required to be detached from the electrical connection socket regardless of whether the chips are tested in the high temperature environment or the low temperature environment, so that the overall testing time can be greatly reduced, and the problem that the memory is easily damaged due to continuous detachment and installation of the existing memory testing device can be avoided.

Drawings

FIG. 1 is a schematic diagram of a chip testing system according to the disclosure.

FIG. 2 is a block diagram of a chip testing system according to the present disclosure.

FIG. 3 is a schematic diagram of a chip testing apparatus according to the disclosure.

FIG. 4 is a partially exploded view of the chip testing apparatus according to the present invention.

FIG. 5 is another partially exploded view of the chip testing device disclosed in the present invention.

Fig. 6 is a partially enlarged schematic view of the chip testing apparatus disclosed in the present invention.

Fig. 7 is an exploded view of the pressing structure and the fixing body of the chip testing device disclosed in the present invention.

Fig. 8 is an exploded view of the electrical connector and the circuit board of the chip testing device disclosed in the present invention.

Fig. 9 is an exploded view of the test module, the circuit board and the second fixing member of the chip testing apparatus according to the present invention.

FIG. 10 is a block diagram of a chip testing apparatus according to the disclosure.

FIG. 11 is a schematic view of an electrical connector of the chip testing apparatus disclosed in the present invention.

FIG. 12 is an exploded cross-sectional view of an electrical connector of the chip testing apparatus according to the present invention.

Fig. 13 is a schematic cross-sectional view of an electrical connector of a chip testing device without a chip according to the disclosure.

FIG. 14 is a cross-sectional view of an electrical connector with a chip of the chip testing device of the present invention.

Fig. 15 is an exploded view of a pressing structure and a fixing body of another embodiment of the chip testing device disclosed in the present invention.

FIG. 16 is a schematic diagram of an electrical connector of another embodiment of the chip testing apparatus disclosed in the present invention.

FIG. 17 is a diagram of an environment control apparatus of the chip testing system according to the present disclosure.

FIG. 18 is a block diagram of an apparatus and a central control apparatus included in the environmental control device of the chip testing system according to the present invention.

Fig. 19 is an assembly diagram of the temperature adjustment device and the cover of the chip testing system according to the disclosure.

Fig. 20 and 21 are exploded views of a temperature adjustment device and a cover of a chip testing system according to the disclosure.

Fig. 22 is a schematic cross-sectional view illustrating a temperature adjustment device and a cover disposed on a chip testing device of a chip testing system according to the present invention.

Fig. 23 is a partially enlarged cross-sectional view of a temperature adjustment device and a cover disposed on a chip testing device of the chip testing system according to the present invention.

Fig. 24 is a flowchart illustrating a first embodiment of a chip testing system according to the present invention, which tests a plurality of chips by using a chip testing method.

Fig. 25 is a flowchart illustrating a second embodiment of a chip testing system for testing a plurality of chips by using a chip testing method according to the present invention.

Fig. 26 is a flowchart illustrating a third embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the disclosure.

Fig. 27 is a flowchart illustrating a fourth embodiment of testing a plurality of chips by a chip testing method in the chip testing system according to the disclosure.

Fig. 28 is a flowchart illustrating a fifth embodiment of testing a plurality of chips by a chip testing method in the chip testing system according to the present disclosure.

Fig. 29 is a flowchart illustrating a sixth embodiment of testing a plurality of chips by a chip testing method in the chip testing system according to the present disclosure.

Fig. 30 is a flowchart illustrating a seventh embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the disclosure.

Fig. 31 is a flowchart illustrating an eighth embodiment of a chip testing system according to the present invention, wherein the chip testing system tests a plurality of chips by using a chip testing method.

Detailed Description

Referring to fig. 1 to 5 together, fig. 1 is a schematic diagram of a chip testing system disclosed in the present invention, fig. 2 is a schematic block diagram of the chip testing system disclosed in the present invention, fig. 3 is a schematic diagram of a chip testing apparatus disclosed in the present invention, and fig. 4 and 5 are partially exploded schematic diagrams of the chip testing apparatus disclosed in the present invention. The chip test system E disclosed by the invention is used for testing a plurality of chips C. The chip test system E includes: a central control device E1, a chip installation device E2, at least one chip testing device 1, a plurality of environment control devices E3, a transfer device E4 and a sorting device E5.

The central control device E1 is connected with the chip mounting equipment E2, the plurality of environment control equipment E3, the transferring equipment E4 and the sorting equipment E5, and the central control device E1 can control the operation of each equipment; the central control device E1 is, for example, a server, various computer devices, and the like, and is not limited thereto. In practical applications, the central control apparatus E1 may include a plurality of environmental status control apparatuses (e.g., various processors, computers, etc.), and the device body E31 (as shown in fig. 17) of each environmental control device E3 may be correspondingly provided with one environmental status control apparatus, that is, each environmental control device E3 may include one environmental status control apparatus. The chip mounting apparatus E2 may include a robot arm (not shown), which can be controlled by the central control device E1 to take out the chips C on the tray one by one and place the chips C on the electrical connectors 2 of the chip testing apparatus 1 one by one.

The chip testing apparatus 1 is used to carry a plurality of chips C, and the chip testing apparatus 1 can be carried by the transfer equipment E4 and transferred among a plurality of workstations (e.g., a chip mounter E2, a plurality of environmental control equipments E3, a transfer equipment E4, and a sorting equipment E5).

As shown in fig. 3 to 5, the chip test apparatus 1 includes: a circuit board 10, a fixing component 11, a plurality of electrical connectors 2, a control unit 3 and at least one power supply member 4. Two opposite sides of the circuit board 10 are respectively defined as a first side 101 and a second side 102 (as shown in fig. 9). The electrical connection sockets 2 are fixedly disposed on the first side surface 101 of the circuit board 10, and each electrical connection socket 2 is used for carrying a chip C. The form of the electrical connector 2 can vary from chip to chip, without limitation.

The fixing assembly 11 includes a first fixing member 111 and a second fixing member 112. The first fixing member 111 is disposed on the first side 101, and the second fixing member 112 is fixedly disposed on the second side 102. The first fixing member 111 has a plurality of first locking holes 1111, the second fixing member 112 has a plurality of second locking holes 1121, the circuit board 10 has a plurality of circuit board locking holes 103, each first locking hole 1111 is disposed through the first fixing member 111, each second locking hole 1121 is disposed through the second fixing member 112, each circuit board locking hole 103 is disposed through the circuit board 10, and the plurality of first locking holes 1111, the plurality of circuit board locking holes 103, and the plurality of second locking holes 1121 are correspondingly disposed. In practical applications, the number, shape and distribution positions of the first locking holes 1111, the circuit board locking holes 103 and the second locking holes 1121 can be varied according to requirements, and are only an exemplary embodiment.

A plurality of locking members (not shown), such as screws, are locked in the plurality of first locking holes 1111, the plurality of circuit board locking holes 103 and the plurality of second locking holes 1121, and the circuit board 10 is fixed between the first fixing member 111 and the second fixing member 112. That is, the circuit board 10 is clamped between the first fixing member 111 and the second fixing member 112, and the overall structural strength of the circuit board 10 is improved by the arrangement of the first fixing member 111 and the second fixing member 112. In practical applications, the first fixing member 111 and the second fixing member 112 may be made of a high hardness material such as stainless steel; the circuit board 10 may be formed such that only each of the circuit board locking holes 103 is disposed through the circuit board 10, and besides, the circuit board 10 does not have other holes penetrating through the circuit board 10.

In particular, in practical applications, each first lock hole 1111 may not be disposed through the first fixing member 111, and each first lock hole 1111 may be a blind hole, or a part of the first lock holes 1111 may be through holes and another part of the first lock holes 1111 may be blind holes; in the case that the first locking hole 1111 is a blind hole, the corresponding second locking hole 1121 is a through hole penetrating through the second fixing member 112, and in the case that the first locking hole 1111 is a through hole, the second locking hole 1121 may be a blind hole. In other words, each of the second locking holes 1121 may not be disposed through the second fixing member 112, and each of the second locking holes 1121 may be a blind hole, or a part of the second locking holes 1121 may be through holes and another part of the second locking holes 1121 may be blind holes.

Referring to fig. 4, 6 and 7, fig. 6 is a partially enlarged schematic view of a chip testing device disclosed in the present invention, and fig. 7 is an exploded schematic view of a pressing structure and a fixing body of the chip testing device disclosed in the present invention. In practical applications, the first fixing member 111 may include a plurality of pressing structures 1112 and a fixing body 1114, each pressing structure 1112 and the fixing body 1114 are independent from each other, and each pressing structure 1112 is detachably fixed on the fixing body 1114. Each pressing structure 1112 is substantially in the shape of a lattice column, and each pressing structure 1112 is correspondingly formed with a plurality of through holes 1113. When the first fixing member 111 is fixed on the first side 101 of the circuit board 10, the plurality of pressing structures 1112 are pressed against a portion of the electrical connector body 21 of the plurality of electrical connectors 2, and a portion of each electrical connector 2 is exposed to each through hole 1113. That is, in addition to the first fixing member 111 and the second fixing member 112 cooperating with each other to clamp the circuit board 10, the first fixing member 111 is also used to fix the plurality of electrical connectors 2 disposed on the first side 101 of the circuit board 10 to the first side 101 of the circuit board 10.

The fixed body 1114 includes a plurality of group receiving holes 1115, and each group receiving hole 1115 is disposed through the fixed body 1114. Each group receiving hole 1115 is used for receiving a plurality of electrical connectors 2. The fixing body 1114 further includes a plurality of auxiliary fixing portions 1116, each of the auxiliary fixing portions 1116 is formed by extending a sidewall forming each of the group receiving holes 1115 toward the center of the group receiving hole 1115. When the fixing body 1114 is fixed to the circuit board 10, the height of each auxiliary fixing portion 1116 relative to the circuit board 10 is smaller than the depth of each group accommodating hole 1115.

Each of the pressing structures 1112 and the auxiliary fixing portion 1116 may have a plurality of corresponding locking

holes

11121 and 1117, and each of the pressing structures 1112 may be an auxiliary fixing portion 1116 that is locked in each group-containing hole 1115 by a plurality of locking members (not shown), such as screws. When the pressing structure 1112 and the auxiliary fixing portion 1116 are locked together, the pressing structure 1112 will correspondingly press against the pressing portions 213 of the electrical connector bodies 21 of the electrical connectors 2 located in the group receiving holes 1115 (as shown in fig. 7 and described in detail later), and a portion of the electrical connectors 2 is correspondingly exposed through the through holes 1113 of the pressing structure 1112. As shown in fig. 6, in the present embodiment, the side of the pressing structure 1112 opposite to the circuit board 10 is lower than the side of the fixing body 1114 opposite to the circuit board 10, that is, the height from the side of the pressing structure 1112 opposite to the circuit board 10 to the side of the circuit board 10 where the electrical connector 2 is disposed is lower than the height from the side of the fixing body 1114 opposite to the circuit board 10 to the side of the circuit board 10 where the electrical connector 2 is disposed, but not limited thereto; in various embodiments, the pressing structure 1112 on the side opposite to the circuit board 10 may also be flush with the fixing body 1114 on the side opposite to the circuit board 10.

As described above, the first fixing member 111 is fastened to the first side 101 of the circuit board 10 by a plurality of fastening members, and the plurality of pressing structures 1112 of the first fixing member 111 correspondingly press a portion of each electrical connector 2, so that each electrical connector 2 can be directly fixed on the circuit board 10 by the first fixing member 111 in a pressing manner without using screws.

Referring to fig. 6 to 8, fig. 8 is an exploded view of an electrical connector and a circuit board of a chip testing device according to the present invention. On the first side 101 of the circuit board 10, a plurality of sets of electrical contact structures 1011 are formed (only two sets of electrical contact structures 1011 are shown in fig. 8, but the number of electrical contact structures 1011 corresponds to the number of electrical sockets 2). Each set of electrical contact structures 1011 includes a plurality of contact pads 10111 (e.g., metal pads). When each electrical connection socket 2 is pressed by the pressing structure 1112 and fixed on the first side 101 of the circuit board 10, one end of a plurality of probe elements 20 (described in detail later) of the electrical connection socket 2 is correspondingly pressed against a plurality of contact pads 10111 included in the set of electrical contact structures 1011, so that the plurality of probe elements 20 of the electrical connection socket 2 can be electrically connected to electronic components disposed on the circuit board 10 through the plurality of contact pads 10111 when the chip testing apparatus 1 is powered. The number, arrangement, and disposition of the electrical contact structures 1011, the number, shape, arrangement, and the like of the contact pads 10111 of each set of electrical contact structures 1011 can be varied according to requirements, and are shown as an exemplary embodiment.

It should be noted that, in the above description of the present embodiment, the pressing structures 1112 and the fixing body 1114 are taken as independent members, but in practical applications, the pressing structures 1112 and the fixing body 1114 may be integrally formed, that is, the whole first fixing member 111 is in a fence shape.

In practical applications, each contact pad 10111 may be substantially flat and formed on the first side 101 of the circuit board 10, and for the convenience of the relevant personnel or machinery, each electrical connector 2 is correctly disposed on each set of contact structures, the first side 101 of the circuit board 10 may also be recessed to form at least two positioning holes 104 around each set of contact structures, and each positioning hole 104 is not disposed through the circuit board 10. Correspondingly, each electrical connector 2 is configured to abut against one side of the first side surface 101 of the circuit board 10, and may have a positioning element 25, and each positioning element 25 may be engaged with the positioning hole 104, so that, through the mutual cooperation of the positioning element 25 and the positioning hole 104, a relevant person or machine can easily and correctly set the electrical connector 2 on each set of contact structures. In practical applications, the positioning element 25 and the electrical connection socket 2 may be two independent components, or the positioning element 25 may be integrally formed with the base structure 231 of the electrical connection socket 2.

As mentioned above, since each electrical connector 2 is fixedly disposed on the first side 101 of the circuit board 10 only by the pressing of the pressing structure 1112, when assembling the electrical connector 2, the first fixing member 111, the second fixing member 112 and the circuit board 10, the electrical connectors 2 must be disposed on the first side 101 of the circuit board 10 first, and then the first fixing member 111 is locked on the first side 101 of the circuit board 10, in this process, each electrical connector 2 is limited by the positioning element 25 and the positioning hole 104, and each electrical connector 2 is not easy to move relative to the circuit board 10, and related personnel or machinery can easily lock the first fixing member 111 on the first side 101 of the circuit board 10. The number of the positioning members 25 disposed between the single electrical connector 2 and the circuit board 10 is not limited to two in the drawings, and the number thereof can be changed according to the requirement, and the shapes of the positioning members 25 and the positioning holes 104 can also be changed according to the requirement.

In summary, in the chip testing device 1 of the present invention, the first fixing member 111 and the second fixing member 112 are used to cooperate with the plurality of locking members to clamp and fix the plurality of electrical connection sockets 2 on the first side surface 101 of the circuit board 10, so that the electrical connection sockets 2 and the circuit board 10 can not be locked with each other by the locking members, and thus, the number of through holes of the circuit board 10 can be greatly reduced.

Referring to fig. 5 and 9, fig. 9 is an exploded view of a testing module, a circuit board and a second fixing member of the chip testing apparatus according to the present invention. The control unit 3 is disposed on the second side 102 of the circuit board 10. The control unit 3 includes a plurality of test modules 30, and each test module 30 is fixedly disposed on the second side 102 of the circuit board 10. The second fixing member 112 has a plurality of relief holes 1122. When the second fixing member 112 is fixedly disposed on the second side surface 102 of the circuit board 10, a portion of each test module 30 can be correspondingly disposed through the corresponding avoiding hole 1122.

In practical applications, the second side 102 of the circuit board 10 may have a plurality of first contact structures 1021. Each test module 30 may have a test module body 32 and two second contact structures 33, an electronic component for testing the chip C disposed on the electrical connector 2 is disposed in the test module body 32, the second contact structures 33 are exposed at one side of the test module body 32, and the second contact structures 33 of each test module body 32 are used for contacting with the first contact structures 1021 of the circuit board 10. When the second contact structure 33 of each test module 30 contacts the first contact structure 1021 of the circuit board 10, the associated electronic components in each test module 30 can be connected to the associated electronic components disposed on the circuit board 10. In a specific application, the first contact structure 1021 and the second contact structure 33 may be, for example, a board-to-board connector, and the form of the first contact structure may be, for example, but not limited to, a Pogo pin or a reed. The number of the second contact structures 33 of each test module 30 is not limited to two, and may vary according to the type of the second contact structures 33.

Through the design of the first contact structure 1021 and the second contact structure 33, each testing module 30 can be detachably fixed on the second side 102 of the circuit board 10, and through the design of detachably mounting each testing module 30 on the circuit board 10, a user can replace the testing module 30 as required, and related maintenance personnel can also easily disassemble, assemble and maintain a specific testing module 30. As shown in fig. 5 and 9, in practical applications, the testing module body 32 may have two auxiliary fixing structures 321, each auxiliary fixing structure 321 may have a plurality of fixing holes 3211, and the second fixing member 112 may have a plurality of corresponding fixing holes 1123. Each of the testing module bodies 32 can be matched with the fixing holes 3211 and the fixing holes 1123 by a plurality of fasteners (e.g., screws) so that the testing module 30 can be detachably fixed on the second fixing member 112. In practical applications, the auxiliary fixing structure 321 may be integrally formed with the testing module body 32, or the auxiliary fixing structure 321 may be a member (e.g., a similar angle structure) independent from the testing module body 32. Of course, the test module body 32 is not limited to be locked to the second fixing member 112 by screws, and any method that can detachably assemble the test module body 32 to the second fixing member 112 is within the scope of the present embodiment, for example, the test module body 32 and the second fixing member 112 may have engaging structures that can engage with each other, and the test module body 32 may be fixed to the second fixing member 112 by the engaging structures.

Referring to fig. 3 again, in practical applications, the electrical connection sockets 2 may be divided into a plurality of electrical connection socket groups, each electrical connection socket group includes at least one electrical connection socket 2, and each test module 30 is correspondingly connected to all electrical connection sockets 2 of one electrical connection socket group. For example, in fig. 3 of the present embodiment, 72 electrical connection sockets 2 are disposed on the circuit board 10, which can be divided into 6 electrical connection socket groups, each electrical connection socket group includes 12 electrical connection sockets 2, and 12 electrical connection sockets 2 in each electrical connection socket group are located in the same group accommodating hole 1115, and 12 electrical connection sockets 2 in each electrical connection socket group are connected to the same test module 30; as shown in fig. 5, the circuit board 10 is provided with 6 test modules 30. Of course, the number of the electrical connection sockets 2 disposed on the circuit board 10 and the number of the electrical connection socket groups correspondingly partitioned can be changed according to the requirement.

As shown in fig. 6, it is particularly described that, through the design of the pressing structures 1112 and the fixing bodies 1114, each electrical connector 2 is directly fixed on the circuit board 10 in a pressing manner, and each set of electrical connector group is correspondingly pressed by one pressing structure 1112, so that, when any electrical connector 2 fails, a related person only needs to remove a screw between the pressing structure 1112 and the fixing body 1114 corresponding to the electrical connector 2, and then can directly remove and replace the electrical connector 2. That is, the design of the pressing structure 1112 and the fixing body 1114 can allow the related maintenance personnel or machine to easily and quickly maintain, replace and install the specific electrical connector 2.

When the test modules 30 are powered, a predetermined test procedure can be performed on the chips C on the electrical connectors 2, for example, the chips C can be various memories (for example, NAND FlaSh, etc.), and the test modules 30 can perform at least one of a read test, a write test and an electrical test on the memories. In an embodiment where each test module 30 is used to test memory, the test module body 32 of each test module 30 may include a Pattern Generator (PG), a Parametric Measurement Unit (PMU), a Device Power supply module (DPS), and a Driver circuit (Driver).

By the design of connecting the electrical connectors 2 disposed on the circuit board 10 to different test modules 30, the test modules 30 and the chips C connected to the electrical connectors 2 can transmit signals faster and less easily. More specifically, if the circuit board 10 provided with 72 electrical connection sockets 2 is connected to only one signal input source, when the signal emitted from the signal input source is transmitted from one side of the circuit board 10 to the other side of the circuit board 10, the signal is attenuated obviously, which may result in inaccurate chip test results.

In practical applications, all the electrical connectors 2 in each electrical connector group may be connected in parallel, and all the electrical connectors 2 connected in parallel in the same electrical connector group are connected to the same test module 30; in other words, all the electrical sockets 2 to which the respective test modules 30 are connected in parallel. In addition, any electrical connector 2 in each electrical connector group is not connected to any electrical connector 2 in other electrical connector groups. For example, suppose that four electrical connectors 2 are disposed on the circuit board 10: z1, Z2, Q1, Q2, four electrical sockets 2 are divided into two groups of electrical sockets, the first group includes Z1, Z2, the second group includes Q1, Q2, then Z1 and Z2 are connected in parallel, Q1 and Q2 are connected in parallel, Z1 is not connected with Q1 (whether in parallel or in series), Z1 is not connected with Q2 (whether in parallel or in series), Z2 is not connected with Q1 (whether in parallel or in series), and Z2 is not connected with Q2 (whether in parallel or in series).

Through the design that the electrical connection seats 2 of different electrical connection seat groups are not mutually connected, when the chip testing device 1 fails, related maintenance personnel can quickly find out the damaged electrical connection seat 2 by testing each electrical connection seat group one by one, and the related maintenance personnel can only replace the damaged electrical connection seat 2, the components of the electrical connection seat 2, the electrical connection seat 2 in the same group or the testing module 30, and the related personnel do not need to replace all the electrical connection seats 2 of the whole circuit board 10 or all the testing modules 30.

As shown in fig. 5, in practical applications, the chip testing apparatus 1 may further include a housing 31, the housing 31 is fixedly disposed on the second fixing member 112, and the housing 31 correspondingly covers the plurality of testing modules 30 to protect the plurality of testing modules 30. In a specific implementation, the housing 31 may also be provided with a related heat dissipation device, such as a fan, a heat dissipation fin, etc., according to requirements. In fig. 5 of the present embodiment, the chip testing apparatus 1 includes only a single housing 31, and the housing 31 correspondingly covers a plurality of testing modules 30, but the number of the housings 31 of the chip testing apparatus 1 is not limited to a single one, and in different applications, the chip testing apparatus 1 may also include a plurality of housings 31, and each housing 31 may be covered with a single testing module 30 or two or three testing modules 30.

As shown in fig. 4 to 6, the power supply member 4 is connected to the circuit board 10, and the power supply member 4 may be connected to a plurality of test modules 30 through the circuit board 10. The power supply member 4 may be, for example, a board-to-board connector, and may be, for example, but not limited to, a Pogo pin or a reed structure. In fig. 4 of the present embodiment, the power supply member 4 includes a plurality of connection terminals, and the power supply member 4 is disposed on the first side surface 101 of the circuit board 10 and exposed to the first fixing member 111 as an example, but the form and number of the power supply member 4, the position of the power supply member 4 disposed on the circuit board, and the like are not limited to those shown in the drawings.

The power supply member 4 is configured to be connected to an external power supply device, and the external power supply device can supply power to each test module 30 through the power supply member 4, the plurality of first contact structures 1021 (as shown in fig. 9) and the plurality of second contact structures 33 (as shown in fig. 5). That is, in the chip testing apparatus 1, when the external power supply device is not connected to the external power supply device through the power supply means 4, the respective test modules 30 basically perform the predetermined test program on the plurality of chips C connected thereto without electric power. Of course, in different embodiments, the chip testing apparatus 1 may also be provided with at least one battery, the battery is connected to the plurality of testing modules 30, and the battery can supply power to the plurality of testing modules 30.

In another embodiment, the power supply means 4 may comprise a receiving antenna, and the power supply means 4 may receive power wirelessly to provide power to each test module 30. In the embodiment where the power supply means 4 is a receiving antenna, the chip testing device 1 may include a rechargeable battery module, and the power supply means 4 is connected to the rechargeable battery module, and the power supply means 4 can receive power wirelessly to charge the rechargeable battery module; in a specific implementation, the power required by each test module 30 to test the chip C carried by the test module may be supplied from the rechargeable battery module and the external power supply device through the receiving antenna (the power supply component 4). In the embodiment where the power supply member 4 is a receiving antenna, the power supply member 4 may be disposed not exposed from the chip testing apparatus 1, but embedded in the circuit board 10 or hidden in the chip testing apparatus 1. The number of the power feeding members 4 included in each chip test apparatus 1 may be changed according to the demand, and is not limited to a single one, and may be two or more.

Please refer to fig. 10, which is a block diagram of a chip testing apparatus according to the disclosure. The power supply means 4 included in the chip testing device 1 may be connected to a plurality of test modules 30, and each test module 30 is connected to a plurality of electrical sockets 2. The chip testing device 1 may further comprise a plurality of first data transmission terminals 8. Each first data transmission terminal 8 may be connected to one test module 30. The plurality of first data transmission terminals 8 are used to connect with a plurality of second data transmission terminals E32 (shown in fig. 18) in a receiving chamber E311 (shown in fig. 17 and described in detail later) of the environmental control device E3, and the chip testing apparatus 1, the environmental control device E3 and the central control device E1 (shown in fig. 1) can transmit data to each other. In practical applications, the first data transmission terminals 8 and the second data transmission terminals E32 may be Pogo pins or reeds, but not limited thereto. The number of the first data transmission terminals 8 and the second data transmission terminals E32 and the arrangement positions thereof may be changed according to the needs, and are not limited herein.

In different embodiments, the chip testing apparatus 1 may also include at least one first data transmission antenna (not shown), and the accommodating chamber E311 may be correspondingly provided with at least one second data transmission antenna (not shown). The first data transmission antenna can interact with the second data transmission antenna to transmit information to each other in a wireless manner. In practical applications, the position of the first data transmission antenna is not limited to the accommodation chamber E311, and the first data transmission antenna may be disposed at any position of the environment control device E3 as long as the first data transmission antenna can transmit information with the second data transmission antenna disposed in the accommodation chamber E311.

Referring to fig. 11 to 14, fig. 11 is a schematic view of an electrical connection socket of a chip testing device disclosed in the present invention, fig. 12 is a schematic cross-sectional exploded view of the electrical connection socket of the chip testing device disclosed in the present invention, fig. 13 is a schematic cross-sectional view of the electrical connection socket of the chip testing device disclosed in the present invention without a chip, and fig. 14 is a schematic cross-sectional view of the electrical connection socket of the chip testing device disclosed in the present invention with a chip.

Each electrical connector socket 2 comprises: a plurality of probe assemblies 20, an electrical connection base body 21, a lifting structure 22, a supporting structure 23 and a plurality of elastic assemblies 24. Each probe assembly 20 includes a needle 201 and a spring 202. One end of the pin 201 is used to connect with the electrical connection C1 (shown in fig. 14) of the chip C. The spring 202 is sleeved on the needle body 201, and when one end of the needle body 201 is pressed, the spring 202 is pressed to generate an elastic restoring force correspondingly, so that when the needle body 201 is not pressed any more, the needle body 201 is restored to an uncompressed position under the action of the elastic restoring force.

The electrical connector body 21 has a top wall 211, a ring-shaped sidewall 212 and a top 213. The top wall 211 has an opening 21A, one side of the annular side wall 212 is connected to the periphery of the top wall 211, the other side of the annular side wall 212 is fixedly disposed on the circuit board 10, and the top wall 211, the annular side wall 212 and the circuit board 10 together form a receiving slot 21B. Opposite sides of the top wall 211 define an outer side 2111 and an inner side 2112 (shown in fig. 13). In practical applications, the top wall 211 and the annular side wall 212 may be integrally formed.

The annular sidewall 212 further protrudes outward to form a top 213. As shown in fig. 6 and 7, when the pressing structure 1112 is fixed to the fixing body 1114, the pressing structure 1112 will correspondingly abut against the abutting portion 213 of each electrical connector 2. That is, each abutting portion 213 is disposed to facilitate the abutting of the abutting structure 1112, and the shape of the abutting portion 213 may be designed to correspond to the abutting structure 1112 and the through hole 1113.

The lifting structure 22 includes a base 221 and a supporting portion 222. The base 221 is completely disposed in the receiving groove 21B, the base 221 extends toward one side to form a bearing portion 222, and a portion of the bearing portion 222 can pass through the opening 21A. The carrying portion 222 extends to a side away from the base portion 221 to form four limiting portions 223, the four limiting portions 223 may be located at four corners of the carrying portion 222, and the four limiting portions 223 and the carrying portion 222 together form a chip accommodating groove 22B, the chip accommodating groove 22B is used for providing a chip C, and the four limiting portions 223 are used for being mutually clamped with the chip C. The lifting structure 22 further has a plurality of connection holes 22A (shown in fig. 12), and each connection hole 22A is disposed through the base portion 221 and the bearing portion 222.

A portion of the plurality of probe assemblies 20 is fixedly disposed in the supporting structure 23, and the plurality of probe assemblies 20 are fixedly disposed at one end of the supporting structure 23 for connecting with the electrical contact structure 1011 (shown in fig. 8) of the circuit board 10; the other ends of the probe assemblies 20 are located in the connecting holes 22A, and one end of the probe assembly 20 located in the connecting holes 22A is used to connect with the electrical connection portion C1 of the chip C.

In practical applications, the supporting structure 23 may include a base structure 231 and an auxiliary structure 232. The base structure 231 is disposed in the receiving cavity 21B, and the base structure 231 and the electrical connector body 21 are fixed to each other (for example, fixed to the electrical connector body 21 by matching with a plurality of screws). The base structure 231 has a plurality of through holes 2311, and one end of the plurality of probe assemblies 20 is fixedly disposed in the plurality of through holes 2311 of the base structure 231. The auxiliary structure 232 is disposed in the receiving groove 21B, the auxiliary structure 232 is located between the base structure 231 and the top wall 211, and the auxiliary structure 232 and the base structure 231 are fixed to each other (for example, fastened to each other by screws). The auxiliary structure 232 has a plurality of supporting holes 2321 disposed at intervals, the supporting holes 2321 communicate with the through holes 2311 of the base structure 231, the supporting holes 2321 are disposed corresponding to the connecting holes 22A, the supporting holes 2321 and the through holes 2311 together form a plurality of probe channels, and the probe assemblies 20 are disposed in the probe channels.

As shown in fig. 8 and 12, it should be noted that the base structure 231 may include a plurality of positioning holes 2312, and each positioning hole 2312 is used for passing through the positioning element 25. In practical applications, the positioning holes 2312 may be disposed through the base structure 231, but not limited thereto.

As shown in fig. 13, the supporting structure 23 is disposed in the accommodating groove 21B, and the elastic component 24 is disposed between the supporting structure 23 and the lifting structure 22. The elastic assembly 24 enables the base 221 of the lifting structure 22 to abut against the inner side 2112 of the top wall 211, and a gap S is correspondingly formed between the base 221 and the supporting structure 23.

In practical applications, when the electrical connector 2 is fixed on the circuit board 10 and the limiting portion 223 of the electrical connector 2 is not pressed by an external force, the four elastic elements 24 located between the lifting structure 22 and the supporting structure 23 may be slightly compressed, and the elastic restoring force generated by the compression of the elastic elements 24 will make the lifting structure 22 firmly abut against the inner side 2112 of the top wall 211.

As shown in fig. 14, when the chip C is fixedly disposed in the chip accommodating slot 22B and the lifting structure 22 is not pressed, the electrical connection portions C1 of the chip C are correspondingly accommodated in the connection holes 22A, and the probe assemblies 20 are not connected with the electrical connection portions C1 (e.g., do not contact each other). When the lifting structure 22 is pressed, at least a portion of the lifting structure 22 will be retracted into the electrical connector body 21, that is, the lifting structure 22 will move toward the circuit board 10 relative to the supporting structure 23, and the probe assemblies 20 will be connected to the electrical connection portions C1 (shown in fig. 14) of the chip C.

Referring to fig. 7 again, in the embodiment shown in fig. 7, the number of the through holes 1113 of the pressing structure 1112 is corresponding to the number of the electrical connection sockets 2 located in the group of the accommodating holes 1115, and when the pressing structure 1112 is located in the group of the accommodating holes 1115, a portion of each electrical connection socket 2 correspondingly penetrates through the through hole 1113 of the adjacent pressing structure 1112. Referring to fig. 15, in various embodiments, the number of the through holes 1113 of the pressing structure 1112 may not completely correspond to the number of the electrical connectors 2. For example, the pressing structure 1112 may have only three through holes 1113, and when the pressing structure 1112 presses the electrical connectors 2 disposed in the group receiving hole 1115, each through hole 1113 penetrates a portion of the electrical connectors 2. In other words, the number or shape of the through holes 1113 of the pressing structure 1112 may vary according to the requirement, and is not limited to the number and shape shown in fig. 7 or fig. 15.

Referring to fig. 15 and 16, when the pressing structure 1112 is the same as the pressing structure 1112 shown in fig. 15, the shape of each electrical connector 2 can be as shown in fig. 16. The electrical connector socket 2 shown in fig. 16 is largely different from the electrical connector socket 2 shown in fig. 11 in that: the top 213 of each electrical connector 2 has a ring-shaped top 2131, and the ring-shaped sidewall 212 is correspondingly located in the area surrounded by the ring-shaped top 2131. When the pressing structure 1112 presses the plurality of electrical connectors 2 in the group receiving hole 1115, the pressing structure 1112 will press a portion of the annular pressing surface 2131 of each electrical connector 2.

Referring to fig. 10, fig. 17 and fig. 18 together, fig. 17 is a schematic diagram of an environment control apparatus of a chip testing system disclosed in the present invention, and fig. 18 is a block schematic diagram of the environment control apparatus and a central control device of the chip testing system disclosed in the present invention. A plurality of environment control devices E3 are connected to the central control unit E1, and the central control unit E1 can control any one of the environment control devices E3 to operate independently. Each of the environment control devices E3 is configured to perform a predetermined test procedure on the plurality of chips C disposed on the chip testing apparatus 1 in an environment with a predetermined temperature (e.g., a predetermined high temperature or a predetermined low temperature).

Each environmental control equipment E3 includes an equipment body E31. The apparatus body E31 includes a plurality of accommodation chambers E311. The containing chamber E311 is mainly used for containing the chip testing apparatus 1, and the containing chambers E311 included in the environmental control equipment E3 may be connected or not connected, which is not limited herein.

It should be noted that in the embodiment where the plurality of chambers E311 included in the environmental control apparatus E3 are independent from each other, but not connected to each other, each chamber E311 may be provided with a movable door, and the environmental control apparatus E3 may be connected to an air extractor. When the chip testing device 1 is disposed in the accommodating chamber E311, the central control device E1 can control the corresponding movable door to operate, so that the accommodating chamber E311 becomes a closed space, and then the central control device E1 can control the air-extracting device to operate, so that the accommodating chamber E311 is in a state similar to vacuum, and thus, the temperature in the accommodating chamber E311 is not easily affected by the external environment.

In an embodiment where the power supply member 4 of the chip testing apparatus 1 includes a plurality of connection terminals, a plurality of chamber terminals E33 may be correspondingly disposed in each chamber E311, and the plurality of chamber terminals E33 are used to connect with the plurality of connection terminals of the chip testing apparatus 1. The position of the housing terminal E33 may be designed according to the position of the chip testing apparatus 1 in the housing E311 and the positions of the plurality of connection terminals of the power feeding member 4, and is not limited thereto. In the embodiment where the power supply member 4 of the chip testing apparatus 1 is a receiving antenna, a transmitting antenna for wireless charging may be correspondingly disposed in each of the accommodating chambers E311, the transmitting antenna is connected to an external power supply device, and when the chip testing apparatus 1 is disposed at a predetermined position in the accommodating chamber E311, the transmitting antenna in the accommodating chamber E311 can be coupled to the receiving antenna (the power supply member 4) of the chip testing apparatus 1, and the external power supply device can provide power to each of the testing modules 30.

Each temperature adjustment device E34 is connected to the central control device E1, and each temperature adjustment device E34 can be controlled by the central control device E1 to make the ambient temperature of the chips C on the plurality of electrical connection sockets 2 of the chip testing device 1 in the corresponding accommodation chamber E311 reach a predetermined temperature.

In one practical example, the plurality of temperature adjustment devices E34 can be divided into a plurality of heating devices E34A and a plurality of cooling devices E34B. A plurality of heating devices E34A provided in the apparatus main body E31, and a plurality of refrigerating devices E34B provided in the apparatus main body E31; the temperature in each of the accommodating compartments E311 can be changed by one of the heating devices E34A or one of the cooling devices E34B to reach a predetermined low temperature or a predetermined high temperature.

Each of the heating devices E34A may include a high temperature contact structure E34a1, and the high temperature contact structure E34a1 is configured to contact one side of the chips C disposed on the chip testing apparatus 1. Each heating device E34A is connected to the central control device E1, and the central control device E1 can control each heating device E34A to operate independently, so that the temperature of the high temperature contact structure E34a1 of each heating device E34A is raised to a predetermined high temperature. The material of the high-temperature contact structure E34a1 may be determined according to a predetermined high-temperature, and a side of the high-temperature contact structure E34a1 contacting the plurality of chips C may be flat.

In a specific application, each high temperature contact structure E34a1 may include various electrothermal heaters (e.g., heating coils), or each high temperature contact structure E34a1 may include a plurality of flow channels, each flow channel providing a high temperature fluid to pass through. Of course, an electric heater or a related heater having a plurality of flow paths may be provided on one side of the high temperature contact structure E34a 1.

Each of the cooling devices E34B may include a low temperature contact structure E34B1, the low temperature contact structure E34B1 for contacting one side of the plurality of chips C disposed on the chip testing apparatus 1. Each of the refrigerators E34B is connected to the central control unit E1, and the central control unit E1 can control each of the refrigerators E34B to operate independently to lower the temperature of the low temperature contact structure E34B1 of each of the refrigerators E34B to a predetermined low temperature. The material of the low temperature contact structure E34B1 may be determined according to a predetermined low temperature, and a side of the low temperature contact structure E34B1 contacting the plurality of chips C may be flat. In a specific application, each low temperature contact structure E34B1 may include a plurality of flow passages, each flow passage providing for the passage of the cryogenic fluid, or related components having a plurality of flow passages may be disposed on one side of the low temperature contact structure E34B 1.

In the above embodiment, each heating device E34A includes a high temperature contact structure E34a1, each cooling device E34B includes a low temperature contact structure E34B1, and each of the heating device E34A and the cooling device E34B contacts one side of the chips C through the high temperature contact structure E34a1 and the low temperature contact structure E34B1, respectively, to directly perform heat transfer or heat removal on each chip C, so that the temperatures of the chips C reach a predetermined temperature. However, in different applications, each heating device E34A and each cooling device E34B may also be used to make the ambient temperature of the plurality of chips C on the chip testing device 1 reach a predetermined temperature in a non-contact manner, for example, each heating device E34A or each cooling device E34B may directly raise or lower the temperature in the corresponding accommodating chamber E311.

In the above description, the heating device E34A or the cooling device E34B is provided in each of the accommodating chambers E311 as an example, but the temperature adjusting device E34 provided in each of the accommodating chambers E311 is not limited to have only a single heating function or only a single cooling function. In various embodiments, each temperature adjustment device E34 may include both a heater E341 and a refrigerator E342, and each temperature adjustment device E34 may further include a contact structure E343 according to requirements. The heater E341 and the refrigerator E342 can be controlled by the central control device E1 so that the temperature of the contact structure E343 reaches a predetermined high temperature or a predetermined low temperature. The contact structure E343 is used to contact the plurality of chips C disposed on the chip testing apparatus 1, thereby bringing the temperature of the plurality of chips C to a predetermined temperature in a direct contact manner. Of course, in different applications, each temperature adjustment device E34 may not have the contact structure E343, and each temperature adjustment device E34 may pass through the heater E341 or the refrigerator E342 to make the corresponding accommodating chamber E311 reach the predetermined high temperature or the predetermined low temperature.

Please refer to fig. 13, 18 to 23, fig. 19 is an assembly diagram of the temperature adjustment device and the cover of the chip testing system, fig. 20 and 21 are exploded diagrams of the temperature adjustment device and the cover of the chip testing system, fig. 22 is a cross-sectional diagram of the temperature adjustment device and the cover of the chip testing system, which are disposed on the chip testing device, and fig. 23 is a cross-sectional partially enlarged diagram of the temperature adjustment device and the cover of the chip testing system, which are disposed on the chip testing device. The thermostat E34 of the respective climate control device E3 may be interconnected with a housing E35. A groove E351 is formed in one side of the cover body E35 in a concave mode, the cover body E35 is provided with an accommodating opening E352, and the accommodating opening E352 is communicated with the groove E351. The cover E35 also has two suction holes E353. Each environmental control apparatus E3 may include at least one air extractor E37, and two air extraction holes E353 for connecting with the air extractor E37.

The temperature adjusting device E34 may include the aforementioned high temperature contact structure E34a1, low temperature contact structure E34B1 and contact structure E343, and one side of the high temperature contact structure E34a1, low temperature contact structure E34B1 and contact structure E343 may be flat, and the high temperature contact structure E34a1, low temperature contact structure E34B1 and contact structure E343 may include at least one flow channel E344, and the high temperature contact structure E34a1, low temperature contact structure E34B1 and contact structure E343 have a fluid inlet E345 and a fluid outlet E346, respectively, whereby the high temperature fluid or the low temperature fluid may enter the flow channel E344 through the fluid inlet E345 and then flow out through the fluid outlet E346, whereby the high temperature fluid or the low temperature fluid may flow uninterruptedly in the flow channel E344 to make the temperature of the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343 reach a predetermined temperature.

In practical applications, the cover E35 may further be fixedly disposed with a cover E36, an accommodating space SP1 may be correspondingly formed between the cover E36 and the temperature adjustment device E34, and the accommodating space SP1 may be filled with any component capable of blocking heat energy transfer.

As shown in fig. 22 and 23, fig. 22 shows a schematic view of the electrical connector 2 of the chip testing device 1 and the chip C disposed thereon contacting with the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343 of the temperature adjusting device E34, and fig. 23 is a partially enlarged schematic view of fig. 22. When the cover E35 abuts against one side of the first fixing member 111, the cover E35, the high temperature contact structure E34a1, the low temperature contact structure E34B1, the contact structure E343 and the circuit board 10 together form a closed space SP2, and the plurality of electrical connectors 2 are correspondingly located in the closed space SP 2; meanwhile, a plurality of connection terminals of the power supply member 4 may be correspondingly connected to a plurality of receiving chamber terminals E33.

As shown in fig. 14 and 23, in the process that the central control device E1 controls the operation of the air-extracting apparatus to extract the air in the enclosed space SP2 through the air extracting hole E353 of the cover E35 to make the enclosed space SP2 be in a state close to vacuum or vacuum, the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343 will press against the lifting structure 22 of each electrical connector 2, and each lifting structure 22 will move relative to the electrical connector body 21 toward the circuit board 10, and the plurality of probe assemblies 20 will be correspondingly connected to the plurality of electrical connectors C1 of the chip C, and the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343 will be correspondingly pressed against one side of the plurality of chips C; in other words, during the process of pumping out the gas in the enclosed space SP2, the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343 will press against the elevating structure 22 of each electrical socket 2, and the elevating structure 22 of the electrical socket 2 will be converted from the state shown in fig. 14 to the state shown in fig. 23.

In practical applications, the central control device E1 controls the air-extracting device, and the time point for extracting the air in the enclosed space SP2 can be designed according to the requirement. For example, the central control device E1 may control the operation of the air-extracting device to extract the air in the enclosed space SP2 when the plurality of connection terminals included in the power supply member 4 are connected to the accommodating chamber terminal E33 (as shown in fig. 18); alternatively, the central control device E1 may determine whether the chip testing device 1 is already disposed at a predetermined position in the accommodating chamber E311 by at least one sensor (e.g., an optical sensor or a mechanical pressing sensor) disposed in the accommodating chamber E311 (as shown in fig. 17), and the central control device E1 controls the air pumping device to operate to pump out the air in the enclosed space SP2 when the chip testing device 1 is determined to be located at the predetermined position in the accommodating chamber E311 by the sensor.

As shown in fig. 18 and 23, when the gas extracting device E37 extracts the gas in the enclosed space SP2 to the outside, and the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343 are correspondingly abutted against one side of the chips C, and the probe assemblies 20 of each electrical connection socket 2 are connected to the electrical connection portions C1 of the chip C disposed thereon, the central control device E1 can control the temperature adjusting device E34 to actuate so that the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343 reach a predetermined temperature, and the central control device E1 can control the test module 30 connected to each electrical connection socket 2 to perform a predetermined test procedure on the chip C when the temperatures of the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343 reach the predetermined temperature.

Through the cooperation of the cover body E35 and the air extractor E37, the acting force required by the high temperature contact structure E34a1, the low temperature contact structure E34B1, and the contact structure E343 to press the lifting structures 22 of the electrical connectors 2 at the same time can be greatly reduced, that is, the acting force required by the lifting device E38 (detailed later) to make the chips C carried by the chip testing device 1 to be simultaneously pressed against the high temperature contact structure E34a1, the low temperature contact structure E34B1, and the contact structure E343 can be reduced.

In particular, according to the above description of the chip testing apparatus 1, since only the plurality of circuit board locking holes 103 are disposed through the circuit board 10 of the chip testing apparatus 1, when the cover E35 abuts against the first fixing member 111, the sealing performance of the enclosed space SP2 is easily controlled, and the air extractor E37 relatively easily extracts the air in the enclosed space SP2 to a state of approximately vacuum in the enclosed space SP 2. That is, in the chip testing apparatus 1 of the present invention, the number of through holes in the circuit board 10 is greatly reduced by the design of the first fixing member 111, the second fixing member 112, and the like, so that the closed space SP2 is relatively easily brought into a vacuum state when the air extractor E37 extracts air from the closed space SP 2.

Referring to fig. 1 and 2 again, the transfer equipment E4 is disposed between the environmental control equipments E3, and the transfer equipment E4 is used for carrying the chip testing apparatus 1. The transfer apparatus E4 may comprise a robot and a holding component for holding the chip testing device 1. The central control device E1 is connected to the transfer facility E4, and the central control device E1 can control the transfer facility E4 to set the chip testing apparatus 1 carrying a plurality of chips C in any of the accommodation chambers E311 (see fig. 17) of any of the environment control facilities E3. In contrast, the transfer device E4 may be controlled by the central control device E1 to move the chip testing apparatus 1 disposed in any of the accommodating chambers E311 out of the accommodating chamber E311.

The sorting apparatus E5 is connected to the central control device E1, and the sorting apparatus E5 can be controlled by the central control device E1 to detach the chips C from the electrical connectors 2 of the chip testing apparatus 1, and the sorting apparatus E5 can place the chips C on a tray of a good area a1 or a tray of a defective area a2 according to the test results of the chips C after passing a predetermined test procedure. The sorting device E5 may for example comprise a robot arm. In an embodiment where the sorting apparatus E5 and the chip mounting apparatus E2 are disposed at adjacent positions, the chip mounting apparatus E2 and the sorting apparatus E5 may share the same robot arm. In practical applications, the good area a1 may be divided into a plurality of areas according to requirements, and the sorting apparatus E5 may arrange the chips C in different areas of the good area a1 according to the test results of the chips C after passing through the predetermined test procedures, for example, the chips C may be distinguished according to the operation performance of the chips C.

Fig. 24 is a schematic flow chart of a chip testing method according to a first embodiment of the present invention. The chip test system E may perform a predetermined test procedure on the plurality of chips C by using a chip test method including:

a chip mounting step S1: transferring a plurality of chips (C) from a carrying tray to a plurality of electric connection seats (2) of a chip testing device (1) by a chip mounting device (E2);

a shift to step S2: transferring a chip testing device (1) carrying a plurality of chips (C) to one of the accommodating chambers (E311) of one of the environment control devices (E3);

a temperature adjustment step S3: controlling a temperature adjusting device (E34) in the accommodating chamber (E311) to operate so that the plurality of chips (C) are in an environment with a preset temperature;

a test step S4: supplying power to a chip testing device (1) arranged in the accommodating chamber (E311) so that each testing module (30) performs a preset testing program on a plurality of chips (C) connected with the testing module;

a shift-out step S6: removing the chip testing device (1) from the accommodating chamber (E311), and transferring the chip testing device (1) to a sorting device (E5);

a classification step S7: a sorting device (E5) is used for placing a plurality of chips (C) into a good product area (A1) or a defective product area (A2) respectively according to the test results of the chips (C) after the chips (C) complete the predetermined test procedures.

In the embodiment where the power supply member 4 of the chip testing apparatus 1 includes a plurality of connection terminals, before the testing step S4, a connection step may be further included: the plurality of connection terminals of the power feeding member 4 of the chip testing apparatus 1 are connected to the plurality of housing chamber terminals E33 provided in the housing chamber E311. In an embodiment, the connection step may be located between the moving-in step S2 and the temperature adjustment step S3, or the connection step may be located between the temperature adjustment step S3 and the test step S4.

Fig. 25 is a schematic flow chart of a chip testing method according to a second embodiment of the present invention. The biggest difference between this embodiment and the embodiment shown in fig. 24 is that: an air-extracting step S21 may be further included between the moving step S2 and the temperature adjusting step S3. In the moving-in step S2, the enclosure E35 disposed in the accommodating chamber E311 and the circuit board 10 of the chip testing apparatus 1 are connected to each other, so that the enclosure E35 and the circuit board 10 form a closed space SP2 (as shown in fig. 22), and then, in the air exhausting step S21, the air exhausting device connected to the closed space SP2 is operated to exhaust the air in the closed space SP2 outward.

As shown in fig. 22 and described in the corresponding embodiment, when the cover body E35 and the circuit board 10 form the enclosed space SP2, each electrical connector 2 is located in the enclosed space SP 2. After the air-extracting step S21 is performed, each electrical connector 2 will be located in a near vacuum environment, so that, when the temperature adjusting step S3 is performed subsequently, the temperature of the enclosed space SP2 will not be affected by the external environment, and the ambient temperature of the electrical connector 2 and the chip C carried thereby will be easily maintained at the predetermined temperature.

Fig. 26 is a schematic flow chart of a chip testing method according to a third embodiment of the present invention. The present embodiment is different from the previous embodiments in the following point: between the test step S4 and the shift-out step S6, the following steps may be included:

a separation step S5: after the chip testing device (1) completes a predetermined test program for all chips (C) connected thereto, the power supply member (4) of the chip testing device (1) is controlled to be separated from the plurality of housing chamber terminals (E33) in the housing chamber (E311).

As shown in fig. 3, 17 and 18, in practical applications, the environmental control apparatus E3 may further include a plurality of lifting devices E38, and each of the accommodating chambers E311 is provided with one lifting device E38. Each of the elevating devices E38 is connected to an environmental condition control device of the central control device E1. Each of the elevating devices E38 is controlled by the central control device E1 to elevate the chip testing apparatus 1 disposed in the housing chamber E311, so that the plurality of connection terminals of the power supply member 4 of the chip testing apparatus 1 are connected to or separated from the housing chamber terminal E33.

In practical applications, when each chip testing apparatus 1 is transferred into the accommodating chamber E311 by the transfer apparatus E4, the power supply members 4 of the chip testing apparatus 1 may not be connected to the accommodating chamber terminals E33, and when the central control apparatus E1 determines that a chip testing apparatus 1 is disposed in any one of the accommodating chambers E311, the central control apparatus E1 may control the corresponding lifting apparatus E38 to move the chip testing apparatus 1 in the accommodating chamber E311, so that the connection terminals of the power supply members 4 are connected to the accommodating chamber terminals E33, whereby the external power supply apparatus can provide power to the test modules 30 through the power supply members 4.

In practical applications, how the central control device E1 determines whether the chip testing device 1 is disposed in any of the accommodating chambers E311 may be designed according to requirements, and is not limited herein. For example, a sensor (e.g., an optical sensor or any mechanical push switch) may be disposed in the housing E311, and when the chip testing device 1 enters the housing E311, the sensor correspondingly generates a relevant signal and transmits the relevant signal to the central control device E1, and the central control device E1 may determine whether the chip testing device 1 is disposed in the housing E311 according to the signal transmitted by the sensor. Of course, the sensor may be used to confirm whether the chip testing device 1 is disposed at a predetermined position in the accommodating chamber E311, and the sensor may transmit a corresponding signal to the central control device E1 according to the position of the chip testing device 1 in the accommodating chamber E311, the central control device E1 may determine whether the chip testing device 1 is disposed at the predetermined position in the accommodating chamber E311 according to the signal transmitted by the sensor, and if the central control device E1 determines that the chip testing device 1 is disposed at the predetermined position in the accommodating chamber E311, the central control device E1 may control the lifting device E38 to operate; on the contrary, if the central control device E1 determines that the chip testing device 1 is not located at the predetermined position in the accommodating chamber E311, the central control device E1 may control the related warning device to activate to warn the user, for example, the central control device E1 may control the related warning lamp to emit light of a specific color, control the related display screen to display error information, and the like.

In the embodiment where the power supply member 4 is a receiving antenna, when the chip testing apparatus 1 is disposed in the accommodating chamber E311, the corresponding transmitting antenna in the accommodating chamber E311 may be coupled to the receiving antenna, and the chip testing apparatus 1 may obtain power through the power supply member 4. Of course, in another embodiment, the receiving antenna may be coupled to the receiving antenna when the chip testing device 1 is disposed at a predetermined position in the accommodating chamber E311, which is not limited herein.

As shown in fig. 3 and 18, in the embodiment where each temperature adjustment device E34 has the aforementioned high temperature contact structure E34a1, low temperature contact structure E34B1, and contact structure E343, when the lifting device E38 is controlled to operate, the chip testing apparatus 1 and the chips C carried by the chip testing apparatus are driven by the lifting device E38 to move toward the high temperature contact structure E34a1, the low temperature contact structure E34B1, and the contact structure E343 or move away from the high temperature contact structure E34a1, the low temperature contact structure E34B1, and the contact structure E343.

In the embodiment where the temperature adjustment device E34 is connected with the cover body E35, when the lifting device E38 is controlled to move the chip testing apparatus 1 to a predetermined position in the directions of the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343, the cover body E35 is correspondingly covered on the circuit board 10 of the chip testing apparatus 1, and the cover body E35 forms a closed space SP2 together with the circuit board 10. Then, before the temperature adjustment step S3, the central control device E1 controls the air extraction device E37 to extract air from the enclosed space SP2 so that the enclosed space SP2 is in a state close to vacuum, and thus, after the temperature adjustment step S3, the temperature in the enclosed space SP2 is not easily affected by the external environment.

In practical applications, when the chip testing apparatus 1 is disposed in the accommodating chamber E311 and the lifting device E38 lifts the chip testing apparatus 1, the chips C may not contact with the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343, and when the air extraction device E37 starts to extract air, the chips C contact with the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343, but not limited thereto. In another embodiment, the plurality of chips C may also be in contact with the high temperature contact structure E34a1, the low temperature contact structure E34B1 and the contact structure E343 when the air extracting device E37 does not extract air.

In the testing step S4, the chip testing apparatus 1 is coupled or connected to the corresponding transmitting antenna or the receiving chamber terminal through the receiving antenna or the plurality of connecting terminals, so as to obtain power, and each testing module 30 can test the chip C connected thereto.

As shown in fig. 17 and 18, in practical applications, in order to firmly connect the plurality of connection terminals of the power supply member 4 of the chip testing apparatus 1 and the plurality of receiving chamber terminals E33, the environmental control device E3 may further include a plurality of position-limiting devices E39, and the plurality of position-limiting devices E39 are disposed in the plurality of receiving chambers E311. Each of the stopper devices E39 is connected to a central control device E1. Each of the position-limiting devices E39 can be controlled by the central control device E1 to limit the moving range of the chip testing device 1 in the accommodating chamber E311. The specific structure of the position-limiting device E39 can be designed according to the requirement, for example, the chip testing device 1 can be provided with a locking hole, and the position-limiting device E39 includes a corresponding hook structure, when the position-limiting device E39 is actuated, the hook structure can be correspondingly locked in the locking hole; alternatively, the stopper E39 may include a plurality of retractable pins, and the retractable pins may be inserted into the engaging holes of the chip testing apparatus 1.

In the above-mentioned embodiment, in which each of the accommodating chambers E311 of each of the environmental control apparatuses E3 has the high temperature contact structure E34a1, the low temperature contact structure E34B1, the contact structure E343, the lifting device E38 and the limiting device E39, in the moving step S2, the chip testing method may include the following steps:

a step of moving into the accommodating chamber: moving the chip testing device (1) into the accommodating chamber (E311);

a rising step: controlling a lifting device (E38) in the accommodating chamber (E311) to enable the chip testing device (1) to move towards the contact structures (E34A1, E34B1 and E343);

a locking step: controlling a limiting device (E39) in the accommodating chamber (E311) to enable the limiting device (E39) to limit the moving range of the chip testing device (1) in the accommodating chamber (E311).

In summary, the chip testing method of the present invention may be that a plurality of chips are mounted on the chip testing device 1; next, the chip testing apparatus 1 is moved into one of the accommodating chambers E311 of the environmental control device E3; then, the lifting device E38 is controlled to lift the chip testing device 1, so that one side of the chips C of the chip testing device 1 is adjacent to the high-temperature contact structure E34a1, the low-temperature contact structure E34B1 and the contact structure E343 of the temperature adjusting device E34, and the cover body E35 connected with the temperature adjusting device E34 is covered on the circuit board 10 of the chip testing device 1 to form a closed space SP 2; subsequently, the air extractor E37 is controlled to extract air from the enclosed space SP2, so that one side of the chips C on the chip testing apparatus 1 is attached to the high-temperature contact structure E34a1, the low-temperature contact structure E34B1 and the contact structure E343, and the temperature regulator E34 is controlled to operate to make the chips C reach a predetermined temperature; when the temperature adjusting device E34 is activated, power is supplied to the chip testing apparatus 1 so that the plurality of test modules 30 test the plurality of chips C.

Referring to fig. 27, which is a flowchart illustrating a fourth embodiment of the chip testing method according to the present disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed by the embodiment is different from the chip testing method in the following point: after moving to step S2 and before the separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeatedly performed twice, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, and the testing step S42, respectively.

In the temperature adjusting step S31 and the testing step S41 (i.e., the temperature adjusting step S3 and the testing step S4 are executed for the first time), the temperature adjusting device E34 corresponding to the accommodating chamber E311 is controlled to enable the chips C to be in an environment with a temperature above 115 ℃, and then each testing module 30 is controlled to perform at least one of a read test, a write test and an electrical test on the chips C. The temperature adjustment step S31 and the test step S41 are performed to Burn-In (Burn-In) the memory.

In the temperature adjusting step S32 and the testing step S42 (i.e., the temperature adjusting step S3 and the testing step S4 are executed for the second time), the temperature adjusting device E34 corresponding to the accommodating chamber E311 is controlled to enable the chips C to be in an environment with a temperature of 75 ℃ to 95 ℃, and then each testing module 30 is controlled to perform at least one of a read test, a write test and an electrical test on the chips C. The temperature adjustment step S32 and the test step S42 are performed to test the memory at a high temperature.

Specifically, in various embodiments, the test step S41 and the temperature adjustment step S32 may include a shift-out step and a shift-in step; the moving-out step is to move the chip testing device 1 out of the current chamber E311, and the moving-in step is to move the chip testing device 1 into another chamber E311. That is, the chip testing apparatus 1 can be sequentially located in two different chambers E311 (which can be located in the same environmental control equipment E3 or in different environmental control equipment E3) with a temperature above 115 ℃ and a temperature between 75 ℃ and 95 ℃ for testing.

Referring to fig. 28, which is a flowchart illustrating a fifth embodiment of the chip testing method according to the disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 28 in the following point: after moving to step S2 and before the separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeated three times, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, the testing step S42, the temperature adjusting step S33 and the testing step S43, respectively.

After the temperature adjusting step S32 and the testing step S42 are performed, the temperature adjusting step S33 and the testing step S43 (i.e., the temperature adjusting step S3 and the testing step S4 are performed for the third time) are performed by controlling the temperature adjusting device E34 corresponding to the accommodating chamber E311 to make the chips C in the environment with the temperature of-55 ℃ to-35 ℃, and then controlling each testing module 30 to perform at least one of the read test, the write test and the electrical test on the chips C. In other words, the chip testing method disclosed In this embodiment sequentially performs a Burn-In (Burn-In) test, a high temperature test, and a low temperature test on the plurality of chips C.

Referring to fig. 29, which is a flowchart illustrating a sixth embodiment of the chip testing method according to the present disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 27 in the following point: after moving to step S2 and before the separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeated four times, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, the testing step S42, the temperature adjusting step S33, the testing step S43, the temperature adjusting step S34, and the testing step S44, respectively.

After the temperature adjusting step S33 and the testing step S43 are performed, the temperature adjusting step S34 and the testing step S44 (i.e., the temperature adjusting step S3 and the testing step S4 are performed for the fourth time) are performed by controlling the temperature adjusting device E34 corresponding to the accommodating chamber E311 to make the chips C in the environment with the temperature of 20 ℃ to 30 ℃ (normal temperature), and then controlling each testing module 30 to perform at least one of the read test, the write test and the electrical test on the chips C. In other words, the chip testing method disclosed In this embodiment sequentially performs a Burn-In (Burn-In) test, a high temperature test, a low temperature test, and a normal temperature test on the plurality of chips C.

As described above, the chip testing method of the present embodiment can be performed by using the chip testing system E in which the temperature adjustment devices E34 of the environmental control apparatuses E3 have the refrigerators E342 and the heaters E341 at the same time in the foregoing description. After the chip testing apparatus 1 is moved into the accommodating chamber E311 of the environment control device E3, at least one of a read test, a write test, and an electrical test is sequentially performed In an environment at a temperature of 115 ℃ or higher, an environment at a temperature of 75 ℃ to 95 ℃, an environment at a temperature of-55 ℃ to-35 ℃, and an environment at a temperature of 20 ℃ to 30 ℃, that is, a Burn-In (Burn-In) test, a high temperature test, a low temperature test, and a normal temperature test are sequentially performed on the plurality of chips C. Of course, In practical applications, the chip testing apparatus 1 may perform the Burn-In (Burn-In) test, the high temperature test, the low temperature test and the normal temperature test on the plurality of chips C In the sequence, which may be arranged according to the requirement, and is not limited to the above sequence.

Referring to fig. 30, which is a flowchart illustrating a chip testing method according to a seventh embodiment of the present disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 27 in the following point: the following steps may be included between the shift-out step S6 and the sorting step S7:

a move-in step SX 1: transferring a chip testing apparatus (1) carrying a plurality of chips (C) to an accommodating chamber (E311) of another environment control device (E3);

a temperature adjustment step SX 2: controlling a temperature adjusting device (E34) in the accommodating chamber (E311) to operate so that the plurality of chips (C) are in an environment of-55 ℃ to-35 ℃;

a test step SX 3: power is supplied to a chip testing device (1) arranged in the accommodating chamber (E311) so that each testing module (30) performs a predetermined testing procedure on a plurality of chips (C) connected with the testing module.

In the chip testing method of the present embodiment, the chip testing apparatus 1 is first disposed in the accommodating chamber E311 of one of the environment control devices E3, and the plurality of chips C are sequentially subjected to at least one of a read test, a write test, and an electrical test in an environment with a temperature of 115 ℃ or higher and in an environment with a temperature of 75 ℃ to 95 ℃; then, the chip testing apparatus 1 is moved out of the containing chamber E311, and the chip testing apparatus 1 is moved into one of the containing chambers E311 of different environmental control devices E3 (or moved into another containing chamber E311 of the same environmental control device E3); subsequently, the temperature control device E34 of the accommodating chamber E311 operates to make the plurality of chips C carried by the chip testing apparatus 1 in an environment with a temperature of-55 ℃ to-35 ℃ for at least one of a read test, a write test and an electrical test.

The chip testing method of the present embodiment may be performed by using the chip testing system E in the foregoing description, and particularly, the chip testing system E in which only the heating device E34A or only the cooling device E34B is disposed in each accommodating chamber E311 of each environmental control apparatus E3.

In the chip testing method of the present embodiment, since the temperature of the single accommodating chamber E311 is not decreased from the temperature of more than 100 ℃ to the temperature of less than 0 ℃, the time required for the temperature around each chip C to reach the predetermined high temperature and the predetermined low temperature can be greatly shortened, and the energy consumed for the temperature adjusting devices E34 to reach the predetermined temperature in the accommodating chamber E311 can be greatly reduced.

As shown in fig. 31, which is a flowchart illustrating an eighth embodiment of the chip testing method disclosed in the present invention, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed by the embodiment is different from the chip testing method in the following point: after the temperature adjustment step SX2 and the test step SX3, a temperature adjustment step SX4 and a test step SX5 may be further included. In the temperature adjusting step SX4, the temperature adjusting device E34 in the accommodating chamber E311 is controlled to operate, so that the plurality of chips C are in an environment of 20 ℃ to 30 ℃. In the testing step SX5, power is supplied to the chip testing apparatus 1 disposed in the accommodating chamber E311, so that each testing module 30 performs a predetermined testing procedure on the plurality of chips C connected thereto. That is, in the temperature adjustment step SX2 and the test step SX3, the plurality of chips C are tested in a low temperature environment, and in the temperature adjustment step SX4 and the test step SX, the plurality of chips C are tested in a normal temperature environment.

It should be noted that, in different embodiments, after each test module 30 completes a predetermined test program for the chips C on the electrical connectors 2 connected thereto, the test module 30 may write the test result data and the corresponding test parameters of each chip C into each chip C, so that the test result data and the test parameter data are stored in each chip C. More specifically, the test result data may include, for example: the test conditions of the chip C in the high temperature test, the pre-burning test, the low temperature test and the normal temperature test may be respectively determined, or only whether the chip C passes the high temperature test, the pre-burning test, the low temperature test and the normal temperature test may be recorded. In a specific chip testing method, after each of the testing steps S41, S42, S43, S44 (as shown in fig. 29), the following steps may be respectively included: a test result writing step: and storing the test result data after each memory completes the preset test program and the corresponding test parameter data in each memory.

The test parameter data may for example comprise: an identification number (IDNumber) of the chip testing apparatus 1, an identification number of the test module 30, an identification number of the electrical connection socket 2, an identification number of the environmental control device E3 and an identification number of the housing chamber E311 thereof, a temperature value at the time of high-temperature test, a temperature value at the time of burn-in test, a temperature value at the time of low-temperature test, a temperature value at the time of normal-temperature test, and the like.

Through the above design that the test module 30 writes the test result data and the test parameter data of the chip C into the chip C, when any chip C is handed to a consumer, the consumer can read the data stored in the chip C through the related device to confirm the detection state during the production; and when the relevant production personnel receive any chip C returned by the consumer, the detection process of the chip C can be quickly traced by reading the test result data and the test parameter data stored in the chip C, so that the production personnel can be effectively helped to find out the possible defects in the detection process.

In different embodiments, the chip testing method may also include, after the classifying step S7 (as shown in fig. 29): a test result writing step: and storing the test result data after each memory completes the preset test program and the corresponding test parameter data in each memory. Specifically, when the memory carried by the chip testing apparatus 1 completes all tests (for example, burn-in test and high temperature test, or burn-in test, high temperature test, low temperature test, and normal temperature test) according to the requirements, the central control apparatus E1 may first control the sorting device E5 to sort each memory according to the test result of each memory. Then, the central control device E1 controls the related read/write device to perform the related read/write operation on the memories classified into the good area a1, so as to store the corresponding test result data and the corresponding test parameter data in each memory. That is, only the memory divided into good memory is stored with the test result data and the test parameter data.

The chip testing method may also include, before the classifying step S7 (shown in fig. 29): a test result writing step: and storing the memory passing through each preset test program, the corresponding test result data and the corresponding test parameter data in the corresponding memory. Specifically, when the memory carried by the chip testing device 1 is tested according to the requirements and passes all tests (such as a burn-in test and a high-temperature test, or a burn-in test, a high-temperature test, a low-temperature test, and a normal-temperature test), the chip testing device 1 writes the test result corresponding to the memory and the related test parameter data into the memory; on the contrary, if the memory fails at least one of the tests, the chip testing apparatus 1 will not write any test-related data corresponding to the memory into the memory. Thus, in the classifying step S7, the classifying device may rapidly determine whether the memory passes the test by determining whether any of the test-related data is written in the memory, and if the classifying device determines that the data is not written in the memory, the classifying device may directly classify the memory into the defective area.

In addition, it should be emphasized that in any of the above embodiments in which the power supply member includes a plurality of connection terminals, the connection terminals and the housing chamber terminals can be directly replaced by the receiving antenna and the transmitting antenna. Of course, since the receiving antenna and the transmitting antenna are wirelessly used for power transmission, the related process steps of contacting or separating the connecting terminal and the accommodating chamber terminal in some embodiments can be omitted when the connecting terminal and the accommodating chamber terminal are directly replaced by the receiving antenna and the transmitting antenna.

In summary, the chip testing system, the chip testing apparatus and the chip testing method applied to the chip testing system disclosed by the invention have the advantages of cost and better testing efficiency compared with the existing chip testing equipment. In addition, the chip testing system disclosed by the invention has the advantages that the plurality of chips are arranged on the chip testing device, then the chip testing device is moved to carry out related testing operation in different temperature environments, therefore, the chips are arranged on the same chip testing device in the testing process in different temperature environments, the chips cannot be repeatedly disassembled and assembled in the whole testing process, and the chips are not easy to be damaged unexpectedly. In contrast, in the conventional memory detection device, the memory is repeatedly detached and mounted on the electrical connection socket in different temperature environments, so that the memory is easily damaged unexpectedly after repeated detachment and mounting.

The disclosure is only a preferred embodiment of the invention and is not intended to limit the scope of the invention, so that all equivalent technical changes made by using the contents of the specification and the drawings are included in the scope of the invention.

Claims

1. A chip testing device, wherein the chip testing device is used for bearing a plurality of chips, and the chip testing device can be carried by a carrying device and transferred among a plurality of workstations, the chip testing device comprises:

the circuit board, its opposite both sides define a first side and a second side separately; the circuit board is provided with a plurality of positioning holes and a plurality of circuit board locking holes, each positioning hole does not penetrate through the circuit board, and each circuit board locking hole penetrates through the circuit board;

a fixing assembly, including a first fixing member and a second fixing member, wherein the first fixing member is disposed on the first side surface, the second fixing member is fixedly disposed on the second side surface, the first fixing member has a plurality of first locking holes, the second fixing member has a plurality of second locking holes, and the plurality of first locking holes, the plurality of circuit board locking holes and the plurality of second locking holes are correspondingly disposed; the circuit board is fixed between the first fixing component and the second fixing component;

the electric connection seats are provided with an electric connection seat body; one side of each electric connection seat body is used for bearing one chip, the other side of the electric connection seat body is provided with at least two positioning pieces, each positioning piece is mutually clamped with the plurality of positioning holes, and each electric connection seat is fixedly arranged on the first side surface of the circuit board; the first fixing member comprises a plurality of pressing structures which are correspondingly pressed against a part of the electric connecting seats, each electric connecting seat is pressed by the first fixing member and fixed on the first side surface of the electric connecting seat, the first fixing member comprises a plurality of through holes, and a part of each electric connecting seat is correspondingly exposed out of one of the through holes;

the control unit is arranged on the second side face of the circuit board and comprises a plurality of test modules, and each test module is connected with one part of the electric connecting seats; the second fixing piece is provided with a plurality of avoidance holes, and a part of the plurality of test modules penetrates through the plurality of avoidance holes;

at least one power supply component connected with the circuit board;

the chip testing device is connected with a power supply device through the power supply component so as to obtain the power required by the operation of each testing module; the power supply equipment is connected with at least one workstation;

when the chip testing device obtains power from the power supply equipment through the power supply component, each testing module can perform a preset testing program on the chips on the electric connection seats connected with the testing module.

2. The chip test apparatus according to claim 1, wherein each of the test modules comprises: the device comprises a graph generator, a component power supply module and a driving circuit; the chip is a memory, and the predetermined test program comprises: at least one of a read test, a write test, and an electrical test; the plurality of electric connection seats are partitioned into a plurality of electric connection seat groups, and each electric connection seat group comprises at least one electric connection seat; the plurality of test modules are connected with the plurality of electric connection seat groups, and each test module is connected with all the electric connection seats in the corresponding electric connection seat group; the plurality of test modules are connected with the plurality of electric connection seat groups, and each test module is connected with all the electric connection seats in the corresponding electric connection seat group.

3. The apparatus of claim 2, wherein each of the pressing structures is detachably fixed to the first fixing member, each of the first fixing members has a plurality of group receiving holes, and each of the group receiving holes is configured to receive a plurality of electrical connectors in the same electrical connector group.

4. The apparatus of claim 3, wherein the circuit board has a plurality of first contact structures formed on the second side, each of the test modules has at least one second contact structure, and the second contact structure of each of the test modules is detachably contactable with one of the first contact structures.

5. The chip testing apparatus according to claim 1, wherein the power supply member includes a plurality of connection terminals, the plurality of connection terminals being disposed on the first side surface of the circuit board, and the plurality of connection terminals being exposed to the first fixing member; the plurality of connecting terminals are used for being connected with the plurality of accommodating chamber terminals of one of the workstations; when the plurality of connecting terminals and the plurality of accommodating chamber terminals are connected with each other, the power supply equipment can supply power to the chip testing device.

6. The apparatus according to claim 1, wherein the power supply means is a receiving antenna for coupling with a transmitting antenna of the power supply device, and the apparatus can wirelessly receive the power transmitted by the power supply device through the receiving antenna.

7. The chip testing device as claimed in claim 1, further comprising at least one first data transmission terminal disposed on the circuit board and exposed from the first fixing member, the first data transmission terminal being configured to contact with at least one second data transmission terminal of one of the workstations for transmitting data therebetween.

8. The device for chip testing as claimed in claim 1, further comprising at least a first data transmission antenna for wirelessly transmitting data with at least a second data transmission antenna of one of the workstations.

9. The apparatus for testing chips as defined in claim 1, wherein after each of said test modules completes said predetermined test procedure for said chip on said plurality of electrical connectors connected thereto, said test module writes test result data and test parameter data of each of said chips into said chip, so that each of said chips stores test result data and test parameter data therein.

10. The chip testing apparatus according to claim 1, wherein each of the electrical connectors comprises:

the electric connecting seat body is provided with a top wall and an annular side wall, the top wall is provided with an opening, one end of the annular side wall is connected with the periphery of the top wall, the other end of the annular side wall is abutted against the circuit board, and a containing groove is formed by the top wall, the annular side wall and the circuit board together; two opposite side surfaces of the top wall are defined as an outer side surface and an inner side surface, and the inner side surface is positioned in the accommodating groove;

the supporting structure is abutted against the circuit board and is positioned in the accommodating groove, the supporting structure comprises a plurality of positioning holes, and each positioning hole is provided with one positioning piece;

the lifting structure is arranged in the accommodating groove and is provided with a base part and a bearing part, the base part is positioned in the accommodating groove, the base part extends towards one side to form the bearing part, and at least one part of the bearing part is positioned in the opening; the bearing part extends to one side far away from the base part to form a plurality of limiting parts, at least one part of the limiting parts penetrates through the opening, a chip containing groove is formed by the limiting parts and the bearing part together, and the chip containing groove is used for containing the chip; the lifting structure is also provided with a plurality of connecting holes which penetrate through the base part and the bearing part;

at least one elastic component, which is arranged in the containing groove, one end of each elastic component is fixed on the lifting structure, the other end of each elastic component is fixed on the supporting structure, the elastic restoring force generated by the compression of the elastic components enables the base part to be abutted against the inner side surface of the top wall, and a gap is formed between the lifting structure and the supporting structure;

one end of each probe assembly is fixedly arranged on the supporting structure, the other end of each probe assembly abuts against the contact structure of the circuit board, and the other ends of the probe assemblies penetrate through the connecting holes;

when the chip accommodating groove is provided with the chip and the limiting part is not pressed by a pressing device, the probe assemblies positioned in the connecting holes are not connected with the contact parts of the chip;

when the chip accommodating groove is provided with the chip, and the limiting part is pressed by the pressing device and is retracted towards the electric connection seat body, the probe assemblies abut against the contact parts, and the probe assemblies and the chip are connected with each other.

11. A chip test system, comprising:

a chip testing device, comprising:

the electric connection seats are provided with an electric connection seat body; one side of each electric connection seat body is used for bearing a chip, the other side of the electric connection seat body is provided with at least two positioning pieces, each positioning piece is mutually clamped with the plurality of positioning holes, and each electric connection seat is fixedly arranged on the first side surface of the circuit board; the first fixing member comprises a plurality of abutting structures which are correspondingly abutted against a part of the plurality of electric connecting seats, each electric connecting seat is abutted against and fixed on the first side surface of the electric connecting seat by the first fixing member, the first fixing member comprises a plurality of through holes, and a part of each electric connecting seat is correspondingly exposed out of each through hole;

the control unit is arranged on the second side face of the circuit board and comprises a plurality of test modules, and each test module is connected with one part of the electric connecting seats; the second fixing component is provided with a plurality of avoidance holes, and a part of the plurality of test modules penetrates through one of the avoidance holes; and

at least one power supply component connected with the circuit board;

a central control device; and

an environmental control apparatus, comprising:

the equipment body comprises a plurality of accommodating chambers, and is connected with power supply equipment; another power supply component is arranged in each accommodating chamber, and the power supply component in each accommodating chamber is connected with the power supply equipment;

the air extracting device is connected with each accommodating chamber and is connected with the central control device; the air pumping device can be controlled by the central control device to pump the air around the chips carried by the chip testing device outwards; and

a plurality of temperature adjusting devices provided in the apparatus body, one temperature adjusting device being provided in each of the accommodating chambers; each temperature adjusting device can be controlled by the central control device to increase or decrease the temperature around the plurality of chips carried by the chip testing device;

when the chip testing device is arranged in one of the accommodating chambers, the power supply equipment can provide power for the chip testing device through a power supply component in the accommodating chamber and the power supply component of the chip testing device; when the power supply equipment supplies power to the chip testing device, each testing module can perform a preset testing program on the chips borne by the electric connection seats connected with the testing module.

12. The chip test system according to claim 11, wherein each of the test modules comprises: the device comprises a graph generator, a component power supply module and a driving circuit; the chip is a memory, and the predetermined test program comprises: at least one of a read test, a write test, and an electrical test; the plurality of electric connection seats are partitioned into a plurality of electric connection seat groups, and each electric connection seat group comprises at least one electric connection seat; the plurality of test modules are connected with the plurality of electric connection seat groups, and each test module is connected with all the electric connection seats in the corresponding electric connection seat group; the plurality of test modules are connected with the plurality of electric connection seat groups, and each test module is connected with all the electric connection seats in the corresponding electric connection seat group.

13. The chip testing system according to claim 12, wherein each of the pressing structures is detachably fixed to the first fixing member, each of the first fixing members has a plurality of group receiving holes, and each of the group receiving holes is configured to receive a plurality of electrical connectors in the same electrical connector group; each abutting structure body is in a fence shape and is provided with a plurality of through holes, and one part of each electric connecting seat is correspondingly exposed out of each through hole.

14. The chip test system according to claim 13, wherein the circuit board is formed with a plurality of first contact structures on the second side, each of the test modules having at least one second contact structure, the second contact structure of each of the test modules being detachably contactable with one of the first contact structures.

15. The chip test system according to claim 11, wherein the power supply member includes a plurality of connection terminals, the plurality of connection terminals being disposed on the first side surface of the circuit board, and the plurality of connection terminals being exposed to the first fixing member; a plurality of accommodating chamber terminals are arranged in each accommodating chamber; when a plurality of the connection terminals are connected with a plurality of the accommodation chamber terminals in one of the accommodation chambers, the power supply device can supply power to the chip testing device.

16. The chip test system according to claim 11, wherein the power supply means is a receiving antenna for coupling with a transmitting antenna of the power supply device, and the chip test apparatus is capable of wirelessly receiving the power transmitted by the power supply device through the receiving antenna.

17. The chip testing system as claimed in claim 11, wherein the chip testing apparatus further comprises at least one first data transmission terminal disposed on the circuit board and exposed from the first fixing member, each of the receiving chambers comprises at least one second data transmission terminal connected to the central control apparatus; the first data transmission terminal can be in contact with the second data transmission terminal in each of the accommodation chambers, and the chip testing device can transmit information to the central control device.

18. The chip testing system according to claim 11, wherein the chip testing device further comprises at least one first data transmission antenna, the device body is provided with at least one second data transmission antenna, and the second data transmission antenna is connected to the central control device; the chip testing device can wirelessly transmit data with the central control device through the first data transmission antenna and the second data transmission antenna.

19. The system for testing chips of claim 11 wherein, after each of said test modules completes said predetermined test procedure on said chips on said plurality of electrical connectors connected thereto, said test modules will write test result data and test parameter data of each of said chips into said chips so that each of said chips stores test result data and test parameter data therein.

20. The chip test system of claim 11, wherein each electrical connector comprises:

21. The chip testing system according to claim 11, wherein each of said receiving chambers further comprises a cover; when the chip testing device is arranged in one of the accommodating chambers and the chip testing device is powered on, the cover body in the accommodating chamber correspondingly covers the first fixing member, the cover body, the first fixing member and the circuit board form a closed space together, the electric connection seats are correspondingly positioned in the closed space, and the air exhaust device can be controlled to exhaust air in the closed space outwards.

22. The chip testing system according to claim 21, wherein each of said receiving chambers further comprises a lifting device, each of said lifting devices being connected to said central control unit; each lifting device can be controlled by the central control device, so that the chip testing device is close to or far away from the cover body.