CN112786447B - Method for removing aluminum oxide and method for preparing three-dimensional memory - Google Patents

Method for removing aluminum oxide and method for preparing three-dimensional memory Download PDF

Info

Publication number
CN112786447B
CN112786447B CN202110087262.6A CN202110087262A CN112786447B CN 112786447 B CN112786447 B CN 112786447B CN 202110087262 A CN202110087262 A CN 202110087262A CN 112786447 B CN112786447 B CN 112786447B
Authority
CN
China
Prior art keywords
aluminum oxide
alumina
etching
wet etching
stack structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110087262.6A
Other languages
Chinese (zh)
Other versions
CN112786447A (en
Inventor
杜明利
李君�
李华东
徐融
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN202110087262.6A priority Critical patent/CN112786447B/en
Publication of CN112786447A publication Critical patent/CN112786447A/en
Application granted granted Critical
Publication of CN112786447B publication Critical patent/CN112786447B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the invention discloses a method for removing aluminum oxide, which comprises the following steps: providing a semiconductor structure comprising exposed aluminum oxide; removing the aluminum oxide by adopting a wet etching method; the etching solution adopted by the wet etching method comprises H 3 PO 4 And (3) solution.

Description

Method for removing aluminum oxide and method for preparing three-dimensional memory
Technical Field
The invention relates to the field of semiconductor preparation processes, in particular to a wet etching removal method for aluminum oxide.
Background
The fabrication of semiconductor devices usually requires a plurality of complicated semiconductor processes, and the conventional semiconductor processes include deposition, etching, cleaning, and packaging. With the increasing requirements of the performance, integration level, etc. of semiconductor devices, the structure of semiconductor devices is gradually developing towards the direction of complication and miniaturization, which brings challenges to the manufacturing process of semiconductor devices.
The alumina material is a commonly used dielectric material in the preparation process of semiconductor devices, and in some semiconductor device processing process links, the alumina material needs to be partially or completely removed. In the current prior art, the removal of the alumina material often requires a large number of man-hours, which severely reduces the production efficiency of the semiconductor device, which is unacceptable in mass production. In addition, in the conventional removal process, residues caused by incomplete removal of alumina also cause the problems of poor device stability, low production yield, increased cost and the like.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a method for removing aluminum oxide to solve at least one problem in the background art.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides an alumina removal method, which comprises the following steps:
providing a semiconductor structure comprising exposed aluminum oxide;
removing the aluminum oxide by adopting a wet etching method;
the etching solution adopted by the wet etching method comprises H 3 PO 4 And (3) solution.
In the scheme, the method comprises the following steps:
the alumina is formed by an atomic layer deposition method.
In the above scheme, the deposition conditions of the atomic layer deposition method include:
growing for 25-35h at the temperature above 500 ℃.
In the foregoing aspect, after the forming the aluminum oxide by the atomic layer deposition method, the method further includes:
and carrying out rapid thermal annealing treatment on the aluminum oxide.
In the foregoing embodiment, the rapid thermal annealing further includes:
and performing rapid thermal annealing treatment at the temperature of 800-1100 ℃ for 6-15 s.
In the above scheme, the thickness of the alumina is greater than 100 nm.
In the above scheme, before removing the alumina by wet etching, the method further includes:
forming a protective layer on other exposed portions of the semiconductor structure than the aluminum oxide.
In the above scheme, the protective layer is formed by a deposition process.
In the above scheme, the etching temperature of the wet etching method is 120-170 ℃.
In the above scheme, the H 3 PO 4 The solution is H 3 PO 4 A mixed solution with water, wherein the H 3 PO 4 The volume concentration of (A) is 80-95%.
In the above scheme, the removing the aluminum oxide by wet etching specifically includes: the alumina is completely removed by controlling the execution time of the wet etching method.
The invention also provides a preparation method of the three-dimensional memory, which comprises any scheme of the aluminum oxide removing method.
In a scheme of the method for manufacturing the three-dimensional memory, the providing a semiconductor structure includes:
providing a substrate;
forming a storage stack structure on the substrate;
forming aluminum oxide on the storage stack structure;
and patterning the aluminum oxide, and etching the storage stack structure by using the patterned aluminum oxide as a mask.
In the above scheme, the preparation method further comprises: and etching the stack layer by using the patterned aluminum oxide as a mask to form a step structure.
The method for removing the aluminum oxide comprises the steps of providing a semiconductor structure, wherein the semiconductor structure comprises exposed aluminum oxide; removing the aluminum oxide by adopting a wet etching method; the etching solution adopted by the wet etching method comprises H 3 PO 4 And (3) solution. Therefore, the time required by the alumina removal process is shortened, the production efficiency is improved, and the corresponding production cost is reduced; meanwhile, the reaction for removing the aluminum oxide is more thorough, the residues of the aluminum oxide are reduced, the stability of the device and the yield of the product are guaranteed, and the overall cost is reduced.
Drawings
FIG. 1 is a schematic flow chart of a method for removing alumina provided by an embodiment of the present invention;
FIGS. 2a and 2c are TEM images corresponding to different growth stages during the deposition of an alumina atomic layer, respectively; FIGS. 2b and 2d are HRTEM FFT images of different positions on the alumina material at different growth stages during the deposition of the alumina atomic layer, respectively;
FIG. 3 is an XRD pattern of alumina treated at different annealing temperatures;
FIG. 4 is a schematic flow chart of a process for fabricating a three-dimensional memory according to an embodiment of the invention;
fig. 5a to 5e are schematic structural diagrams of a three-dimensional memory provided in an embodiment of the invention in a manufacturing process;
fig. 6 is a TEM image at the position corresponding to the dashed box in fig. 5 e.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
As used in the following description, the term "three-dimensional memory" refers to a semiconductor device having the following memory cells: the memory cells are arranged vertically on a laterally oriented substrate such that the number of memory cells increases in the vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of a substrate.
The alumina material belongs to common amphoteric oxide, and is a common dielectric material in the preparation process of semiconductor devices, such as a gate insulating layer, an etching blocking mask and the like. In semiconductor device processing, the alumina material often needs to be partially or completely removed. In the prior art, a Single stand Single HSPM solution (a mixed solution of sulfuric acid and hydrogen peroxide) is typically used to remove alumina. However, the above removal process takes 16.5min to completely remove the alumina with a thickness of 120nm on a single wafer. The long process time seriously affects the productivity and the cost of the chip, and when the Single HSPM solution is adopted to remove the alumina, the alumina is often difficult to remove completely, the residue of the alumina can damage the stability of a semiconductor, the yield of products is reduced, and the production cost is improved.
Based on this, the embodiment of the invention provides a method for removing aluminum oxide; please refer to fig. 1. As shown in fig. 1, the method comprises the steps of:
step 101, providing a semiconductor structure, wherein the semiconductor structure comprises exposed aluminum oxide;
102, removing the aluminum oxide by adopting a wet etching method, wherein the etching solution adopted by the wet etching method comprises H 3 PO 4 And (3) solution.
In step 101, providing a semiconductor structure, comprising: the alumina is formed by an atomic layer deposition method. Here, the alumina may be specifically Al 2 O 3 。
In practical operation, the deposition conditions of the atomic layer deposition method include: growing at a temperature above 500 deg.C for 25-35h, such as at 550 deg.C for 30 h.
FIGS. 2a and 2c are TEM images corresponding to different growth stages during the deposition of the alumina atomic layer, respectively; fig. 2b and fig. 2d are HRTEM FFT images corresponding to different positions on the alumina material at different growth stages during the alumina atomic layer deposition process, respectively. Specifically, FIG. 2a is a TEM image of alumina grown to a thickness of 37.65nm during atomic layer deposition; FIG. 2b is a HRTEM FFT image corresponding to the arrow position in FIG. 2 a; fig. 2c is a TEM image of alumina grown to a thickness of 135.85nm during atomic layer deposition, and fig. 2d is a HRTEM FFT image corresponding to the position of the arrow in fig. 2 c.
As shown in FIGS. 2a-2b, when the alumina growth proceeded to a thickness of 37.65nm, the occurrence of amophorus → gamma-Al in the alumina partial region was detected 2 O 3 Phase transition of (2). As shown in FIGS. 2c-2d, when the alumina growth proceeded to a thickness of 135.85nm, in the alumina, more regions were detected to occur by amophorus → gamma-Al 2 O 3 Phase transition of (2). As will be appreciated by those skilled in the art, there is a concomitant amophorus → gamma-Al in the atomic layer deposition of alumina 2 O 3 The phase transformation process of (2), the alumina material in the phase state of gamma-Al 2O3 has the characteristics of harder texture and more stable property. Thus, the alumina in the present embodiment has higher hardness and higher stability.
In semiconductor structures, alumina having high hardness and high stability has wide application value. For example, in the fabrication process of a three-dimensional memory, the step area usually requires multiple patterning masks and multiple etching of the memory stack layer. With the increasing demand of memory capacity, the number of layers of the memory stack layer is increased, which means that the etching mask in the step region needs to withstand more patterning processes. Limited by the hardness limit of the current hard mask material, the hard mask is hard to withstand multiple patterning processes, which hinders the breakthrough of the number of stacks of the current three-dimensional memory. In view of the higher hardness and the higher stability of the aluminum oxide provided by the embodiment of the invention, the aluminum oxide provided by the embodiment of the invention can be applied to the hard mask material of the step region of the three-dimensional memory, can bear multiple patterning, and allows the three-dimensional memory to be provided with more stacked layers, thereby improving the storage capacity and the density of the three-dimensional memory. The above is merely illustrated by using alumina as a three-dimensional memory etching hard mask material, and it should be understood that the alumina provided by the embodiment of the present invention can be applied to any other semiconductor device and semiconductor process applying alumina.
In one embodiment, after the forming the aluminum oxide by the atomic layer deposition method, the method further comprises: and carrying out rapid thermal annealing treatment on the aluminum oxide.
In practical operation, the rapid thermal annealing process may further include: the rapid thermal annealing treatment is carried out at a temperature of 800-1100 ℃ for 6-15s, for example, at 900 ℃ for 10 s.
As shown in fig. 3, common alumina is a common amphoteric oxide, and the properties of the common alumina are changed by high-temperature thermal annealing, and the common alumina can be converted into other various phase states according to different thermal annealing conditions. Some phases of alumina have higher hardness and stability.
The rapid thermal annealing step provided by the embodiment of the invention further drives the non-phase-transformed region of the aluminum oxide material to complete amophorous → gamma-Al on the basis of atomic layer deposition 2 O 3 The phase transformation in the alumina is more sufficient, so that the alumina material with more hardness and more stable performance can be obtained. Based on this, the aluminum oxide provided by the embodiment of the invention allows more stacked layers to be arranged in the three-dimensional memory, and has more obvious advantages in the aspects of improving the storage capacity and density of the three-dimensional memory, and the like.
Further, the thickness of the hard mask layer may affect the morphology of the step obtained by etching, and an excessively thin mask layer may cause the mask not to withstand multiple patterning and may also cause deformation of the step region.
Based on this, in step 101, the alumina thickness may be above 100 nm.
Executing step 102, wherein the removing the aluminum oxide by using a wet etching method specifically comprises the following steps: the alumina is completely removed by controlling the execution time of the wet etching method.
In step 102, the wet etching method further includes: the etching temperature of the wet etching method is 120-170 ℃, such as 165 ℃.
In step 102, the H 3 PO 4 The solution is H 3 PO 4 A mixed solution with water, wherein the H 3 PO 4 The volume concentration of (a) is 80-95%, for example 80%, 85%, etc.
In one embodiment, prior to step 102, the method further comprises:
forming a protective layer on other exposed portions of the semiconductor structure than the aluminum oxide.
Here, the protective layer may be formed by a deposition process.
The material of the protective layer may be silicon oxide. It should be understood that the embodiments of the present application are not limited thereto, and the material of the protective layer may be selected according to a specific semiconductor structure and a specific process condition.
In a specific application, the protective layer may also fill gaps between the aluminum oxide and other portions of the semiconductor structure.
The following is an example of the case where alumina is applied to a three-dimensional memory. The embodiment of the invention provides a preparation method of a three-dimensional memory, which comprises the method for removing aluminum oxide in any one of the previous embodiments of the invention.
Specifically, in an embodiment, the method for manufacturing the three-dimensional memory includes:
providing a semiconductor structure comprising exposed aluminum oxide; removing the aluminum oxide by adopting a wet etching method, wherein the etching solution adopted by the wet etching method comprises H 3 PO 4 And (3) solution.
As shown in fig. 4, in one embodiment, the providing a semiconductor structure includes:
step 401, providing a substrate;
step 402, forming a storage stack structure on the substrate;
step 403, forming aluminum oxide on the storage stack structure;
step 404, patterning the aluminum oxide, and etching the storage stack structure by using the patterned aluminum oxide as a mask to form a step structure.
The above steps are described in detail below with reference to fig. 5a-5 d.
First, as shown in fig. 5a, step 401 is performed to provide a substrate 10. In the embodiment of the present application, the material of the substrate 10 may include bulk silicon (bulk Si), bulk germanium (bulk ge), silicon-on-insulator (SOI), germanium-on-insulator (GeOI), or other compound semiconductor substrate, such as SiGe, SiC, GaN, GaAs, InP, etc., and combinations thereof. In one embodiment provided herein, a substrate of silicon-containing material, such as Si, SOI, SiGe, or SiC, is used for compatibility with existing IC fabrication processes.
Next, step 402 is performed to form a storage stack structure 11 on the substrate 10. The memory stack structure 11 includes a plurality of sacrificial layers and interlayer dielectric layers stacked alternately, a top dielectric layer 18 located on the sacrificial layers and the interlayer dielectric layers, and a channel structure 17 penetrating through the sacrificial layers and the interlayer dielectric layers. Here, the top dielectric layer 18 material includes, but is not limited to, silicon oxide, silicon nitride layers, silicon oxynitride, and other high dielectric constant (high-k) dielectric layers. The sacrificial layer is, for example, a dummy gate layer, and the material thereof includes, but is not limited to, silicon nitride; the interlayer dielectric layer is an insulating isolation layer between the memory units formed at the position of the sacrificial layer in the subsequent process, and the material of the interlayer dielectric layer comprises but is not limited to silicon oxide, a silicon nitride layer, silicon oxynitride and other high dielectric constant (high-k) dielectric layers. In this embodiment, the sacrificial layer may be formed of silicon nitride (SiN), and the interlayer dielectric layer may be formed of silicon oxide (SiO) 2 ) Thereby forming an NO stack. The sacrificial layer and the interlayer dielectric layer may be formed using a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or an Atomic Layer Deposition (ALD) process; wherein the sacrificial layer and the interlayer dielectric layer may have the same thickness or have the same thicknessDifferent in thickness from each other. In addition, the embodiment of the invention does not exclude the mode of directly forming a plurality of gate layers and interlayer dielectric layers which are alternately arranged; namely, the gate layer material required by the three-dimensional memory is directly deposited on the substrate without adopting the position occupied by the sacrificial layer.
Next, as shown in fig. 5c, step 403 is performed to form aluminum oxide 13 on the memory stack structure 11.
In some embodiments, the alumina 13 may be formed using an atomic layer deposition method. In practical operation, the deposition conditions for forming the alumina 13 by the atomic layer deposition method include: growing for 25-35h at the temperature above 500 ℃.
In some embodiments, after forming the aluminum oxide using an atomic layer deposition method, the method further comprises: and carrying out rapid thermal annealing treatment on the aluminum oxide. In practical operation, the rapid thermal annealing treatment comprises performing rapid thermal annealing treatment on the aluminum oxide at the temperature of 800-1100 ℃ for 6-15 s.
In some embodiments, as shown in fig. 5c, before forming the aluminum oxide 13 on the storage stack structure 11, the method further comprises: an auxiliary hard mask layer 16 is formed on the memory stack structure 11. The auxiliary hard mask layer is made of one or more of silicon oxide, silicon oxynitride and amorphous carbon. As shown in fig. 5c, the auxiliary hard mask layer 16 is located below the aluminum oxide 13, and forms a hard mask layer with a step structure by etching together with the aluminum oxide 13.
Next, as shown in fig. 5d, step 404 is performed to pattern the aluminum oxide 13, and etch the storage stack structure 11 by using the patterned aluminum oxide 13 as a mask, so as to form a step structure 14.
In practical operation, the etching the storage stack structure 11 to form the step structure 14 using the patterned aluminum oxide 13 as a mask includes etching the storage stack structure 11 through multiple patterning of the aluminum oxide 13 and multiple etching processes to form the step structure 14. The patterning of the aluminum oxide comprises the steps of coating photoresist on the aluminum oxide, exposing and developing the photoresist, and etching the aluminum oxide by taking the exposed and developed photoresist as a mask. The etching of the alumina may be performed using a dry etching process, such as, for example, a Reactive Ion Etching (RIE) process or a high density plasma etching (HDP) process, etc. In an actual process, each sacrificial layer in the storage stack structure 11 may be exposed on a step surface of the step region.
Further, the thickness of the hard mask layer may affect the morphology of the step obtained by etching, and an excessively thin mask layer may cause the mask not to withstand multiple patterning and may also cause deformation of the step region. Based on this, the alumina thickness may be 100nm or more.
In the embodiment where the method further includes forming an auxiliary hard mask layer, after the aluminum oxide is patterned, the auxiliary hard mask layer 16 is continuously patterned, and the patterned aluminum oxide 13 and the auxiliary hard mask layer 16 are used together as a mask to etch the storage stack structure 11, so as to form the step structure 14. The etching of the memory stack structure may be implemented using a dry/wet etching process, such as a Reactive Ion Etching (RIE) process or a high density plasma etching (HDP) process, for example.
The process is carried out to this point resulting in a semiconductor structure as shown in figure 5d, which comprises exposed aluminum oxide. Fig. 6 is a TEM image of the corresponding semiconductor structure at the location of the dashed box in fig. 5 d. It can be seen that the semiconductor structure includes a memory stack 11, and an alumina 13 located on the memory stack 11. In some embodiments that include an auxiliary hard mask layer, the corresponding TEM image will also include an image of the auxiliary hard mask layer 16 (not shown here) underlying the aluminum oxide 13.
After the step of providing the semiconductor structure is completed, a step of removing the aluminum oxide by a wet etching method (i.e., step 405 in fig. 4) is performed, specifically including removing the aluminum oxide by a wet etching method using an etching solution including H 3 PO 4 And (3) solution.
In practical operation, the etching temperature of the wet etching method is 120-170 ℃. Specifically, theH 3 PO 4 The solution may be H 3 PO 4 A mixed solution with water, wherein the H 3 PO 4 The volume concentration of (A) is 80-95%. By controlling the execution time of the wet etching method, the alumina 13 is completely removed.
In one embodiment, as shown in fig. 5e, before removing the aluminum oxide by wet etching, the method further comprises: forming a protective layer 15 on the exposed portion of the semiconductor structure other than the alumina 13 specifically includes forming a protective layer on the surface exposed portion, the sidewalls, and the bottom (the protective layer on the sidewalls and the bottom is not shown).
In practice, the protective layer may be formed using a deposition process, including but not limited to a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or an Atomic Layer Deposition (ALD) process, among others.
According to the embodiment of the invention, the working hours required by the alumina removal process are shortened, the number of chips produced per machine per hour can be increased from 30 to 180, the cost of each chip is reduced from 20 dollars to 1 dollar, and the method has a wide application value in industrial production.
In the present invention, the technical features described in the embodiments can be arbitrarily combined without conflict. It should be further noted that, the technical features of the method for removing aluminum oxide provided in the embodiments of the present application can be combined to solve the technical problems to be solved by the present application; therefore, the method for removing aluminum oxide provided by the embodiment of the present application is not limited by the method for removing aluminum oxide in a three-dimensional memory provided by the embodiment of the present application, and any device or process segment requiring aluminum oxide removal to which the method for removing aluminum oxide provided by the embodiment of the present invention is applied is within the scope of protection of the present application.
The above description is only exemplary of the present application and should not be taken as limiting the scope of the present application, as any modifications, equivalents, improvements, etc. made within the spirit and principle of the present application should be included in the scope of the present application.

Claims (10)

1. A method for removing alumina, the method comprising:
providing a semiconductor structure comprising exposed aluminum oxide;
the aluminum oxide is used as an etch stop mask,
the aluminum oxide is formed by adopting an atomic layer deposition method, and the thickness of the aluminum oxide is more than 100 nm; after the aluminum oxide is formed by adopting an atomic layer deposition method, carrying out rapid thermal annealing treatment on the aluminum oxide at the temperature of more than 900 ℃ and less than or equal to 1100 ℃ for 6-15 s; removing the aluminum oxide by adopting a wet etching method; the etching solution adopted by the wet etching method comprises H 3 PO 4 And (3) solution.
2. The method of claim 1, wherein the deposition conditions of the atomic layer deposition method comprise:
growing for 25-35h at the temperature of over 500 ℃.
3. The method of claim 1, wherein prior to removing the aluminum oxide using a wet etch process, the method further comprises:
forming a protective layer on other exposed portions of the semiconductor structure than the aluminum oxide.
4. The method of claim 3,
the protective layer is formed by a deposition process.
5. The method as claimed in claim 1, wherein the etching temperature of the wet etching method is 120-170 ℃.
6. The method of claim 1, wherein the H is 3 PO 4 The solution is H 3 PO 4 With waterMixing the solution, wherein the H 3 PO 4 The volume concentration of (A) is 80-95%.
7. The method according to claim 1, wherein the removing the aluminum oxide by wet etching comprises: the alumina is completely removed by controlling the execution time of the wet etching method.
8. A method for producing a three-dimensional memory, characterized in that the method comprises the method for removing aluminum oxide according to any one of claims 1 to 7.
9. The method of manufacturing according to claim 8, wherein the providing a semiconductor structure comprises: providing a substrate; forming a storage stack structure on the substrate;
forming aluminum oxide on the storage stack structure;
and patterning the aluminum oxide, and etching the storage stack structure by using the patterned aluminum oxide as a mask.
10. The method according to claim 9, wherein the etching the memory stack structure with the patterned alumina as a mask comprises: and etching the storage stack structure by taking the patterned aluminum oxide as a mask to form a step structure.
CN202110087262.6A 2021-01-22 2021-01-22 Method for removing aluminum oxide and method for preparing three-dimensional memory Active CN112786447B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110087262.6A CN112786447B (en) 2021-01-22 2021-01-22 Method for removing aluminum oxide and method for preparing three-dimensional memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110087262.6A CN112786447B (en) 2021-01-22 2021-01-22 Method for removing aluminum oxide and method for preparing three-dimensional memory

Publications (2)

Publication Number Publication Date
CN112786447A CN112786447A (en) 2021-05-11
CN112786447B true CN112786447B (en) 2022-08-30

Family

ID=75758544

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110087262.6A Active CN112786447B (en) 2021-01-22 2021-01-22 Method for removing aluminum oxide and method for preparing three-dimensional memory

Country Status (1)

Country Link
CN (1) CN112786447B (en)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156867A (en) * 2004-12-01 2006-06-15 Seiko Epson Corp Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device
US8609536B1 (en) * 2012-07-06 2013-12-17 Micron Technology, Inc. Stair step formation using at least two masks
WO2017081579A1 (en) * 2015-11-13 2017-05-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9905514B2 (en) * 2016-04-11 2018-02-27 Micron Technology, Inc. Semiconductor device structures including staircase structures, and related methods and electronic systems
US10361121B2 (en) * 2016-05-13 2019-07-23 Intel Corporation Aluminum oxide for thermal management or adhesion
CN107706184A (en) * 2017-08-22 2018-02-16 长江存储科技有限责任公司 The preparation method and its structure of a kind of three-dimensional storage
CN118785714A (en) * 2018-06-22 2024-10-15 长江存储科技有限责任公司 Method for manufacturing word line connection area of three-dimensional memory and three-dimensional memory
JP2020047848A (en) * 2018-09-20 2020-03-26 キオクシア株式会社 Semiconductor memory
US10903623B2 (en) * 2019-05-14 2021-01-26 Soraa Laser Diode, Inc. Method and structure for manufacturable large area gallium and nitrogen containing substrate
CN111584359A (en) * 2020-05-09 2020-08-25 中国科学院上海技术物理研究所 Al deposition based on ALD2O3Ultrasonic wet etching method as mask

Also Published As

Publication number Publication date
CN112786447A (en) 2021-05-11

Similar Documents

Publication Publication Date Title
US8461028B2 (en) Synthesizing graphene from metal-carbon solutions using ion implantation
CN106229288B (en) Active area preparation method
US11189729B2 (en) Forming a sacrificial liner for dual channel devices
CN104900495B (en) The preparation method of self-alignment duplex pattern method and fin formula field effect transistor
US20090155977A1 (en) Methods for Forming a Gate and a Shallow Trench Isolation Region and for Planarizating an Etched Surface of Silicon Substrate
US20090096055A1 (en) Method to form cmos circuits with sub 50nm sti structures using selective epitaxial silicon post sti etch
US7892929B2 (en) Shallow trench isolation corner rounding
CN114038801A (en) Method for forming semiconductor device
CN112786447B (en) Method for removing aluminum oxide and method for preparing three-dimensional memory
CN110752213A (en) Method for manufacturing semiconductor structure
CN107978514A (en) Transistor and forming method thereof
CN109461651A (en) Improve the method for silicide barrier layer etching defect
CN107591399B (en) Semiconductor structure and forming method thereof
CN109860291A (en) Semiconductor structure and forming method thereof
CN109148294B (en) Semiconductor structure and forming method thereof
TWI845979B (en) Integrated wet clean for gate stack development
US11646262B2 (en) Semiconductor device with horizontally arranged capacitor and method for fabricating the same
US20230040843A1 (en) Nanostructure field-effect transistor device and method of forming
US11948843B2 (en) Method for forming hardmask formation by hybrid materials in semiconductor device
CN118380325B (en) Fin surface treatment method of fin field effect transistor
US11271097B2 (en) Cap oxidation for FinFET formation
KR20080011619A (en) Method for forming isolation layer of semiconductor device
CN104157600A (en) Shallow groove structure manufacturing method
CN105990128B (en) The forming method of insulating layer, EEPROM and forming method thereof
JP2024522986A (en) Sacrificial cap layer for contact etching

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant