CN112752097B

CN112752097B - Method and system for testing CMOS image sensor

Info

Publication number: CN112752097B
Application number: CN202011642675.8A
Authority: CN
Inventors: 刘洋; 李扬; 马成; 戚忠雪
Original assignee: Changchun Changguang Chenxin Microelectronics Co ltd
Current assignee: Changchun Changguang Chenxin Microelectronics Co ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2023-05-26
Anticipated expiration: 2040-12-30
Also published as: CN112752097A

Abstract

The invention provides a method and a system for testing a CMOS image sensor, wherein the testing system comprises a master controller and image sensor mounting equipment; the image sensor mounting equipment is used for mounting the CMOS image sensor, and is also provided with pin debugging equipment which is used for configuring the working modes of all pins on the CMOS image sensor; the master controller is electrically connected with the pin debugging equipment and used for controlling the pin debugging equipment to debug each pin on the CMOS image sensor. According to the scheme, the universal image sensor testing platform is constructed to meet the testing conditions of the image sensor, so that the repeated testing workload and testing preparation time are reduced.

Description

Method and system for testing CMOS image sensor

Technical Field

The present invention relates to the field of image sensors, and in particular, to a method and a system for testing a CMOS image sensor.

Background

Along with the development of integrated circuit manufacturing technology and the continuous improvement of integrated circuit design level, the CMOS image sensor manufactured based on the CMOS integrated circuit technology gradually takes advantage in the competition of CCD due to the characteristics of high integration level, low power consumption, small volume, simple process, low cost, short development period and the like. The CMOS image sensor is widely applied to various photographic products and has wide market application prospect.

With the rapid development of semiconductor technology, the application range of CMOS image sensors is expanding continuously, and the CMOS image sensors have infinite application space in the fields of monitoring security, machine vision, intelligent automobiles, consumer products and the like, while the image sensors are a key point of the development of the technologies, because of the different package sizes and pin numbers of the image sensors, different test systems are required to be designed for different image sensors when the image sensors are tested, and the differences of different test systems are not large in many times, if the whole test system cannot be used continuously only because of the disuse of pin distribution sequences, the test resources are wasted greatly.

Disclosure of Invention

Therefore, the invention provides a technical scheme for testing the CMOS image sensor, which is used for solving the problems of poor reusability and complex construction of the existing testing system of the CMOS image sensor.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.

To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a first aspect of the invention provides a test system of a CMOS image sensor, the test system including a general controller and an image sensor mounting apparatus;

the image sensor mounting equipment is used for mounting the CMOS image sensor, and is also provided with pin debugging equipment which is used for configuring the working modes of all pins on the CMOS image sensor;

the master controller is electrically connected with the pin debugging equipment and used for controlling the pin debugging equipment to debug each pin on the CMOS image sensor.

Preferably, the test system further comprises a data buffer;

the data buffer is electrically connected with the master controller and is used for buffering the image data transmitted by the CMOS image sensor.

Preferably, the test system further comprises a data processor, and the data processor is electrically connected with the data buffer and the master controller respectively;

the data processor is used for acquiring the image data cached in the data cache after receiving the data processing control signal sent by the master controller, processing and calculating the image data, and generating a test report according to the processing and calculating results.

Preferably, the data processor is an FPGA processor.

Preferably, the test system further comprises a test result display device, wherein the test result display device is connected with the data processor and is used for displaying the test report.

Preferably, the test system further comprises a light source controller, and the light source controller is connected with the master controller; the light source controller is used for receiving a light source control signal sent by the master controller and providing test light for the CMOS image sensor according to the light source control signal.

Preferably, the light source controller includes a light source configuration register storing operation data of a plurality of light source modes;

the "providing test light for the CMOS image sensor according to the light source control signal": and determining a current light source mode according to the light source control signal, and acquiring and operating operation data corresponding to the light source mode from the light source configuration register so as to emit test light conforming to the current light source mode.

Preferably, the operation modes of the respective pins include: any one of a data mode, a power supply mode, a reference voltage mode, a ground mode, a bias mode.

Preferably, the image sensor mounting apparatus has a greater number of pins than the CMOS image sensor.

The second aspect of the present invention also provides a method for testing a CMOS image sensor, the method comprising the steps of:

installing the CMOS image sensor on the image sensor installation equipment, and configuring the working modes of all pins on the CMOS image sensor through pin debugging equipment on the image sensor installation equipment;

according to the working modes configured by the pins, connecting a data output pin with a data buffer memory, which is in a working mode, with the data buffer memory, connecting a data input pin with a master controller through an interface, and sending corresponding configuration signals through the master controller;

modifying the connection configuration between the data buffer and the data processor to meet the data transmission requirement between the data buffer and the data processor; modifying interface configuration between a data processor and test result display equipment to meet data transmission requirements of the data processor and the test result display equipment;

configuring a master controller according to the test requirement, and configuring other module components in a test system through the master controller;

after the connection configuration work of all the modules is completed, a power switch is turned on, at the moment, each module works under the control of a master controller, and after the system is stable, the working state of each module in the current test system and the judgment result of the test system on the performance of the image sensor are observed through the content displayed on the test result display device.

The invention provides a method and a system for testing a CMOS image sensor, wherein the testing system comprises a general controller and image sensor mounting equipment; the image sensor mounting equipment is used for mounting the CMOS image sensor, and is also provided with pin debugging equipment which is used for configuring the working modes of all pins on the CMOS image sensor; the master controller is electrically connected with the pin debugging equipment and used for controlling the pin debugging equipment to debug each pin on the CMOS image sensor. According to the scheme, the universal image sensor testing platform is constructed to meet the testing conditions of the image sensor, the repeated testing workload and testing preparation time are reduced, all modules in the testing system can be configured through the master controller, and meanwhile, according to different testing requirements, the modules can be independently modified (such as the working mode of a modification pin) so that the requirements of the CMOS image sensor in different testing application scenes can be met.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a schematic diagram of a testing system of a CMOS image sensor according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a testing system of a CMOS image sensor according to another embodiment of the present invention;

FIG. 3 is a schematic view showing a structure of an image sensor mounting apparatus according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating an operation mode configuration of a pin according to an embodiment of the present invention;

fig. 5 is a flowchart of a method for testing a CMOS image sensor according to an embodiment of the present invention.

Reference numerals illustrate:

101. a master controller;

102. an image sensor mounting device; 1021. pin debugging equipment; 1022. pins;

103. a data buffer;

104. a data processor;

105. test result display equipment;

106. a light source controller; 1061. a light source configuration register;

107. a CMOS image sensor;

Detailed Description

It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the singular is "a," an, "and/or" the "when used in this specification is taken to mean" the presence of a feature, step, operation, device, component, and/or combination thereof.

Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways and the spatially relative descriptions used herein are construed accordingly.

Fig. 1 is a schematic structural diagram of a test system of a CMOS image sensor according to an embodiment of the invention. The first aspect of the present invention provides a test system for a CMOS image sensor, the test system comprising a general controller 101 and an image sensor mounting device 102;

the image sensor mounting device 102 is used for mounting the CMOS image sensor, and a pin debugging device 1021 is further arranged on the image sensor mounting device 102, and the pin debugging device is used for configuring the working mode of each pin on the CMOS image sensor; the master controller 101 is electrically connected to the pin debugging device 1021, and is used for controlling the pin debugging device 1021 to debug each pin on the CMOS image sensor. The overall controller 101 is a control core of the whole test system, and controls the operation of each module (such as a pin debugging device and the like) through instructions.

The image sensor mounting apparatus 102 is mainly used for mounting a CMOS image sensor, on which the power supply size and the value of the reference voltage can be changed by configuring a circuit to be suitable for different image sensors, and meanwhile, channels of signals can be configured to meet the requirement of signal transmission. Preferably, as shown in fig. 3, the image sensor mounting apparatus has a greater number of pins 1022 than the CMOS image sensor. In this way, the testing of a plurality of CMOS image sensors 107 can be performed simultaneously on one image sensor mounting apparatus 102.

According to the scheme, the image sensor mounting equipment 102 is arranged to debug each pin on the CMOS image sensor, so that repeated testing workload and testing preparation time are effectively reduced, and testing efficiency is improved.

As shown in fig. 2, the test system further includes a data buffer 103; the data buffer 103 is electrically connected to the overall controller 101, and the data buffer 103 is used for buffering the image data transmitted by the CMOS image sensor. The reasons for setting the data buffer 103 are mainly two, one is that when the test system works, the data of the image sensor is continuously output, and the data processor needs time for processing the data, so that the data can be temporarily stored by setting the data buffer 103 in order to ensure the accuracy of the system data; secondly, because the data output of the image sensor is a high-frequency signal, the image sensor is easy to be interfered by the outside, and the accuracy of the data can be ensured by analyzing and caching the image.

In some embodiments, the test system further comprises a data processor 104, and the data processor 104 is electrically connected to the data buffer 103 and the overall controller 101, respectively; the data processor 104 is configured to receive a data processing control signal sent by the overall controller 101, obtain image data cached in the data cache 103, process and calculate the image data, and generate a test report according to a processing and calculating result. In this embodiment, the data processor 104 receives the image data buffered by the data buffer 103, and processes and calculates the image data to determine the working state of the system and the performance of the image sensor.

Preferably, the data processor is an FPGA processor. The FPGA processor adopts a concept of a logic cell array LCA (Logic Cell Array), and includes three parts, i.e., a configurable logic module CLB (Configurable Logic Block), an input-output module IOB (Input Output Block), and an Interconnect (Interconnect). A Field Programmable Gate Array (FPGA) is a programmable device that has a different structure than conventional logic circuits and gate arrays (such as PAL, GAL, and CPLD devices). The FPGA utilizes small lookup tables (16X 1 RAM) to realize the combinational logic, each lookup table is connected to the input end of one D trigger, and the trigger drives other logic circuits or drives I/O, so that basic logic unit modules which can realize the combinational logic function and the sequential logic function are formed, and the modules are mutually connected or connected to the I/O modules through metal wires. The logic of the FPGA is realized by loading programming data into an internal static storage unit, the value stored in the storage unit determines the logic function of the logic unit and the connection mode between each module or between the modules and I/O, and finally determines the function realized by the FPGA, and the FPGA allows unlimited programming.

In some embodiments, the test system further comprises a test result display device 105, the test result display device 105 being connected to the data processor 104, the test result display device 105 being configured to display the test report.

In certain embodiments, the test system further comprises a light source controller 106, the light source controller 106 being connected to the overall controller 101; the light source controller 106 is configured to receive a light source control signal sent by the overall controller 101, and provide test light for the CMOS image sensor according to the light source control signal.

Preferably, the light source controller 106 includes a light source configuration register 1061, and the light source configuration register 1061 stores operation data of a plurality of light source modes. The "providing test light for the CMOS image sensor according to the light source control signal": the current light source mode is determined according to the light source control signal, and the operation data corresponding to the light source mode is obtained and operated from the light source configuration register 1061, so as to emit test light conforming to the current light source mode. Of course, the overall controller 101 may also write the operation data of the new light source mode into the light source configuration register 1061 according to the actual requirement, so as to meet the requirements of different application scenarios.

As shown in fig. 4, the operation modes of the respective pins include: any one of a data mode, a power supply mode, a reference voltage mode, a ground mode, a bias mode. The data mode may in turn be configured as a data input mode, a data output mode, and a data input output mode. The power supply mode can provide required power supply voltage in a resistance adjustment mode according to different power supply sizes required by pins. The reference voltage mode can provide the required reference voltage in a resistance adjustment mode according to the different reference voltage sizes required by the pins. The ground mode may select different grounds for the pins, wherein all kinds of grounds are connected inside the device; the bias mode may be configured by configuring different capacitances and connecting to the corresponding ground.

As shown in fig. 5, the second aspect of the present invention further provides a method for testing a CMOS image sensor, the method comprising the steps of:

firstly, step S501 is carried out to mount the CMOS image sensor on the image sensor mounting equipment, and the working modes of all pins on the CMOS image sensor are configured through pin debugging equipment on the image sensor mounting equipment;

step S502 is then entered into, according to the working modes configured by the pins, connecting the data output pins with the working modes being data modes with the data buffer, simultaneously connecting the data input pins with the master controller through the interface, and transmitting corresponding configuration signals through the master controller;

step S503 is then performed to modify the connection configuration between the data buffer and the data processor so as to meet the data transmission requirement between the data buffer and the data processor; modifying interface configuration between a data processor and test result display equipment to meet data transmission requirements of the data processor and the test result display equipment;

and then, the step S504 is carried out to configure the overall controller according to the test requirement, and other module components in the test system are configured through the overall controller. For example, the overall controller changes its test light source signal by sending a different light source control signal to the light source controller, etc.

And then, step S505 is carried out, after the connection configuration work of all the modules is completed, a power switch is turned on, at the moment, all the modules work under the control of a master controller, after the system is stable, the working state of each module in the current test system and the judgment result of the test system on the performance of the image sensor are observed through the content displayed on the test result display device.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments is modified or some or all of the technical features are replaced equivalently, so that the essence of the corresponding technical scheme does not deviate from the scope of the technical scheme of the embodiments of the present invention.

The foregoing description is only a technical content closely related to the inventive point of the present application, and some conventional steps for forming an image sensor are not described in detail, but a person skilled in the art has the ability to combine the present application with the conventional steps of the prior art on the basis of combining the prior art, so that the detailed description is omitted herein.

From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects: the universal image sensor test platform is constructed to meet the test conditions of the image sensor, the repeated test workload and test preparation time are reduced, all modules in the test system can be configured through the master controller, and meanwhile, according to different test requirements, the modules can be independently modified (such as the working mode of a modification pin) so as to meet the requirements of the CMOS image sensor in different test application scenes.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. It is therefore intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. A test system for a CMOS image sensor, the test system comprising a general controller and an image sensor mounting apparatus;

the working modes of the pins comprise: any one of a data mode, a power supply mode, a reference voltage mode, a ground mode, a bias mode;

2. The test system of a CMOS image sensor of claim 1, wherein the test system further comprises a data buffer;

3. The CMOS image sensor testing system according to claim 2, further comprising a data processor electrically connected to the data buffer and the overall controller, respectively;

4. A CMOS image sensor testing system according to claim 3, wherein the data processor is an FPGA processor.

5. The CMOS image sensor testing system according to claim 3 or 4, further comprising a test result display device connected to the data processor, the test result display device for displaying the test report.

6. The CMOS image sensor testing system according to claim 1, further comprising a light source controller connected to the overall controller; the light source controller is used for receiving a light source control signal sent by the master controller and providing test light for the CMOS image sensor according to the light source control signal.

7. The CMOS image sensor testing system according to claim 6, wherein the light source controller includes a light source configuration register storing operation data of a plurality of light source modes;

8. The test system of the CMOS image sensor according to claim 1, wherein the image sensor mounting apparatus has a greater number of pins than the CMOS image sensor has.

9. A method of testing a CMOS image sensor, the method comprising the steps of: