CN112750915B - Thin film gallium arsenide solar cell upper electrode and preparation method thereof - Google Patents
Thin film gallium arsenide solar cell upper electrode and preparation method thereof Download PDFInfo
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- CN112750915B CN112750915B CN202110233503.3A CN202110233503A CN112750915B CN 112750915 B CN112750915 B CN 112750915B CN 202110233503 A CN202110233503 A CN 202110233503A CN 112750915 B CN112750915 B CN 112750915B
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- 238000001704 evaporation Methods 0.000 claims description 18
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022433—Particular geometry of the grid contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0693—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
A thin film gallium arsenide solar cell upper electrode and a preparation method thereof are provided, the thin film gallium arsenide solar cell upper electrode comprises: the bottom metal grid, the dielectric layer and the top metal grid are sequentially arranged on the outer surface of the epitaxial wafer from inside to outside, and the bottom metal grid is connected with the top metal grid. The upper electrode of the thin film gallium arsenide solar cell and the preparation method thereof provided by the invention have the following advantages and positive effects: by using the local insulation type upper electrode structure, the short circuit phenomenon caused by local pressure of the battery can be effectively avoided, and the output efficiency of the battery is ensured; the oxide dielectric layer is used as an insulating structure, so that the insulating structure has the characteristics of high temperature resistance, good bonding force, strong insulating property and the like; the upper electrode is prepared by adopting the photoetching technology and the vacuum evaporation technology, and the method has the characteristics of simple process, mature technology and the like.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an upper electrode of a thin-film gallium arsenide solar cell and a preparation method thereof.
Background
The growth process of the metal organic compound vapor phase epitaxy technology is an advanced technology that metal organic compound vapor and non-metal hydride are sent to a substrate heated in a reaction chamber through a multi-way switch by using hydrogen carrier gas and finally an epitaxial layer is grown on the substrate through decomposition reaction.
The gallium arsenide is used as a substrate to grow and prepare III-V family epitaxial structures, which is an important technical means for manufacturing solar cells and LEDs, wherein the solar cells can be grown into multijunction solar cells, and the efficiency of the multijunction solar cells is far higher than that of other types of solar cells. Meanwhile, gallium arsenide is a direct bandgap semiconductor, and thus, a thin structure is required to realize the required functions. At present, a pure metal system is mostly used as an upper electrode of a thin film gallium arsenide solar cell, and the thin film gallium arsenide solar cell has the defects that the cell is easily damaged when the electrode is subjected to local pressure due to good metal ductility and brittle thin film gallium arsenide materials, and the output power of the cell is greatly reduced due to the fact that the upper electrode and the lower electrode are connected and short-circuited.
Disclosure of Invention
In order to solve the above problems, the present invention provides an upper electrode of a thin film gallium arsenide solar cell, comprising: the bottom metal grid, the dielectric layer and the top metal grid are sequentially arranged on the outer surface of the epitaxial wafer from inside to outside, and the bottom metal grid is connected with the top metal grid.
Preferably, the bottom metal gate includes: the solar cell comprises a bottom layer main grid, bottom layer welding points and bottom layer fine grids, wherein the bottom layer main grid is arranged on the side edge of the solar cell, the bottom layer welding points are arranged on the bottom layer main grid at equal intervals, and the bottom layer fine grids are uniformly arranged on the epitaxial wafer and are perpendicular to the bottom layer main grid.
Preferably, the width range of the bottom layer main grid is 0.2mm-1mm, the length range of the bottom layer main grid is 5mm-100mm, the width range of the bottom layer fine grid is 0.005mm-0.1mm, the length range of the bottom layer fine grid is 5mm-100mm, and the size range of the bottom layer welding spot is 0.5mm × 0.5mm-5mm × 5mm.
Preferably, the top metal gate includes: the top layer main grid is arranged on the side edge of the dielectric layer, the top layer welding points are arranged on the top layer main grid at equal intervals, and the top layer fine grids are uniformly arranged on the dielectric layer and are perpendicular to the top layer main grid.
Preferably, the width range of the top layer main grid is 0.2mm-1mm, the length range of the top layer main grid is 5mm-100mm, the width range of the top layer fine grid is 0.005mm-0.1mm, the length range of the top layer fine grid is 5mm-100mm, and the size range of the top layer welding point is 0.5mm x 0.5mm-5mm x 5mm.
Preferably, the epitaxial wafer is a thin film gallium arsenide epitaxial wafer, and the outermost surface is an N-type gallium arsenide contact layer.
Preferably, the dielectric film is SiOx, alOx, tiOx, or SiNx.
Preferably, the thickness of the dielectric film is 20nm-200nm.
Preferably, the dielectric layer is in a discontinuous dispersed pattern, the area of the bottom layer main grid in the bottom layer metal grid is 50% -80%, the area of the bottom layer welding point in the bottom layer metal grid is 100%, and the area of the bottom layer fine grid in the bottom layer metal grid is 10% -30%.
The invention also provides a preparation method of the upper electrode of the thin-film gallium arsenide solar cell, wherein the upper electrode of the thin-film gallium arsenide solar cell comprises the upper electrode of any one of the thin-film gallium arsenide solar cells, and the method comprises the following steps:
placing the epitaxial wafer into acetone, ultrasonically cleaning for more than 5 minutes, and then flushing water for spin-drying;
putting the epitaxial wafer into a gluing machine table, and uniformly coating a layer of photoresist with the thickness of 500nm-3000 nm;
making a bottom metal gate pattern on the photoresist;
placing the epitaxial wafer into a vacuum coating machine, and enabling one side of the bottom layer metal grid electrode pattern to face an evaporation source;
vacuumizing the vacuum coating machine, wherein the vacuum degree is less than 5E-3Pa;
performing a metal evaporation process on the bottom layer metal grid electrode pattern, wherein the evaporation rate is 0.1nm-10nm/s;
inflating the vacuum coating machine and taking out the epitaxial wafer;
placing the epitaxial wafer into the degumming solution to be soaked for 10-120 min;
taking out the epitaxial wafer and cleaning the epitaxial wafer by using a cotton ball or a water gun;
putting the epitaxial wafer into a clean photoresist removing liquid, ultrasonically cleaning for 1-2min, and then flushing for spin-drying;
putting the epitaxial wafer into a gluing machine table, and uniformly coating a layer of photoresist with the thickness of 500nm-3000 nm;
manufacturing a dielectric layer pattern on the photoresist;
putting the epitaxial wafer into a vacuum coating machine, and enabling one side of the dielectric layer pattern to face an evaporation source;
vacuumizing the vacuum coating machine, wherein the vacuum degree is less than 5E-3Pa;
performing a metal evaporation process on the dielectric layer pattern, wherein the evaporation rate is 0.1nm-10nm/s;
inflating the vacuum coating machine and taking out the epitaxial wafer;
putting the epitaxial wafer into acetone, ultrasonically cleaning for more than 5 minutes, and then flushing water for spin-drying;
putting the epitaxial wafer into a gluing machine table, and uniformly coating a layer of photoresist with the thickness of 500nm-3000 nm;
manufacturing a top metal grid electrode pattern on the photoresist;
putting the epitaxial wafer into a vacuum coating machine, and enabling one side of the top layer metal grid electrode pattern to face an evaporation source;
vacuumizing the vacuum coating machine, wherein the vacuum degree is less than 5E-3Pa;
performing a metal evaporation process on the top layer metal gate pattern, wherein the evaporation rate is 0.1nm-10nm/s;
inflating the vacuum coating machine and taking out the epitaxial wafer;
placing the epitaxial wafer into the degumming solution to be soaked for 10-120 min;
taking out the epitaxial wafer and cleaning the epitaxial wafer by using a cotton ball or a water gun;
and putting the epitaxial wafer into a clean photoresist removing liquid, ultrasonically cleaning for 1-2min, and then flushing for spin-drying.
The upper electrode of the thin film gallium arsenide solar cell and the preparation method thereof provided by the invention have the following advantages and positive effects:
(1) By using the local insulation type upper electrode structure, the short circuit phenomenon caused by local pressure of the battery can be effectively avoided, and the output efficiency of the battery is ensured;
(2) The oxide dielectric layer is used as an insulating structure, so that the insulating structure has the characteristics of high temperature resistance, good bonding force, strong insulating property and the like;
(3) The upper electrode is prepared by adopting the photoetching technology and the vacuum evaporation technology, and the method has the characteristics of simple process, mature technology and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a thin-film GaAs epitaxial wafer in an upper electrode of a thin-film GaAs solar cell according to the present invention;
FIG. 2 is a schematic structural diagram of a cross section of an upper electrode in the upper electrode of a thin film GaAs solar cell according to the present invention;
fig. 3 is a schematic top view of a bottom grid line of an upper electrode in an upper electrode of a thin film gaas solar cell according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
In the embodiments of the present application, as shown in fig. 1 to 3, the present invention provides a thin film gallium arsenide solar cell upper electrode, including: the epitaxial wafer comprises a bottom metal grid 3, a dielectric layer 4 and a top metal grid 5, wherein the bottom metal grid 3, the dielectric layer 4 and the top metal grid 5 are sequentially arranged on the outer surface of an epitaxial wafer 1 from inside to outside, and the bottom metal grid 3 is connected with the top metal grid 5.
In the embodiment of the present application, the size of the epitaxial wafer 1 is 2-6 feet, the metal used for the bottom metal gate 3 and the top metal gate 5 may be elemental metal such as Au, ag, cu, ge, ni, ti, al, or a combination of these metals, and the thickness of the bottom metal gate 3 and the top metal gate 5 is 1 micrometer-10 micrometers.
In the embodiment of the present application, the bottom metal gate 3 includes: the solar cell comprises a bottom layer main grid 7, bottom layer welding points 6 and bottom layer fine grids 8, wherein the bottom layer main grid 7 is arranged on the side edge of the solar cell, the bottom layer welding points 6 are arranged on the bottom layer main grid 7 at equal intervals, and the bottom layer fine grids 8 are uniformly arranged on the epitaxial wafer 1 and are perpendicular to the bottom layer main grid 7.
In the embodiment of the application, the width range of the bottom layer main grid 7 is 0.2mm-1mm, the length range of the bottom layer main grid 7 is 5mm-100mm, the width range of the bottom layer fine grid 8 is 0.005mm-0.1mm, the length range of the bottom layer fine grid 8 is 5mm-100mm, and the size range of the bottom layer welding spot 6 is 0.5mm × 0.5mm-5mm × 5mm.
In the embodiment of the present application, the top metal gate 5 includes: the top layer main grid is arranged on the side edge of the dielectric layer 4, the top layer welding points are arranged on the top layer main grid at equal intervals, and the top layer fine grid is uniformly arranged on the dielectric layer 4 and is perpendicular to the top layer main grid.
In the embodiment of the application, the width range of the top layer main grid is 0.2mm-1mm, the length range of the top layer main grid is 5mm-100mm, the width range of the top layer fine grid is 0.005mm-0.1mm, the length range of the top layer fine grid is 5mm-100mm, and the size range of the top layer welding spot is 0.5mm x 0.5mm-5mm x 5mm.
In the embodiment of the application, the epitaxial wafer 1 is a thin film gallium arsenide epitaxial wafer 1, and the outermost surface is an N-type gallium arsenide contact layer 2.
In the embodiment of the application, the dielectric film is SiOx, alOx, tiOx or SiNx.
In the embodiment of the application, the thickness of the dielectric film is 20nm-200nm.
In the embodiment of the present application, the dielectric layer 4 is a discrete and discontinuous pattern, and occupies 50% to 80% of the area of the bottom layer main grid 7 in the bottom layer metal grid 3, 100% of the area of the bottom layer welding spot 6 in the bottom layer metal grid 3, and 10% to 30% of the area of the bottom layer fine grid 8 in the bottom layer metal grid 3.
In an embodiment of the present application, the present invention further provides a method for manufacturing an upper electrode of a thin film gallium arsenide solar cell, where the upper electrode of the thin film gallium arsenide solar cell includes the upper electrode of the thin film gallium arsenide solar cell shown in fig. 1 to 3, and the method includes the steps of:
putting the epitaxial wafer 1 into acetone, ultrasonically cleaning for more than 5 minutes, and then flushing water for spin-drying;
putting the epitaxial wafer 1 into a gluing machine table, and uniformly coating a layer of photoresist with the thickness of 500nm-3000 nm;
making a bottom layer metal grid 3 pattern on the photoresist;
putting the epitaxial wafer 1 into a vacuum coating machine, and enabling one side of the bottom layer metal grid 3 graph to face an evaporation source;
vacuumizing the vacuum coating machine, wherein the vacuum degree is less than 5E-3Pa;
performing a metal evaporation process on the bottom metal grid 3 pattern, wherein the evaporation rate is 0.1nm-10nm/s;
inflating the vacuum coating machine and taking out the epitaxial wafer 1;
placing the epitaxial wafer 1 into the degumming solution to be soaked for 10-120 min;
taking out the epitaxial wafer 1 and cleaning the epitaxial wafer by using a cotton ball or a water gun;
putting the epitaxial wafer 1 into a clean photoresist removing liquid, ultrasonically cleaning for 1-2min, and then flushing for spin-drying;
putting the epitaxial wafer 1 into a gluing machine table, and uniformly coating a layer of photoresist with the thickness of 500nm-3000 nm;
manufacturing a dielectric layer 4 pattern on the photoresist;
placing the epitaxial wafer 1 into a vacuum coating machine and enabling one side of the medium layer 4 graph to face an evaporation source;
vacuumizing the vacuum coating machine, wherein the vacuum degree is less than 5E-3Pa;
performing a metal evaporation process on the dielectric layer 4 pattern, wherein the evaporation rate is 0.1nm-10nm/s;
inflating the vacuum coating machine and taking out the epitaxial wafer 1;
putting the epitaxial wafer 1 into acetone, ultrasonically cleaning for more than 5 minutes, and then flushing water for spin-drying;
putting the epitaxial wafer 1 into a gluing machine table, and uniformly coating a layer of photoresist with the thickness of 500nm-3000 nm;
manufacturing a top metal grid 5 pattern on the photoresist;
placing the epitaxial wafer 1 into a vacuum coating machine, and enabling one side of the top layer metal grid 5 graph to face an evaporation source;
vacuumizing the vacuum coating machine, wherein the vacuum degree is less than 5E-3Pa;
performing a metal evaporation process on the top layer metal grid 5 pattern, wherein the evaporation rate is 0.1nm-10nm/s;
inflating the vacuum coating machine and taking out the epitaxial wafer 1;
placing the epitaxial wafer 1 into a degumming solution for soaking for 10-120 min;
taking out the epitaxial wafer 1 and cleaning the epitaxial wafer by using a cotton ball or a water gun;
and putting the epitaxial wafer 1 into a clean photoresist removing solution, ultrasonically cleaning for 1-2min, and then flushing for spin-drying.
In the embodiment of the application, the adopted photoresist meets the Lift-off requirement.
In the embodiment of the application, the adopted degumming solution is an alkaline degumming solution, and the alkaline degumming solution cannot corrode the bottom layer metal grid and the top layer metal grid.
The upper electrode of the thin film gallium arsenide solar cell and the preparation method thereof provided by the invention have the following advantages and positive effects:
(1) By using the local insulation type upper electrode structure, the short circuit phenomenon caused by local pressure of the battery can be effectively avoided, and the output efficiency of the battery is ensured;
(2) The oxide dielectric layer is used as an insulating structure, so that the insulating structure has the characteristics of high temperature resistance, good bonding force, strong insulating property and the like;
(3) The upper electrode is prepared by adopting the photoetching technology and the vacuum evaporation technology, and the method has the characteristics of simple process, mature technology and the like.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modifications, equivalents, improvements and the like which are made without departing from the spirit and scope of the present invention shall be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (9)
1. A thin film gallium arsenide solar cell top electrode, comprising: the epitaxial wafer comprises a bottom metal grid, a dielectric layer and a top metal grid, wherein the bottom metal grid, the dielectric layer and the top metal grid are sequentially arranged on the outer surface of the epitaxial wafer from inside to outside, and the bottom metal grid is connected with the top metal grid;
the dielectric layer is in a discontinuous dispersed pattern, the area of the bottom layer main grid in the bottom layer metal grid is 50% -80%, the area of the bottom layer welding point in the bottom layer metal grid is 100%, and the area of the bottom layer fine grid in the bottom layer metal grid is 10% -30%.
2. The thin film gallium arsenide solar cell top electrode of claim 1 wherein said bottom layer metal grid comprises: the solar cell comprises a bottom layer main grid, bottom layer welding points and bottom layer fine grids, wherein the bottom layer main grid is arranged on the side edge of the solar cell, the bottom layer welding points are arranged on the bottom layer main grid at equal intervals, and the bottom layer fine grids are uniformly arranged on the epitaxial wafer and are perpendicular to the bottom layer main grid.
3. The upper electrode of thin film gallium arsenide solar cell as claimed in claim 2, wherein the width of the bottom layer main grid is in the range of 0.2mm-1mm, the length of the bottom layer main grid is in the range of 5mm-100mm, the width of the bottom layer fine grid is in the range of 0.005mm-0.1mm, the length of the bottom layer fine grid is in the range of 5mm-100mm, and the size of the bottom layer solder joint is in the range of 0.5mm x 0.5mm-5mm x 5mm.
4. The thin film gallium arsenide solar cell top electrode of claim 1 wherein said top metal gate comprises: the top layer main grid is arranged on the side edge of the dielectric layer, the top layer welding points are arranged on the top layer main grid at equal intervals, and the top layer fine grids are uniformly arranged on the dielectric layer and are perpendicular to the top layer main grid.
5. The upper electrode of thin film gallium arsenide solar cell as claimed in claim 4 wherein the width of the top layer main grid is in the range of 0.2mm to 1mm, the length of the top layer main grid is in the range of 5mm to 100mm, the width of the top layer fine grid is in the range of 0.005mm to 0.1mm, the length of the top layer fine grid is in the range of 5mm to 100mm, and the size of the top layer solder joint is in the range of 0.5mm x 0.5mm to 5mm x 5mm.
6. The thin film gallium arsenide solar cell top electrode of claim 1 wherein said epitaxial wafer is a thin film gallium arsenide epitaxial wafer and the outermost surface is an N-type gallium arsenide contact layer.
7. The upper electrode of a thin film gallium arsenide solar cell as claimed in claim 1, wherein said dielectric layer is SiOx, alOx, tiOx or SiNx.
8. The thin film gallium arsenide solar cell top electrode of claim 1 wherein the thickness of the dielectric layer is 20nm to 200nm.
9. A method for preparing a thin film gallium arsenide solar cell upper electrode, wherein the thin film gallium arsenide solar cell upper electrode comprises the thin film gallium arsenide solar cell upper electrode as claimed in any of claims 1-8, and the method comprises the steps of:
placing the epitaxial wafer into acetone, ultrasonically cleaning for more than 5 minutes, and then flushing water for spin-drying;
putting the epitaxial wafer into a gluing machine table, and uniformly coating a layer of photoresist with the thickness of 500nm-3000 nm;
making a bottom metal gate pattern on the photoresist;
placing the epitaxial wafer into a vacuum coating machine, and enabling one side of the bottom layer metal grid electrode pattern to face an evaporation source;
vacuumizing the vacuum coating machine, wherein the vacuum degree is less than 5E-3Pa;
performing a metal evaporation process on the bottom layer metal grid electrode pattern, wherein the evaporation rate is 0.1nm-10nm/s;
inflating the vacuum coating machine and taking out the epitaxial wafer;
placing the epitaxial wafer into the degumming solution to be soaked for 10-120 min;
taking out the epitaxial wafer and cleaning the epitaxial wafer by using a cotton ball or a water gun;
putting the epitaxial wafer into a clean photoresist removing liquid, ultrasonically cleaning for 1-2min, and then flushing for spin-drying;
putting the epitaxial wafer into a gluing machine table, and uniformly coating a layer of photoresist with the thickness of 500nm-3000 nm;
manufacturing a dielectric layer pattern on the photoresist;
placing the epitaxial wafer into a vacuum coating machine and enabling one side of the dielectric layer graph to face an evaporation source;
vacuumizing the vacuum coating machine, wherein the vacuum degree is less than 5E-3Pa;
performing a metal evaporation process on the dielectric layer pattern, wherein the evaporation rate is 0.1nm-10nm/s;
inflating the vacuum coating machine and taking out the epitaxial wafer;
putting the epitaxial wafer into acetone, ultrasonically cleaning for more than 5 minutes, and then flushing water for spin-drying;
putting the epitaxial wafer into a gluing machine table, and uniformly coating a layer of photoresist with the thickness of 500nm-3000 nm;
manufacturing a top metal grid electrode pattern on the photoresist;
putting the epitaxial wafer into a vacuum coating machine, and enabling one side of the top layer metal grid electrode pattern to face an evaporation source;
vacuumizing the vacuum coating machine, wherein the vacuum degree is less than 5E-3Pa;
performing a metal evaporation process on the top layer metal gate pattern, wherein the evaporation rate is 0.1nm-10nm/s;
inflating the vacuum coating machine and taking out the epitaxial wafer;
placing the epitaxial wafer into a degumming solution to be soaked for 10-120 min;
taking out the epitaxial wafer and cleaning the epitaxial wafer by using a cotton ball or a water gun;
and putting the epitaxial wafer into a clean photoresist removing liquid, ultrasonically cleaning for 1-2min, and then flushing for spin-drying.
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