CN112750910A - Integrated chip - Google Patents

Integrated chip Download PDF

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Publication number
CN112750910A
CN112750910A CN202011187561.9A CN202011187561A CN112750910A CN 112750910 A CN112750910 A CN 112750910A CN 202011187561 A CN202011187561 A CN 202011187561A CN 112750910 A CN112750910 A CN 112750910A
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China
Prior art keywords
layer
nanosheet channel
gate
channel structure
ring
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Pending
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CN202011187561.9A
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Chinese (zh)
Inventor
徐崇威
江国诚
朱龙琨
黄懋霖
余佳霓
王志豪
程冠伦
蔡庆威
陈豪育
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/819,632 external-priority patent/US11502168B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112750910A publication Critical patent/CN112750910A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

In some embodiments, the present disclosure relates to an integrated chip comprising a first nanosheet field effect transistor (NSFET). The first NSFET includes: the first nanosheet channel structure is arranged on the substrate; a second nanosheet channel structure directly arranged on the first nanosheet channel structure; and a first gate structure. The first nanosheet channel structure and the second nanosheet channel structure extend in parallel between the first and second source/drain regions. The first gate structure includes a first conductive ring and a second conductive ring respectively completely surrounding a plurality of outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, and the first gate structure includes a first material. The first gate structure also includes a passivation layer completely surrounding the first and second conductive rings, and disposed directly between the first and second nanosheet channel structures, and including a second material different from the first material.

Description

Integrated chip
Technical Field
Embodiments of the present invention relate to integrated chips, and more particularly, to an integrated chip including a passivation layer.
Background
The semiconductor industry continues to improve the integration density of various electronic devices (e.g., transistors, diodes, resistors, capacitors, etc.) by, for example, reducing the minimum feature size and/or arranging the electronic devices more recently with respect to one another, allowing more components to be integrated into a given area. For example, a nanosheet field effect transistor (NSFET) includes a vertically aligned nanosheet channel structure, with a plurality of gates surrounding each nanosheet channel structure to reduce device area and increase device control.
Disclosure of Invention
An integrated chip, comprising: a first nanosheet field effect transistor, comprising: the first nanosheet channel structure is arranged on the substrate; the second nano-sheet channel structure is directly arranged on the first nano-sheet channel structure and extends from the first source electrode/drain electrode region to the second source electrode/drain electrode region in parallel; and a first gate structure comprising: the nano-film structure comprises a first conducting ring, a second conducting ring and a passivation layer, wherein the first conducting ring comprises a first material and completely surrounds a plurality of outer side walls of a first nano-film channel structure, the second conducting ring comprises a first material and completely surrounds a plurality of outer side walls of a second nano-film channel structure, the passivation layer completely surrounds the first conducting ring and the second conducting ring, the first conducting ring and the second conducting ring are directly arranged between the first nano-film channel structure and the second nano-film channel structure, and the first conducting ring and the second conducting ring comprise a second material different from.
An integrated chip, comprising: a first nanosheet field effect transistor (NSFET) comprising: a first source/drain region and a second source/drain region having a first doping type and arranged on the substrate; a first nanosheet channel structure and a second nanosheet channel structure arranged on the substrate and extending in parallel between the first and second source/drain regions, wherein the second nanosheet channel structure is directly arranged on the first nanosheet channel structure; a first gate structure comprising: a first conducting ring completely surrounding the first nanosheet channel structure, and a second conducting ring completely surrounding the second nanosheet channel structure; and a second NSFET arranged laterally next to the first NSFET, and including: a third source/drain region and a fourth source/drain region having a second doping type different from the first doping type and arranged on the substrate; a third nanosheet channel structure and a fourth nanosheet channel structure arranged on the substrate and extending in parallel between the third and fourth source/drain regions, wherein the fourth nanosheet channel structure is directly arranged on the third nanosheet channel structure; and a second gate structure comprising: a third conductive ring completely surrounding the third nanosheet channel structure, a fourth conductive ring completely surrounding the fourth nanosheet channel structure, and a passivation layer surrounding the third and fourth conductive rings and directly separating the third conductive ring from the fourth conductive ring.
A method of forming an integrated chip, comprising: forming a first nanosheet channel structure and a second nanosheet channel structure on the substrate, and extending in parallel between the first source/drain region and the second source/drain region, wherein the second nanosheet channel structure is directly arranged on the first nanosheet channel structure; forming a first dielectric ring and a second dielectric ring respectively covering a plurality of outer surfaces of the first nanosheet channel structure and the second nanosheet channel structure; performing a first Atomic Layer Deposition (ALD) process to form a first conductive layer on the substrate, including a first conductive ring on the first dielectric ring and a second conductive ring on the second dielectric ring; and performing a second ALD process to form a passivation layer on the first and second conductive rings, wherein the passivation layer separates the first and second conductive rings.
Drawings
The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.
Fig. 1A-1C illustrate various views of some embodiments of a first nanosheet field effect transistor (NSFET) having a first gate structure comprising a passivation layer comprising silicon and arranged on a first conductive layer comprising titanium nitride (titanium nitride).
Figure 1D illustrates a graph of some embodiments of work function of a first gate structure including a first conductive layer versus thickness of the first conductive layer including titanium nitride.
Fig. 2A and 2B illustrate various views of some embodiments of a first NSFET having a first gate structure laterally arranged next to a second NSFET having a second gate structure different from the first gate structure.
FIG. 3 illustrates a cross-sectional view of some additional embodiments of a first NSFET laterally beside a second NSFET and coupled to a contact hole.
Fig. 4-13, 14A, 14B, 15-26 illustrate various views of some embodiments of a method of forming a first NSFET having a first gate structure including a first conductive layer and a passivation layer, and using a dummy mask structure to form a second NSFET laterally arranged beside the first NSFET and having a second gate structure different from the first gate structure.
Fig. 27 illustrates a flow diagram corresponding to some embodiments of the methods of fig. 4-13, 14A, 14B, 15-26.
Wherein the reference numerals are as follows:
100A, 200A, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400A: perspective view of
100B, 100C, 200B, 300, 1400B, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600: sectional view of
100D: graph table
101: first NSFET
102: substrate
104: first fin structure
106 a: lower isolation structure
106 b: upper isolation structure
108: first source/drain region
110: second source/drain region
112: first grid structure
114: first gate layer
116: adhesive layer
118a, 118b, 118c, 118d, 218a, 218b, 218c, 218 d: nanosheet channel structure
120: interfacial layer
120a, 120b, 120c, 120d, 220a, 220b, 220c, 220 d: interface ring
122: dielectric layer
122a, 122b, 122c, 122d, 222a, 222b, 222c, 222 d: dielectric ring
124: first conductive layer
124a, 124b, 124c, 124d, 224a, 224b, 224c, 224 d: conducting ring
126: passivation layer
126a, 126b, 126c, 126 d: passivation ring
130: vacuum energy level
132: conduction band energy level
134: valence band energy level
136: first drawing line
138: second drawing line
201: second NSFET
204: second fin structure
208: third source/drain region
210: fourth source/drain region
212: second grid structure
214: second gate layer
224: second conductive layer
302: contact hole
304: interface (I)
501: semiconductor layer stack
502: spacer layer
506: semiconductor layer
601: first semiconductor layer stack
602: patterned spacer layer
603: second semiconductor layer stack
610: first mask structure
612: second mask structure
802: virtual interface layer
804: virtual grid structure
806: third mask structure
902: gate spacer
1402: universal layer
1602: virtual mask layer
1702: dummy mask structure
1802: fourth mask structure
2102: fifth mask structure
2700: flow chart
2702, 2704, 2706, 2708, 2710, 2712, 2714, 2716, 2718: movement of
BB ', CC': section line
t1: first thicknessDegree of rotation
t2: second thickness
t3: third thickness
t4: a fourth thickness
t5: a fifth thickness
t6: a sixth thickness
d1: first distance
d2: second distance
d3: third distance
d4: a fourth distance
d5: a fifth distance
VG: grid voltage
VSD1: first source/drain voltage
VSD2: second source/drain voltage
w1: first width
w2: second width
Detailed Description
The following disclosure provides many embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the embodiments of the invention. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as "under", "below", "over", "upper", and the like, are used for ease of describing the relationship of one element of the present disclosure to another. Spatially relative terms are intended to encompass different orientations of the device in which the element is incorporated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.
In some embodiments, a nanosheet field effect transistor (nset) can include a nanosheet channel structure extending in parallel from a first source/drain region to a second source/drain region. The nanosheet channel structure may be surrounded continuously by one or more gate layers forming the gate structure. Thus, the nanosheet channel structure can be "turned on" to allow mobile charge carriers (mobile charge carriers) to be transferred from the first source/drain region to the second source/drain region by applying a bias voltage to the gate structure that exceeds the threshold voltage of the NSFET.
The threshold voltage of an NSFET is at least dependent on the work function of the gate structure, which is at least controllable by the thickness and composition of the gate layer of the gate structure. For example, a gate structure of an n-nsefet, in which electrons are mobile charge carriers, may comprise a first gate layer comprising aluminum (aluminum) that continuously surrounds the nanosheet channel structure. The work function of the gate structure including aluminum is closer to the conduction band energy levels of the first and second channel structures than to the valence band energy levels of the nanosheet channel structure, and the threshold voltage may be lowered to turn "on" the n-NSFET.
However, due to the precursor reaction for the formation and/or composition of the first gate layer, the portion of the first gate material disposed directly between the nanosheet channel structures may include an aluminum concentration of about 10 percent, or greater than the aluminum concentration of the portion of the first gate layer disposed on the outer surface of the nanosheet channel structures. Also, the aluminum in the first gate layer may diffuse into other layers of the gate structure, causing more unpredictability and/or variation in aluminum concentration. In such embodiments, the work function of the gate structure, and therefore the threshold voltage of the NSFET, may vary because the gate structure does not have a uniform composition, thereby reducing the performance of the NSFET.
Various embodiments of the present disclosure are directed to a method of forming a first NSFET having a first gate structure that is substantially uniform in composition and, thus, substantially uniform in first work function. The first gate structure may include a first conductive layer including titanium nitride (tin nitride) instead of aluminum, and the first conductive layer may be formed by a first Atomic Layer Deposition (ALD) process to control the thickness and composition of the titanium nitride of the first conductive layer. In such embodiments, the concentration of titanium (titanium) may vary by less than 1 percent throughout the first conductive layer, and the concentration of nitrogen (nitrogen) may vary by less than 1 percent throughout the first conductive layer. In addition, in some embodiments, a second ALD process may be performed to form a passivation layer, which includes silicon (silicon) and does not include aluminum, arranged on the first conductive layer, and arranged between the nanosheet channel structures to push the first work function of the first gate structure closer to its conduction band than to the valence band of the nanosheet channel structure. As a result, in such embodiments, the first NSFET may be a reliable n-NSFET having a substantially uniform first threshold voltage.
In addition, various embodiments of the present disclosure are also directed to a method of forming a second NSFET (e.g., a p-NSFET) laterally next to a first NSFET (e.g., an n-NSFET). In some embodiments, the second NSFET may include a second gate structure that is different (e.g., composition of the film layers, thickness of the film layers, number of film layers, etc.) from the first gate structure such that the second gate structure has a second work function that is different from the first work function. In such an embodiment, the dummy mask structure may be formed directly between the nanosheet channel structures of the second nset, and then, a first conductive layer and a passivation layer may be formed on the nanosheet channel structures of the first and second nsets. The dummy mask structure reduces the maximum dimensions of the first conductive layer and the passivation layer to be removed, which are directly arranged between the nanosheet channel structures of the second NSFET, to avoid over-etching (over-etching) of the first gate structure by an unintentional (inadvertent) process of selectively removing the first conductive layer and the passivation layer from the nanosheet channel structures of the second NSFET. Thus, due to the dummy mask structure, the second NSFET can be formed laterally next to the first NSFET to increase device density without sacrificing reliability of the first gate structure.
Fig. 1A shows a perspective view 100A of some embodiments of a first nanosheet field effect transistor (NSFET) having a first gate structure including a passivation layer comprising silicon and located on a first conductive layer comprising titanium nitride.
The perspective view 100A shows a first NSFET101 comprising a substrate 102 including a first fin structure 104. The first fin structures 104 protrude from the substrate 102 through the lower isolation structures 106 a. The first source/drain regions 108 are arranged on a first side of the first fin structures 104 and the second source/drain regions 110 are arranged on a second side of the first fin structures 104. The first gate structure 112 is arranged directly on the first fin structure 104, and the nanosheet channel structure (see 118a-c of fig. 1B) is embedded within the first gate structure 112. The nanosheet channel structure (see 118a-c of fig. 1B) extends from the first source/drain region 108 to the second source/drain region 110. In some embodiments, the first source/drain region 108 and the second source/drain region 110 are covered by the upper isolation structure 106 b. The second source/drain region 110 is shown with dashed lines because, in some embodiments, the second source/drain region 110 is not visible from the perspective view 110A of fig. 1A. In some embodiments, the adhesion layer 116 may surround the first gate structure 112. It should be understood that the adhesion layer 116 is shown as being somewhat transparent such that the first gate structure 112 may be visible in fig. 1A, and thus, in some embodiments, the adhesion layer 116 is not transparent, or is not somewhat transparent.
In some embodiments, the first and second source/ drain regions 108, 110 have a first doping type (e.g., n-type), and the substrate 102, the first fin structures 104, and the nanosheet channel structure (see 118a-c of fig. 1B) are intrinsic semiconductor (intrinsic semiconductor) materials. Thus, the first NSFET101 may be an n-NSFET, in that when a voltage greater than the first threshold voltage is applied to the first gate structure 112, electrons will be mobile charge carriers that flow from the first source/drain region 108 to the second source/drain region 110 through the nanosheet channel structure (see 118a-c of FIG. 1B) surrounded by the first gate structure 112. The first threshold voltage of the first NSFET101 may depend on the first work function of the first gate structure 112. The first gate structure 112 may include a plurality of gate layers 114, as described in more detail in fig. 1B, which plurality of gate layers 114 may affect a first work function of the first gate structure 112.
Further, it will be understood that in some instances, the first NSFET101 may also be referred to as, for example, a gate-all-around FET (gate-all-around FET), a gate-surrounding transistor (gate-surrounding transistor), a multi-bridge channel (MBC) transistor, a nanowire FET, and the like.
Fig. 1B illustrates a cross-sectional view 100B of some embodiments of the first NSFET101, which may correspond to the section line BB' of fig. 1A.
As shown in fig. 1B, in some embodiments, the first NSFET101 includes a first nanosheet channel structure 118a arranged directly on the first fin structure 104, a second nanosheet channel structure 118B arranged directly on the first nanosheet channel structure 118a, and a third nanosheet channel structure 118c arranged directly on the second nanosheet channel structure 118B. Furthermore, in some embodiments, the first fin structures 104 and the first through third nanosheet channel structures 118a-c comprise the same semiconductor material. For example, in some embodiments, the first fin structures 104 and the first through third nanosheet channel structures 118a-c can comprise intrinsic (inrinsic) silicon. In addition, the first fin structure and the first through third nanosheet channel structures 118a-c are spaced from one another by the first gate structure 112.
In some embodiments, the first gate structure 112 includes a plurality of first gate layers 114, and the first gate layers 114 may include the following: an interfacial layer 120, a gate dielectric layer 122, a first conductive layer 124, and a passivation layer 126. In some embodiments, a plurality of first gate layers 114 are arranged on the lower isolation structure 106a and also continuously surround the first through third nanosheet channel structures 118 a-c. For example, in some embodiments, the interface layer 120 can include a first interface ring 120a, a second interface ring 120b, and a third interface ring 120c that directly contact and continuously surround the first nanosheet channel structure 118a, the second nanosheet channel structure 118b, and the third nanosheet channel structure 118 c. In some embodiments, the interfacial layer 120 is also arranged on the lower isolation structures 106a and on the first fin structures 104. In some embodiments, the gate dielectric layer 122 may include a first dielectric ring 122a, a second dielectric ring 122b, and a third dielectric ring 122c arranged on the first interface ring 120a, the second interface ring 120b, and the third interface ring 120c, respectively, and continuously surrounding the first interface ring 120a, the second interface ring 120b, and the third interface ring 120c, respectively. In some embodiments, the first conductive layer 124 may include a first conductive ring 124a, a second conductive ring 124b, and a third conductive ring 124c, which are respectively arranged on the first dielectric ring 122a, the second dielectric ring 122b, and the third dielectric ring 122c and respectively continuously surround the first dielectric ring 122a, the second dielectric ring 122b, and the third dielectric ring 122 c. In some embodiments, the passivation layer 126 may include a first passivation ring 126a, a second passivation ring 126b, and a third passivation ring 126c arranged on the first conductive ring 124a, the second conductive ring 124b, and the third conductive ring 124c, respectively, and continuously surrounding the first conductive ring 124a, the second conductive ring 124b, and the third conductive ring 124c, respectively.
In some embodiments, the second passivation ring 126b directly contacts the first passivation ring 126a and the third passivation ring 126 c. Furthermore, in some embodiments, the second conductive ring 124b is completely separated from the first and third conductive rings 124a and 124c by the passivation layer 126. Thus, the passivation layer 126 is arranged directly between the first fin structure 104 and the first nanosheet channel structure 118a, directly between the first nanosheet channel structure 118a and the second nanosheet channel structure 118b, and directly between the second nanosheet channel structure 118b and the third nanosheet channel structure 118 c.
In some embodiments, the first work function of the first gate structure 112 is at least dependent on the materials and thicknesses of the first conductive layer 124 and the passivation layer 126. In some embodiments, first conductive layer 124 comprises titanium nitride and has a first thickness t in a range between, for example, about 8 angstroms and about 50 angstroms1. In some embodiments, the first thickness t of the first conductive layer 1241Can be at firstThe entire portion of conductive layer 124 is substantially constant. In such embodiments, the first conductive layer 124 may have a minimum concentration of titanium and a maximum concentration of titanium. The difference between the maximum concentration of titanium and the minimum concentration of titanium may be less than or equal to about 1 percent. Similarly, in such embodiments, the first conductive layer 124 may have a minimum concentration of nitrogen and a maximum concentration of nitrogen. The difference between the maximum concentration of nitrogen and the minimum concentration of nitrogen may be less than or equal to about 1 percent. Thus, the first conductive layer 124 may be formed to have a composition (e.g., titanium nitride) with substantially low variation throughout the first conductive layer 124 and a first thickness t1Thereby reducing the variation in the first work function of the first gate structure 112. For example, in some embodiments, the first conductive layer 124 may be formed by an Atomic Layer Deposition (ALD) process.
Further, in some embodiments, passivation layer 126 comprises silicon and has a second thickness t, for example, in a range between about 10 angstroms and about 20 angstroms2. In some embodiments, the silicon in the passivation layer 126 may lower the first work function of the first gate structure 112. The first work function of the first gate structure 112 may increase or decrease depending on the first thickness t of the first conductive layer 1241And a second thickness t of the passivation layer2Thereby increasing or decreasing the first threshold voltage of the first NSFET 101.
In some embodiments, the first thickness t1And a second thickness t2Will be a first distance d1Limit, first distance d1The second dielectric ring 122b is separated from the first dielectric ring 122a and the second dielectric ring 122b is separated from the third dielectric ring 122 c. In some embodiments, the first distance d1May range between, for example, about 4 nanometers and about 6 nanometers. In some embodiments, the first distance d1Can be increased by increasing the spacing between the first through third nanosheet channel structures 118 a-c. However, increasing the spacing between the first through third nanosheet channel structures 118a-c increases the size of the first NSFET101, which is undesirable because the electronic devices continue to decrease.
Thus, for forming the first conductive layer 124 and passivationThe process of forming layer 126 may transition to the following first distance d1And a first and a second thickness t1、t2The relationship between: d1＝t2+2t1. For example, in some embodiments, d1May be equal to 5 nanometers. In some such embodiments, the first thickness t of the first conductive layer 1241May be equal to about 2 nanometers and the second thickness t of the passivation layer 1262May be equal to about 1 nanometer. In other embodiments, the first distance d1And a first and a second thickness t1、t2The relationship between may be as follows: d1＝2t2+2t1. If the first thickness t1Too large for the passivation layer 126 to form directly between the second nanosheet channel structure 118b and the first or third nanosheet channel structures 118a, 118c, the work function of the first gate structure 112 varies, and thus the first threshold voltage of the first NSFET also varies and cannot be expected. Thus, in some embodiments, the first conductive layer 124 and the passivation layer 126 may be deposited by an Atomic Layer Deposition (ALD) process for controlling the first and second thicknesses t1、t2. In some embodiments, to prevent oxidation on the first conductive layer 124, and thus maximize the second thickness t2The deposition of the first conductive layer 124 is performed in-situ (in-situ) with the deposition of the passivation layer 126. In such an embodiment, in-situ means that the substrate (102 of fig. 1A) is not removed from the host (mainframe) structure while forming the first conductive layer 124 and the passivation layer 126, such that there is no vacuum break between the formation of the first conductive layer 124 and the formation of the passivation layer 126.
Fig. 1C illustrates a cross-sectional view 100C of some embodiments of the first NSFET101, which may correspond to section line CC of fig. 1A.
As shown in fig. 1C, in some embodiments, the first, second, and third nanosheet channel structures 118a, 118b, 118C extend in parallel from the first source/drain region 108 to the second source/drain region 110. In addition, the first, second, and third nanosheet channel structures 118a, 118b, 118c directly contact the first source/drain region 108 and the second source/drain region 110. In some embodiments, during the formation of the plurality of first gate layers 114, the plurality of first gate layers 114 are formed on the first fin structures 104, the first to third nanosheet channel structures 118a-c, the first source/drain region 108, and the second source/drain region 110. Therefore, in some embodiments, from the cross-sectional view 100C, some of the plurality of first gate layers 114, such as the interface layer 120, the gate dielectric layer 122, and the first conductive layer 124, may have a rectangular ring shape. In other embodiments, the plurality of first gate layers 114 may appear more oval or more circular from the cross-sectional view 100C of fig. 1C.
The gate voltage V may be adjusted while operating the first NSFET101GApplied to the adhesion layer 116, a first source/drain voltage V may be appliedSD1Is applied to the first source/drain region 108, and a second source/drain voltage V may be appliedSD2To the second source/drain region 110. In some embodiments, when the gate voltage V is appliedGExceeds the absolute value of the first threshold voltage of the first NSFET101, the first NSFET101 is turned "on" such that mobile charge carriers (e.g., electrons) are transferred between the first source/drain region 108 and the second source/drain region 110. In some embodiments, contact holes couple adhesive layer 116, first source/drain region 108, and second source/drain region 110 to a gate voltage source, a first source/drain voltage source, and a second source/drain voltage source, respectively. In some embodiments, the adhesion layer 116 comprises a conductive material such as, for example, titanium nitride (tin nitride), tantalum nitride (tan al nitride), and the like. Thus, the adhesion layer 116 may be electrically coupled to the first gate structure 112. Because of the substantially constant composition and thickness of the plurality of first gate layers 114 of the first gate structure 112, the first threshold voltage of the first NSFET101 may also be substantially constant. Therefore, when the gate voltage V is appliedGThe first through third nanosheet channel structures 118a-c can be simultaneously and reliably "turned on" in excess of the first threshold voltage of the first NSFET 101.
FIG. 1D illustrates work function versus first thickness (t of FIG. 1B) of a first conductive layer (124 of FIG. 1B) comprising titanium nitride1) Graph 100D of (a).
As shown in FIG. 1D, a first scribe line 136 is shown in the passivation layer (of FIG. 1B126) Second thickness (t of fig. 1B)2) Zero in some embodiments of the first gate structure (112 of fig. 1B) has a first work function versus a first thickness (t of fig. 1B) of the first conductive layer (124 of fig. 1B)1). In other words, the first scribe line 136 shows a first work function of the first gate structure (112 of fig. 1B) when the first gate structure (112 of fig. 1B) contains a first conductive layer (124 of fig. 1B) comprising titanium nitride and does not contain a passivation layer (126 of fig. 1B). Thus, when the first thickness (t of FIG. 1B) of the first conductive layer (124 of FIG. 1B)1) As an increase, the first work function of the first gate structure (112 of fig. 1B) comprising titanium nitride instead of silicon may increase. A second scribe line 138 shows how the first work function of the first gate structure (112 of fig. 1B) changes when the first gate structure (112 of fig. 1B) contains a first conductive layer (124 of fig. 1B) comprising titanium nitride and a passivation layer (126 of fig. 1B) comprising silicon. The first gate structure (112 of fig. 1B), represented by the second drawn line 138, may have a second thickness (t 2 of fig. 1B) of the passivation layer (126 of fig. 1B) that is greater than zero and constant, while the first thickness (t of fig. 1B)1) To collect work function data for the second scribe line 138. The graph 100D shows that in some embodiments, because the second draw line 138 has a greater slope than the first draw line 136, the presence of the passivation layer (126 of fig. 1B) comprising silicon increases the ability to vary the first work function of the first gate structure (112 of fig. 1B).
Additionally, the graph 100D of FIG. 1D illustrates a first thickness saturation value 140 defined by the intersection of the second trace 138 with the first trace 136. The passivation layer (126 of fig. 1B) reduces the first work function of the first gate structure (112 of fig. 1B) prior to the first thickness saturation value 140 of the first conductive layer (124 of fig. 1B). However, after the first thickness saturation value 140 of the first conductive layer (124 of fig. 1B), the presence of silicon of the passivation layer (126 of fig. 1B) may not affect the first work function of the first gate structure (112 of fig. 1B). In some embodiments, the second scribes 138 may be at a first thickness (t of FIG. 1B)1) Increasing from about 8 angstroms to about 50 angstroms represents a first workfunction data. Thus, in some embodiments, first thickness saturation value 140 may be, for example, in a range between about 45 angstroms and about 55 angstroms.
Further, the vacuum level 130, conduction band level 132, and valence band level 134 of the first through third nanosheet channel structures (118 a-c of fig. 1B) are shown on the graph 100D. Thus, when the first thickness (t 1 of fig. 1B) of the first conductive layer (124 of fig. 1B) comprising titanium nitride is low and when the first gate structure (112 of fig. 1B) comprises the passivation layer (126 of fig. 1B), the first gate structure (112 of fig. 1B) has a first work function that is closest to the conduction band energy level 132 of the first through third nanosheet channel structures (118 a-c of fig. 1B). When the first NSFET (101 of FIG. 1B) is an n-type NSFET, the first work function near the conduction band energy level 132 lowers the first threshold voltage of the first NSFET (101 of FIG. 1B). In other embodiments, a higher threshold voltage for the first NSFET (101 of FIG. 1B) may be required, and thus, the first thickness (t of FIG. 1B) of the first conductive layer (124 of FIG. 1B) may be increased1). Thus, in some embodiments, a first thickness (t of fig. 1B) of a first conductive layer (124 of fig. 1B) comprising titanium nitride may be adjusted1) To adjust the first work function of the first gate structure (112 of fig. 1B) and, therefore, adjust the first threshold voltage of the first NSFET (101 of fig. 1B).
Fig. 2A illustrates a perspective view 200A of some embodiments of a first NSFET laterally arranged next to a second NSFET, wherein a first gate structure of the first NSFET has a different work function than a second gate structure of the second NSFET.
The perspective view 200A shows a second NSFET201 laterally arranged next to the first NSFET 101. In some embodiments, the second NSFET201 may include a second fin structure 204 protruding from the substrate 102. In some embodiments, the second fin structures 204 comprise an intrinsic semiconductor material, protrude from the substrate 102 and through the lower isolation structures 106a, and are separated from the first fin structures 104 by the lower isolation structures 106 a. In some embodiments, the second NSFET201 includes a third source/drain region 208 arranged on a first side of the second fin structure 204 and a fourth source/drain region 210 arranged on a second side of the second fin structure 204. The second gate structure 212 is arranged directly on the second fin structure 204, and the nanosheet channel structure of the second NSFET201 (see 218a-c of fig. 2B) is embedded within the second gate structure 212. The nanosheet channel structure (see 218a-c) of the second NSFET201 extends from the third source/drain region 208 to the fourth source/drain region 210. In some embodiments, the third source drain region 208 and the fourth source/drain region 210 are covered by the upper isolation structure 106 b. In addition, the adhesion layer 116 may surround the first and second gate structures 112, 212.
In such an embodiment, the first gate structure 112 may have a first work function that affects a first threshold voltage of the first NSFET101, and the second gate structure 212 may have a second work function that affects a second threshold voltage of the second NSFET 201. The first work function may be different from the second work function, and thus, in some embodiments, the first gate structure 112 may have a different structure (e.g., composition of the film layers, thickness of the film layers, number of film layers, etc.) than the second gate structure 212. In some embodiments, for example, the third source drain region 208 and the fourth source/drain region 210 have a second doping type (e.g., p-type), while the first source/drain region 108 and the second source/drain region 110 have a first doping type (e.g., n-type) that is different from the second doping type (e.g., p-type). In such an embodiment, when the first NSFET101 is "on," the mobile charge carriers of the first NSFET101 may be electrons, and when the second NSFET201 is "on," the mobile charge carriers of the second NSFET201 may be holes. In such an embodiment, the first NSFET101 may be an n-type NSFET, and the second NSFET201 may be a p-type NSFET. In other embodiments, the first and second source/ drain regions 108, 110 and the third and fourth source/ drain regions 208, 210 may have the same doping type, and the first and second NSFETs 101, 201 have different threshold voltages due to different structures, and thus result in different work functions of the first and second gate structures 112, 212. In some embodiments, the first gate structure 112 may include a plurality of first gate layers 114 and the second gate structure 212 may include a plurality of second gate layers 214. As described in more detail in fig. 2B, the plurality of first gate layers 114 and the plurality of second gate layers 214 may have the same point and different points.
Fig. 2B illustrates a cross-sectional view 200B of some embodiments of the first NSFET101 laterally arranged next to the second NSFET201, which may correspond to the section line BB' of fig. 2A.
As shown in fig. 2B, in some embodiments, the second NSFET201 includes a fourth nanosheet channel structure 218a arranged directly over the second fin structure 204, a fifth nanosheet channel structure 218B arranged directly over the fourth nanosheet channel structure 218a, and a sixth nanosheet channel structure 218c arranged directly over the fifth nanosheet channel structure 218B. The second fin structure 204 and the fourth-sixth nanosheet channel structures 218a-c are spaced from one another by the second gate structure 212. In some embodiments, a fourth nanosheet channel structure 218a, a fifth nanosheet channel structure 218b, and a sixth nanosheet channel structure 218c are laterally disposed alongside the first nanosheet channel structure 118a, the second nanosheet channel structure 118b, and the third nanosheet channel structure 118c, respectively. Further, in some embodiments, the first through third nanosheet channel structures 118a-c, the fourth through sixth nanosheet channel structures 218a-c, the first fin structures 104, and the second fin structures 204 comprise the same semiconductor material, such as, for example, intrinsic silicon. In other embodiments, the same semiconductor material may be doped silicon or some other suitable semiconductor material.
In some embodiments, the second gate structure 212 includes a plurality of second gate layers 214, which may include the following: an interfacial layer 120, a gate dielectric layer 122, and a second conductive layer 224. For example, in some embodiments, the interface layer 120 may further include: a fourth interface ring 220a, a fifth interface ring 220b, and a sixth interface ring 220c, which directly contact and continuously surround the fourth nanosheet channel structure 218a, the fifth nanosheet channel structure 218b, and the sixth nanosheet channel structure 218c, respectively. In some embodiments, the interface layer 120 is also arranged on the second fin structures 204. In some embodiments, the gate dielectric layer 122 may include a fourth dielectric ring 222a, a fifth dielectric ring 222b, and a sixth dielectric ring 222c, which are respectively arranged on the fourth interface ring 220a, the fifth interface ring 220b, and the sixth interface ring 220c, and respectively continuously surround the fourth interface ring 220a, the fifth interface ring 220b, and the sixth interface ring 220 c. In some embodiments, the second conductive layer 224 may include a fourth conductive ring 224a, a fifth conductive ring 224b, and a sixth conductive ring 224c, which are respectively arranged on the fourth dielectric ring 222a, the fifth dielectric ring 222b, and the sixth dielectric ring 222c, and respectively continuously surround the fourth dielectric ring 222a, the fifth dielectric ring 222b, and the sixth dielectric ring 222 c. In some embodiments, the fifth conductive ring 224b directly contacts the fourth conductive ring 224a and the sixth conductive ring 224 c. Thus, the second conductive layer 224 is directly arranged between the second fin structure 204 and the fourth nanosheet channel structure 218a, between the fourth nanosheet channel structure 218a and the fifth nanosheet channel structure 218b, and between the fifth nanosheet channel structure 218b and the sixth nanosheet channel structure 218 c.
In some embodiments, the second conductive layer 224 can also be arranged on the first through third nanosheet channel structures 118 a-c. Because the second gate structure 212 includes the second conductive layer 224 but does not include the first conductive layer 124 or the passivation layer 126, the second gate structure 212 may have a second work function that is different from the first work function of the first gate structure 112. In some embodiments, for example, the first work function of the first gate structure 112 may be less than the second work function of the second gate structure 212. In such an embodiment, the first NSFET101 may be an n-type NSFET, and the second NSFET201 may be a p-type NSFET.
In some embodiments, dummy mask structures (see, e.g., 1702 of fig. 17) may be formed directly between the second fin structure 204 and the fourth nanosheet channel structure 218a, between the fourth nanosheet channel structure 218a and the fifth nanosheet channel structure 218b, and between the fifth nanosheet channel structure 218b and the sixth nanosheet channel structure 218c upon formation of the first and second gate structures 112, 212. The dummy mask structure (see, e.g., 1702 of fig. 17) reduces the maximum dimensions of the first conductive layer 124 and the passivation layer 126 to be removed, which are arranged directly between the fourth through sixth nanosheet channel structures 218a-c, to avoid inadvertent over-etching of the first gate structure 112 when selectively removing the first conductive layer 124 and the passivation layer 126 from the fourth through sixth nanosheet channel structures 218 a-c. Thus, in some embodiments, the second NSFET201 and the first NSFET101 may be formed on the same structure (102 of fig. 2A), and may have different work functions without sacrificing the first gate structure 112 of the first NSFET 101.
Fig. 3 shows a cross-sectional view 300 of some alternative embodiments of fig. 2B, in which a first NSFET is arranged next to a second NSFET and coupled to the same contact hole.
In some embodiments, adhesion layer 116 comprises a conductive material, such as, for example, tantalum nitride or titanium nitride, and thus adhesion layer 116 is electrically coupled to first gate structure 112 and second gate structure 212. In some embodiments, a contact hole 302 may be arranged on and electrically coupled to the adhesive layer 116, and a gate voltage may be applied to the contact hole 302 to selectively "turn on" the first or second nsffet 101, 201. Because the first threshold voltage of the first NSFET101 is different from the second threshold voltage of the second NSFET201, the first NSFET101 can be turned "on" while the second NSFET201 is turned "off," or vice versa.
In some embodiments, the interfacial layer 120 may comprise an oxide such as, for example, silicon dioxide (silicon dioxide). In some embodiments, the gate dielectric layer 122 may comprise a high-k dielectric material, such as, for example, hafnium oxide (hafnium dioxide), zirconium dioxide (zirconium dioxide), hafnium silicon oxide (hafnium silicon oxide), or some other suitable dielectric material. Furthermore, in some embodiments, second conductive layer 224 comprises a conductive material, such as, for example, titanium nitride, tantalum nitride, tungsten carbon nitride (tungsten carbide nitride), or some other suitable conductive material. Thus, in some embodiments, second conductive layer 224 comprises the same material (e.g., titanium nitride) as first conductive layer 124, while in some other embodiments, second conductive layer 224 comprises a different material than first conductive layer 124.
Moreover, in some embodiments, the adhesion layer 116, the first conductive layer 124, and the second conductive layer 224 may comprise the same material (e.g., titanium nitride), while in some other embodiments, at least one of the adhesion layer 116, the first conductive layer 124, or the second conductive layer 224 may comprise a different material. It is understood that if the adhesive layer 116 and the second conductive layer 224 comprise the same material, the adhesive layer 116 and the second conductive layer 224 cannot be distinguished from each other. Accordingly, in the cross-sectional view 300 of fig. 3, the interface 304 between the adhesive layer 116 and the second conductive layer 224 is shown in dashed lines.
Furthermore, in some embodiments, the fourth dielectric ring 222a is separated from the fifth dielectric ring 222b by a first distance d1And the fifth dielectric ring 222b and the sixth dielectric ring 222c are separated by a first distance d1. In such embodiments, the second conductive layer 224 may have a third thickness t3 that is greater than or equal to half of the first distance d 1. Thus, in some embodiments, second conductive layer 224 is thicker than first conductive layer 124 and thicker than passivation layer 126.
FIGS. 4-13, 14A, 14B, 15-26 show various views 400-2600 of some embodiments of a method of forming a first NSFET having a first gate structure arranged next to a second NSFET having a second gate structure different from the first gate structure. Although fig. 4 to 13, 14A, 14B, and 15 to 26 are described with respect to one method, it is to be understood that the structures disclosed in fig. 4 to 13, 14A, 14B, and 15 to 26 are not limited to such a method, but may be used alone as a structure independent of the above-described method.
As shown in the perspective view 400 of fig. 4, a substrate 102 is provided. In some embodiments, the substrate 102 may be or include a semiconductor wafer, a semiconductor substrate, a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, the substrate 102 may include a first semiconductor material, such as, for example, silicon, germanium (germanium), or some other suitable semiconductor material. In such embodiments, the substrate 102 may be an intrinsic (e.g., undoped) semiconductor.
As shown in the perspective view 500 of fig. 5, in some embodiments, a semiconductor layer stack 501 may be formed on the substrate 102. The stack may comprise spacer layers 502 and semiconductor layers 506, wherein the spacer layers 502 and the semiconductor layers 506 are arranged in an alternating order in the semiconductor layer stack 501. In other words, each semiconductor layer 506 is arranged between a lower spacer layer 502 and an upper spacer layer 502. In some embodiments, semiconductor layer 506 comprises a first semiconductor material and spacer layer 502 comprises a second semiconductor material different from the first semiconductor material. For example, in some embodiments, the first semiconductor material may comprise silicon and the second semiconductor material may comprise germanium or silicon germanium (silicon germanium). In some embodiments, the semiconductor layer 506 and the spacer layer 502 are formed by an epitaxial growth process.
Furthermore, in some embodiments, the semiconductor layer 506 has a fourth thickness t4And the spacer layer 502 has a fifth thickness t5. In some embodiments, the spacer layer 502 is removed and finally the semiconductor layer 506 is formed into a nanosheet channel structure (see, e.g., 218 of fig. 14A). Thus, the fifth thickness t of the spacer layer 5025The spacing of the nanosheet channel structures (e.g., 218 of fig. 14A) can be determined. In some embodiments, the fourth thickness t4May be in a range, for example, between about 4 nanometers and about 8 nanometers. In some embodiments, the fifth thickness t5May be in a range, for example, between about 8 nanometers and about 15 nanometers. Furthermore, in some embodiments, the uppermost layer of the semiconductor layer stack 501 may be one of the spacers 502 for protecting the semiconductor layer 506 during future processing steps. In some embodiments, it may be appreciated that although four semiconductor layers 506 are shown in the perspective view 500 of fig. 5, the number of semiconductor layers 506 in the semiconductor layer stack 501 may be less than or greater than four.
As shown in the perspective view 600 of fig. 6, in some embodiments, the first mask structure 610 and the second mask structure 612 are arranged on the semiconductor layer stack (501 of fig. 5). In some embodiments, the first and second mask structures 610, 612 may be formed using photolithography and removal (e.g., etching) processes. In some embodiments, the first and second mask structures 610, 612 may comprise a photoresist material or a hard mask material.
Further, as shown in the perspective view 600 of FIG. 6, in some embodiments, the first and second masking structures may be based on610. A first removal process is performed 612 to form the first fin structures 104 and the second fin structures 204 from the substrate 102. In some embodiments, the first removal process may be or include a dry, vertical etch. The first fin structures 104 are continuously connected to the second fin structures 204 through the substrate 102, and the first fin structures 104 and the second fin structures 204 are directly below the first mask structures 610 and the second mask structures 612. In some embodiments, the first fin structures 104 are at a third distance d3Separate from the second fin structures 204. In some embodiments, for example, third distance d3 is in a range between approximately 30 nanometers and approximately 80 nanometers. In addition, the first removal process removes portions of the semiconductor layer (506 of fig. 5) and the spacer layer (502 of fig. 5) that are not covered by the first and second mask structures 610, 612. Thus, after the first removal process, in some embodiments, the first semiconductor layer stack 601 including the patterned spacer layer 602 and the patterned semiconductor layer 606 is arranged on the first fin structures 104, and the second semiconductor layer stack 603 including the patterned spacer layer 602 and the patterned semiconductor layer 606 is arranged on the second fin structures 204. It is understood that in other embodiments in which only one nanosheet field effect transistor (NSFET) is formed, the first mask structure 610 may be used without the second mask structure 612 to form the first fin structures 104 and the first semiconductor layer stack 601 arrayed on the substrate 102.
As shown in the perspective view 700 of fig. 7, in some embodiments, the lower isolation structures 106a may be formed on the substrate 102 and between the first fin structures 104 and the second fin structures 204. The lower isolation structures 106a may provide electrical isolation between the first fin structures 104 and the second fin structures 204. In some embodiments, the lower isolation structure 106a may comprise a dielectric material, such as, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-dielectric-constant (low-k) oxide (e.g., carbon-doped oxide, SiCOH), and the like.
In some embodiments, the lower isolation structure 106a is formed through various steps, including thermal oxidation or deposition processes (e.g., Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), PE-CVD, Atomic Layer Deposition (ALD), sputtering, etc.), and removal processes (e.g., wet etching, dry etching, Chemical Mechanical Polishing (CMP), etc.). For example, in some embodiments, a dielectric material is deposited on the substrate 102 and the first and second mask structures (610, 612 of fig. 6). Next, in some embodiments, a removal process, such as CMP, is used to remove portions of the dielectric material and the first and second mask structures (610, 612 of fig. 6), thereby exposing the first and second semiconductor layer stacks 601, 603. Next, in some embodiments, another removal process, such as vertical, dry etching, may be performed to remove the dielectric material surrounding portions of the first and second semiconductor layer stacks 601, 603 to form the lower isolation structure 106 a. It is understood that other processes and/or sequences of steps for forming the lower isolation structure 106a are also within the scope of the present disclosure.
As shown in the perspective view 800 of fig. 8, a dummy gate structure 804 may be formed on the first and second semiconductor layer stacks 601, 603. In some embodiments, the dummy interface layer 802 separates the first and second semiconductor layer stacks 601, 603 from the dummy gate structure 804, and the third mask structure 806 is arranged on the dummy gate structure 804. In some embodiments, to form the dummy gate structure 804, a dummy interface material of the dummy interface layer 802 is first formed on the first and second semiconductor layer stacks 601, 603. In some embodiments, the dummy interfacial layer 802 may comprise, for example, a dielectric material such as a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), or some other suitable material. Next, in some embodiments, a dummy gate material, such as, for example, polysilicon (polysilicon), of the dummy gate structure 804 is formed on the dummy interface material. The dummy gate material and/or the dummy interface material may be formed by a thermal oxidation process and/or a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, a third mask structure 806 is formed on the dummy gate material and directly over the first and second semiconductor layer stacks 601, 603. In some embodiments, the third mask structure 806 may be formed using photolithography and removal (e.g., etching) processes. In some embodiments, the third mask structure 806 may include a photoresist material or a hard mask material. After the formation of the third mask structure 806, a removal process (e.g., etching) may be performed to remove portions of the dummy gate material and the dummy interface material that are not directly under the third mask structure 806, thereby forming a dummy gate structure 804 and a dummy interface layer 802, respectively.
As shown in the perspective view 900 of fig. 9, in some embodiments, a gate spacer layer 902 may be formed on the lower isolation structure 106a, the first semiconductor layer stack 601, the second semiconductor layer stack 603, and the dummy gate structure (804 of fig. 8). In some embodiments, the gate spacer 902 may be or include a dielectric material such as, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low dielectric constant oxide (e.g., carbon doped oxide, SiCOH), and the like. Furthermore, in some embodiments, the gate spacer layer 902 may be deposited by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). It is understood that other materials and/or methods of forming the gate spacer 902 are also within the scope of the present disclosure.
As shown in the perspective view 1000 of fig. 10, in some embodiments, a second removal process may be performed to remove portions of the gate spacer 902, the first semiconductor layer stack 601, and the second semiconductor layer stack 603 that are not directly under the third mask structure 806. In some embodiments, the second removal process may be or include an etching process. In some embodiments, a single etchant may be used to remove the gate spacer layer 902, the first semiconductor layer stack 601, and the second semiconductor layer stack 603, while in other embodiments, multiple etchants may be used to perform the second removal process. After the second removal process, the first fin structures 104 and the second fin structures 204 are exposed. In some embodiments, an upper portion of the lower isolation structure 106a, the first fin structure 104, the second fin structure 204, and/or the third mask structure 806 may be left removed by a second removal process (residual). Thus, in some embodiments, after the second removal process, the first fin structures 104 and the second fin structures 204 may have upper surfaces that are below the upper surface of the lower isolation structure 106 a.
As shown in the perspective view 1100 of fig. 11, in some embodiments, an epitaxial process may be performed to form the first source/drain region 108 and the second source/drain region (not shown) on the first fin structure 104, and to form the third source/drain region 208 and the fourth source/drain region 210 on the second fin structure 204. First source/drain region 108, second source/drain region (not shown), third source/drain region 208, and fourth source/drain region 210 may comprise a third semiconductor material. In some embodiments, the third semiconductor material may be, for example, doped silicon. Thus, in some embodiments the first fin structure 104, the second fin structure 204, the first source/drain region 108, the second source/drain region (not shown), the third source/drain region 208, and the fourth source/drain region 210 may comprise silicon. In some embodiments, the first and second source/drain regions 108 and 210 (not shown) may have a first doping type, while the third and fourth source/ drain regions 208 and 208 may have a second doping type different from the first doping type. For example, in some embodiments, the first doping type may be n-type and the second doping type may be p-type. In some embodiments, the first source/drain region 108, the second source/drain region (not shown), the third source/drain region 208, and the fourth source/drain region 210 may have a hexagonal shape, a diamond shape, or some other geometric shape due to the epitaxial growth process. Furthermore, in some embodiments, first source/drain region 108, second source/drain region (not shown), third source/drain region 208, and fourth source/drain region 210 are not in direct contact with each other.
As shown in the perspective view 1200 of fig. 12, in some embodiments, the upper isolation structure 106b is formed on the lower isolation structure 106a, the first source/drain region 108, the second source/drain region (not shown), the third source/drain region 208, and the fourth source/drain region 210. In some embodiments, the upper isolation structure 106b comprises a dielectric material, such as, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low dielectric constant oxide (e.g., carbon doped oxide, SiCOH), and the like. In some embodiments, the upper isolation structure 106b may provide electrical isolation between the first source/drain region 108, the second source/drain region (not shown), the third source/drain region 208, and the fourth source/drain region (210 of fig. 11). In some embodiments, the upper isolation structure 106b is formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). Furthermore, in some embodiments, an etch stop layer (not shown) may be formed on the lower isolation structure 106a, the first source/drain region 108, the second source/drain region (not shown), the third source/drain region 208, and the fourth source/drain region (210 of fig. 11) prior to the formation of the upper isolation structure 106 b.
As shown in the perspective view 1300 of fig. 13, in some embodiments, a third removal process is performed to remove the third mask structure (806 of fig. 8), the dummy gate structure (804 of fig. 8), and the dummy interface layer (802 of fig. 8) from the first semiconductor layer stack 601 and the second semiconductor layer stack 603. In some embodiments, the third removal process includes a CMP step and/or an etching step. For example, in some embodiments, the third removal process first includes a CMP process to remove the upper portion of the upper isolation structure 106b and completely remove the third mask structure (806 of fig. 8) to expose the dummy gate structure (804 of fig. 8). In some embodiments, the third removal process further includes performing an etching process to completely remove the dummy gate structure (804 of fig. 8) to expose the first semiconductor layer stack 601 and the second semiconductor layer stack 603. It is understood that the second source/drain region 110 and the fourth source/drain region 210 are arranged behind the gate spacer 902, and thus are shown in dashed lines.
As shown in the perspective view 1400A of fig. 14A, in some embodiments, a fourth removal process is performed to remove the patterned spacer layer (602 of fig. 13) from the first semiconductor layer stack (601 of fig. 13) and to remove the patterned spacer layer (602 of fig. 13) from the second semiconductor layer stack (603 of fig. 13). In some embodiments, the fourth removal process comprises an isotropic etch step such that the patterned spacer layer (602 of fig. 13) from the first and second semiconductor layer stacks (601, 603 of fig. 13) may be completely removed from between the patterned semiconductor layers (606 of fig. 13). In some embodiments, the fourth removal process may include a wet etchant or a dry etchant. After the fourth removal process, the first nanosheet channel structure stack (see 118 of fig. 14B) comprising the patterned semiconductor layer (606 of fig. 13) extends from the first source/drain region 108 to the second source/drain region 110, and in some embodiments, the second nanosheet channel structure stack 218 comprising the patterned semiconductor layer (606 of fig. 13) extends from the third source/drain region 208 to the fourth source/drain region 210.
Fig. 14B shows a cross-sectional view 1400B of some embodiments, which may correspond to section line BB' of fig. 14A.
As shown in the cross-sectional view 1400B of fig. 14B, in some embodiments, after the fourth removal process, the first nanosheet channel structure stack 118 is arranged on the first fin structure 104 and the second nanosheet channel structure stack 218 is arranged on the second fin structure 204. In some embodiments, the first nanosheet channel structure stack 118 includes a first nanosheet channel structure 118a, a second nanosheet channel structure 118b, a third nanosheet channel structure 118c, and a fourth nanosheet channel structure 118 d. In some embodiments, the second nanosheet channel structure stack 218 includes a fifth nanosheet channel structure 218a, a sixth nanosheet channel structure 218b, a seventh nanosheet channel structure 218c, and an eighth nanosheet channel structure 218 d. Thus, in some embodiments, the first nanosheet channel structure stack 118 includes four nanosheet channel structures and the second nanosheet channel structure stack 218 includes four nanosheet channel structures. It will be appreciated that in other embodiments, the first and second stacks of nanosheet channel structures 118, 218 may each include more or less than four nanosheet channel structures.
In some embodiments, after the fourth removal process, the first through eighth nanosheet channel structures 118a-d, 218a-d exhibit elongated oval or rectangular shapes with rounded (rounded) corners as shown in cross-section 1400B. In some embodiments, the rounded corner is the result of the fourth removal process. In other embodiments, after the fourth removal process, the first through eighth nanosheet channel structures 118a-d, 218a-d may assume a circular, square, rectangular, hexagonal, elliptical, diamond, or some other geometric shape, as shown in cross-section 1400B.
Further, in some embodiments, the first through fourth nanosheet channel structures 118a-d are at a fourth distance d4Spaced apart from one another and the fifth through eighth nanosheet channel structures 218a-d also being a fourth distance d4Are spaced apart from each other. For example, the fourth distance d4Is the distance between the upper surface of the third nanoplatelet channel structure 118c and the lower surface of the fourth nanoplatelet channel structure 118 d. In some embodiments, for example, the fourth distance d4In a range between about 8 nanometers and about 15 nanometers. Thus, in some embodiments, the fifth thickness (t of FIG. 5) of the spacer layer (502 of FIG. 5)5) Will determine the fourth distance d4. Furthermore, in some embodiments, the first through fourth nanosheet channel structures 118a-d and the fifth through eighth channel structures 218a-d each have a fourth thickness t4. In some embodiments, the fourth thickness t4May be in a range, for example, between about 4 nanometers and about 8 nanometers. Thus, in some embodiments, the fourth thickness t of the semiconductor layer 5064A fourth thickness t of the first through eighth nanosheet channel structures 118a-d, 218a-d is determined4. Further, in some embodiments, the first through eighth nanosheet channel structures 118a-d, 218a-d can have a first width w1In a range between, for example, about 40 nanometers and about 60 nanometers. It will be appreciated that other values of the fourth distance d4A fourth thickness t4And a first width w1Are also within the scope of the present disclosureAnd (4) the following steps.
It will be appreciated that for ease of illustration, a generic layer 1402 is shown behind the first and second nanosheet channel structure stacks 118, 218 and in front of the second and fourth source/ drain regions 110, 210. For example, from the perspective view 1400A of FIG. 14A, it can be appreciated that in the cross-sectional view 1400B of FIG. 14B, the generic layer 1402 represents the gate spacer layer 902 in some embodiments. The generic layer 1402 is shown in dotted outline as a white box. As a result, the film formed around the first and second nanosheet channel structures 118, 218 may be more readily visible in future processing steps.
Further, it is understood that the identification codes (identifiers) used in the present disclosure for the nanosheet channel structures (e.g., 118a, 118b, 218a, 218b, etc.), the interface rings (e.g., 120a, 120b, 220a, 220b, etc.), the dielectric rings (e.g., 122a, 122b, etc.), and the conductive rings (e.g., 124a, 124b, 224a, 224b, etc.) are generic identifiers and may vary between illustration. For example, in fig. 2B, the fourth nanosheet channel structure is labeled "218 a", while in fig. 14B, "218 a" labels the fifth nanosheet channel structure.
As shown in the cross-sectional view 1500 of fig. 15, in some embodiments, an interface layer 120 is formed over the first and second fin structures 104, 204 and between the first through eighth nanosheet channel structures 118a-d, 218 a-d. In some embodiments, the interfacial layer 120 may comprise, for example, an oxide such as silicon dioxide. In such embodiments, the interfacial layer 120 may be formed by a thermal oxidation process or by other deposition processes (e.g., CVD, PVD, PE-CVD, ALD, sputtering, etc.). In some embodiments, the interfacial layer 120 may have a thickness in a range between about 8 angstroms and about 15 angstroms, for example. In some embodiments, the interface layer 120 includes a first interface ring 120a, a second interface ring 120b, a third interface ring 120c, a fourth interface ring 120d, a fifth interface ring 220a, a sixth interface ring 220b, a seventh interface ring 220c, and an eighth interface ring 220d that directly contact and continuously surround the first nanosheet channel structure 118a, the second nanosheet channel structure 118b, the third nanosheet channel structure 118c, the fourth nanosheet channel structure 118d, the fifth nanosheet channel structure 218a, the sixth nanosheet channel structure 218b, the seventh nanosheet channel structure 218c, and the eighth nanosheet channel structure 218d, respectively.
Furthermore, in some embodiments, a gate dielectric layer 122 is formed on the interface layer 120. In some embodiments, the gate dielectric layer 122 may comprise a high-k dielectric material, such as, for example, hafnium dioxide, zirconium dioxide, hafnium silicon oxide, or some other suitable dielectric material. In some embodiments, the gate dielectric layer 122 may be formed by a deposition process (e.g., CVD, PVD, PECVD, ALD, sputtering, etc.). In some embodiments, the gate dielectric layer 122 may have a thickness in a range between about 10 angstroms and about 20 angstroms, for example. In some embodiments, the gate dielectric layer 122 includes a first dielectric ring 122a, a second dielectric ring 122b, a third dielectric ring 122c, a fourth dielectric ring 122d, a fifth dielectric ring 222a, a sixth dielectric ring 222b, a seventh dielectric ring 222c, and an eighth dielectric ring 222d that continuously surround the first nanosheet channel structure 118a, the second nanosheet channel structure 118b, the third nanosheet channel structure 118c, the fourth nanosheet channel structure 118d, the fifth nanosheet channel structure 218a, the sixth nanosheet channel structure 218b, the seventh nanosheet channel structure 218c, and the eighth nanosheet channel structure 218d, respectively. In some embodiments, the interfacial layer 120 and the gate dielectric layer 122 may also be formed on the gate spacer layer (902 of fig. 14A). In such an embodiment, the common layer 1402 may represent the gate dielectric layer 122 after the formation of the interface layer 120 and the gate dielectric layer 122.
After the formation of the interfacial layer 120 and the gate dielectric layer 122, in some embodiments, the first distance d1 is maintained between the nearest neighboring first through eighth dielectric rings 122a-122d, 222a-222 d. For example, the first dielectric ring 122a is directly over the gate dielectric layer 122 disposed on the first fin structure 104, and the first dielectric ring 122a is spaced apart from the gate dielectric layer 122 disposed on the first fin structure 104 by a first distance d 1. Also, for example, the fourth dielectric ring 122d is directly above the third dielectric ring 122c, and the fourth dielectric ring 122d is spaced apart from the third dielectric ring 122c by a first distance d 1. In some embodiments, the first distance d1 is in a range between, for example, about 4 nanometers and about 6 nanometers.
As shown in cross-section 1600 of fig. 16, in some embodiments, a dummy mask layer 1602 is formed over the first fin structure 104, the second fin structure 204, and the first through eighth nanosheet channel structures 118a-d, 218 a-d. In some embodiments, the dummy mask layer 1602 includes aluminum oxide (aluminum oxide). It is understood that other materials for dummy mask structure 1602 are also within the scope of the present disclosure. In some embodiments, the dummy mask structure 1602 may be formed by a deposition process (e.g., CVD, PVD, PE-CVD, ALD, sputtering, etc.). The dummy mask layer 1602 is formed to completely cover the first fin structure 104, the second fin structure 204, and the first through eighth nanosheet channel structures 118a-d, 218 a-d. In some embodiments, the dummy mask layer 1602 has a sixth thickness t6, and the sixth thickness t6 is at least equal to half of the first distance d 1. Thus, the dummy mask layer 1602 completely fills the space between the nearest neighboring first through eighth dielectric rings 122a-122d, 222a-222d directly. For example, in some embodiments, the dummy mask layer 1602 is directly arranged in the space between the fourth dielectric ring 122d and the third dielectric ring 122 c.
In some embodiments, a fifth removal process is performed to remove the outer portion of the dummy mask layer (1602 of fig. 16) to form a dummy mask structure 1702, as shown in the cross-sectional view 1700 of fig. 17. Thus, in some embodiments, after the fifth removal process, the dummy mask structures 1702 are at least directly arranged between the second fin structure 204 and the fifth nanosheet channel structure 218a, between the fifth nanosheet channel structure 218a and the sixth nanosheet channel structure 218b, between the sixth nanosheet channel structure 218b and the seventh nanosheet channel structure 218c, and between the seventh nanosheet channel structure 218c and the eighth nanosheet channel structure 218 d.
In some embodiments, the fifth removal process may include an isotropic wet etch. For example, in some embodiments, the fifth removal process may include hydrogen oxidationAn ammonium hydroxide solution that selectively removes the dummy mask layer (1602 of fig. 16) without removing the gate dielectric layer 122. Therefore, in some embodiments, the dummy mask layer (1602 of fig. 16) is a material that can be selectively removed by a specific wet etchant, which does not remove the material of the gate dielectric layer 122. Therefore, the dummy mask layer (1602 of fig. 16) and other etchants for the fifth removal process are also within the scope of the present disclosure. In addition, in some embodiments, a fifth removal process is performed for a period of time to remove at least the sixth thickness t of the dummy mask layer (1602 of fig. 16)6. Thus, the dummy mask layer 1702 remains between the first fin structure 104, the second fin structure 204, and the first through eighth nanosheet channel structures 118a-d, 218a-d, as shown in the cross-sectional view 1700 of fig. 17.
As shown in cross-section 1800 of fig. 18, in some embodiments, a fourth mask structure 1802 is formed over the second fin structures 204 and the fifth through eighth nanosheet channel structures 218 a-d. The fourth mask structure 1802 is not directly over the first fin structure 104 or the first through fourth nanosheet channel structures 118 a-d. In some embodiments, the fourth mask structure 1802 may be formed using deposition (e.g., spin-coating), photolithography, and removal (e.g., etching) processes. For example, in some embodiments, the fourth mask structure 1802 may be or include a bottom anti-reflective coating (BARC), an anti-reflective coating (ARC), or some other suitable photoresist material. In some other embodiments, the fourth mask structure 1802 may be or include a hard mask material.
After the formation of the fourth mask structure 1802, in some embodiments, a sixth removal process is performed to remove the dummy mask structure 1702 not covered by the fourth mask structure 1802. In some embodiments, the sixth removal process includes the same wet etchant as the fifth removal process because the same dummy mask material is removed. Thus, in some embodiments, the dummy mask structures 1702 comprise aluminum oxide, and the sixth removal process comprises ammonium hydroxide to selectively remove the dummy mask structures 1702 not covered by the fourth mask structures 1802 without removing the gate dielectric layer 122. After the sixth removal process, the dummy mask structures 1702 are not directly over the first fin structures 104.
As shown in the cross-sectional view 1900 of fig. 19, in some embodiments, the fourth mask structure 1802 is removed, and the first conductive layer 124 is formed over and completely surrounds the first through fourth nanosheet channel structures 118 a-d. In some embodiments, the first conductive layer 124 does not completely surround the fifth through eighth nanosheet channel structures 218a-d because of the dummy mask structure 1702. In some embodiments, the first conductive layer 124 is formed to have a first thickness t1And includes a first conductive ring 124a around the first nanosheet channel structure 118a, a second conductive ring 124b around the second nanosheet channel structure 118b, a third conductive ring 124c around the third nanosheet channel structure 118c, and a fourth conductive ring 124d around the fourth nanosheet channel structure 118 d. A first thickness t1Is less than the first distance d1Half of that. Thus, the first pedestal layer 124 does not completely fill the first distance d between the first fin structure 104 and the first through fourth nanosheet channel structures 118a-d1The defined space.
In some embodiments, first conductive layer 124 comprises a conductive material, such as titanium nitride. In such an embodiment, the first conductive layer 124 may be deposited by a first Atomic Layer Deposition (ALD) process. Since the first ALD process is a self-limiting (self-limiting) process, the first thickness t1 of the first conductive layer 124 can be more easily and precisely controlled. For example, in some embodiments, the formation of the first conductive layer 124 using the first ALD process stops when the reaction site or surface, such as the outer surface of the gate dielectric layer 122, is saturated or covered by the first conductive layer 124. In some embodiments, first thickness t1 is in a range, for example, between about 8 angstroms and about 50 angstroms. Furthermore, as shown in graph 100D of fig. 1D, in some embodiments, the first thickness t1 depends on the first distance D1 and also depends on the desired first work function of the first gate structure (see 112 of fig. 22) to be formed including the first pad layer 124. In some embodiments, when the first conductive layer 124 comprises titanium nitride, the precursor reactants for the first ALD process include titanium tetrachloride (titanium tetrachloride) and ammonia (ammonia). It is understood that other materials of first conductive layer 124 and corresponding precursor reactants to form first conductive layer 124 are also within the scope of the present disclosure.
In some embodiments, as shown in cross-section 2000 of fig. 20, a passivation layer 126 is formed on and around the first conductive layer 124. The passivation layer 126 may be directly disposed between the first fin structure 104 and the first conductive ring 124a, directly disposed between the first conductive ring 124a and the second conductive ring 124b, directly disposed between the second conductive ring 124b and the third conductive ring 124c, and directly disposed between the third conductive ring 124c and the fourth conductive ring 124 d. The passivation layer 126 includes a first passivation ring 126a, a second passivation ring 126b, a third passivation ring 126c, and a fourth passivation ring 126d that completely cover the first conductive ring 124a, the second conductive ring 124b, the third conductive ring 124c, and the fourth conductive ring 124d, respectively. In some embodiments, the passivation layer 126 has a second thickness t2, which may be in a range, for example, between about 10 angstroms and about 20 angstroms. The second thickness t2 depends on at least the first distance d1 and the first thickness t 1. Further, in some embodiments, the passivation layer 126 includes silicon. In some embodiments in which the passivation layer 126 comprises silicon and the first conductive layer 124 comprises titanium nitride, the presence of the passivation layer 126 lowers the first work function of a first gate structure (see 112 of fig. 22) to be formed comprising the first conductive layer 124 and the passivation layer 126, as shown in graph 100D of fig. 1D.
In some embodiments, the passivation layer 126 is also deposited by an ALD process. By utilizing the second ALD process, the second thickness t2 of the passivation layer 126 may be controlled to be less than about 20 angstroms in some embodiments, and thus fit (fit) between each of the first through fourth conductive rings 124 a-d. In some embodiments, the passivation layer 126 comprises silicon and the precursor reactant for the second ALD process comprises silane (silicon tetra-hydride). Furthermore, in some embodiments, a first ALD process to form the first conductive layer 124 is performed in a first reaction chamber, and a second ALD process to form the passivation layer 126 is performed in a second reaction chamber. In such embodiments, the first and second reaction chambers may be part of the same host structure and, thus, not break the vacuum seal when the substrate (102 of fig. 14A) is moved from the first reaction chamber to the second reaction chamber. In such an embodiment, the first ALD process may be performed in-situ with the second ALD process, since the first and second ALD processes are performed on the same host structure without vacuum sealing. Thus, the first conductive layer 124 does not oxidize between the first ALD process and the second ALD process because there is no vacuum seal broken. In some embodiments, if the first conductive layer 124 is oxidized between the first ALD process and the second ALD process, there may be no space between the first through fourth conductive rings 124a-d for the passivation layer 126 to fit. Furthermore, if an oxide layer is arranged between the passivation layer 126 and the first conductive layer 124, it may not be possible to control the desired first work function of the first gate structure to be formed (see 112 of fig. 22).
As shown in the cross-sectional view 2100 of fig. 21, in some embodiments, a fifth mask structure 2102 is formed over the first fin structure 104 and the first through fourth nanosheet channel structures 118 a-d. The fifth mask structure 2102 does not lie directly over the second fin structure 204 or the fifth through eighth nanosheet channel structures 218 a-d. In some embodiments, the fifth mask structure 2102 may be formed by deposition (e.g., spin coating), photolithography, and removal (e.g., etching) processes. For example, in some embodiments, the fifth masking structure 2102 may be or include a bottom anti-reflective coating (BARC), an anti-reflective coating (ARC), or some other suitable photoresist material. In some other embodiments, the fifth masking structure 2102 may be or include a hard mask material.
As shown in the cross-sectional view 2200 of fig. 22, in some embodiments, a seventh removal process is performed to remove the passivation layer 126 and the first conductive layer 124 from the fifth through eighth nanosheet channel structures 218a-d and the portion of the passivation layer 126 and the first conductive layer 124 that is not directly under the fifth masking structure 2102. In some embodiments, the seventh removal process includes an isotropic etch to remove the passivation layer 126 and the first conductive layer 124 in all directions that are not directly under the fifth mask structure 2102. In some embodiments, for example, the seventh removal process includesAnd (4) wet etching agent. Furthermore, in some embodiments, the seventh removal process may include a first wet etchant to remove a portion of the passivation layer 126 and a second wet etchant to remove a portion of the first conductive layer 124, while in other embodiments, the seventh removal process may include a single wet etchant to remove both the passivation layer 126 and the first conductive layer 124. After the seventh removal process, a first nsefet 101 is formed, including a first gate structure 112 including a first conductive layer 124 and a passivation layer 126 over the first fin structure 104 and the first through fourth nanosheet channel structures 118 a-d. The first gate structure 112 may have a first work function that is at least dependent on the first thicknesses t of the first conductive layer 124 and the passivation layer 126, respectively1And a second thickness t2。
Furthermore, in some embodiments, the dummy mask structure 1702 reduces the maximum dimension of the first conductive layer 124 and the passivation layer 126 to be removed by the seventh removal process by at least the fifth distance d5. In some embodiments, the fifth distance d5Is equal to about the second width w of the dummy mask structure 17022Half of that. In some embodiments, for example, because of the dummy mask structure 1702, the maximum dimension of the first conductive layer 124 for removal by the seventh etching process may be equal to the first thickness t1And the passivation layer 126 for passing through the seventh etching process may be equal to the second thickness t2。
In some embodiments, the etch time of the seventh removal process may be reduced as a result of shrinking the maximum size of the first conductive layer 124 and the passivation layer 126 for removal by the seventh removal process. Then, the portion 2202 of the first conductive layer 124 and the passivation layer 126 that is arranged directly below the fifth mask structure 2102 and closest to the second fin structures 204 is not exposed for that long in the seventh removal process. Thus, removal of the first conductive layer 124 and the portion 2202 of the passivation layer 126 is prevented or at least mitigated. In other embodiments, if the dummy mask structure 1702 is not provided, it is understood that the overetching of the seventh removal process may also remove portions of the first conductive ring 124a and/or the first passivation ring 126a, thereby compromising the reliability of the first gate structure 112. Therefore, due to the dummy mask structure 1702, the seventh removal process is faster, and the exposure of the first conductive layer 124 and the passivation layer 126 to the etchant of the seventh removal process is reduced, thereby preventing damage to the first gate structure 112.
In some embodiments, an eighth removal process is performed to completely remove the dummy mask structure (1702 of FIG. 22), as shown in cross-section 2300 of FIG. 23. In some embodiments, the fifth mask structure 2102 remains on the first NSFET101 during the eighth removal process. In some embodiments, the eighth removal process includes an etchant that can remove the dummy mask structure (1702 of fig. 22) in the lateral direction. In some embodiments, the dummy mask structure (1702 of fig. 22) may comprise aluminum oxide, and the eighth removal process may use a wet etchant, such as, for example, ammonium hydroxide, to completely remove the dummy mask structure (1702 of fig. 22), while the first conductive layer 124, the passivation layer 126, and the gate dielectric layer 122 remain unchanged. Accordingly, the dummy mask structure (1702 of fig. 22) advantageously reduces over-etching of the first conductive layer 124 and the passivation layer 126 during the seventh removal process of fig. 22 without damaging other components (e.g., the first conductive layer 124, the passivation layer 126, and the gate dielectric layer 122).
As shown in the cross-sectional view 2400 of fig. 24, in some embodiments, the fifth mask structure (2102 of fig. 23) is removed and a second conductive layer 224 is formed over the first fin structure 104, the second fin structure 204, and the first through eighth nanosheet channel structures 118a-d, 218 a-d. In some embodiments, the second conductive layer 224 has a third thickness t3 that is at least equal to half the first distance d1, such that the second conductive layer 224 completely and continuously surrounds the fifth through eighth nanosheet channel structures 218 a-d. For example, in some embodiments, the second conductive layer 224 includes a fifth conductive ring 224a, a sixth conductive ring 224b, a seventh conductive ring 224c, and an eighth conductive ring 224d that continuously surround and contact the fifth dielectric ring 222a, the sixth dielectric ring 222b, the seventh dielectric ring 222c, and the eighth dielectric ring 222d, respectively. Furthermore, in some embodiments, a second dielectric layer 224 is also disposed on passivation layer 126. However, in some embodiments, the second conductive layer 224 is not directly arranged between the first fin structure 104 and the first nanoplatelet channel structure 118a, is not directly arranged between the first nanoplatelet channel structure 118a and the second nanoplatelet channel structure 118b, is not directly arranged between the second nanoplatelet channel structure 118b and the third nanoplatelet channel structure 118c, or is not directly arranged between the third nanoplatelet channel structure 118c and the fourth nanoplatelet channel structure 118 d. Furthermore, in some embodiments, the second conductive layer 224 does not affect or significantly affect the first work function of the first gate structure 112. Instead, in some embodiments, the first work function of the first gate structure 112 is dominated by the first conductive layer 124 and the passivation layer 126.
In some embodiments, the second conductive layer 224 is deposited by a third ALD process. Moreover, in some embodiments, second conductive layer 224 comprises a conductive material such as, for example, titanium nitride, tantalum nitride, and the like. In some embodiments, after the formation of the second conductive layer 224, the second gate structure 212 is formed on the second fin structure 204, thereby forming the second nsffet 201 arranged next to the first nsffet 101. In some embodiments, second gate structure 212 has a second work function different from the first work function, depending at least on the conductive material of second conductive layer 224. In some embodiments, the first NSFET101 may be formed next to the second NSFET201 at least because of the dummy mask structure (1702 of FIG. 22), wherein the first gate structure 112 of the first NSFET101 has a different structure than the second gate structure 212 of the second NSFET 201.
Further, it is understood that in some instances, the first and second NSFETs 101 and 201 may also be referred to as, for example, a full wrap gate FET, a gate wrap transistor, a multi-bridge channel (MBC) transistor, a nanowire FET, and the like.
In some embodiments, as shown in the cross-sectional view 2500 of fig. 25, an adhesion layer 116 is formed on the first and second NSFETs 101, 201. In some embodiments, adhesion layer 116 comprises a conductive material such as, for example, titanium nitride, tantalum nitride, tungsten carbon nitride, or some other suitable material. In some embodiments, adhesion layer 116 is formed by a deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.).
Furthermore, in some embodiments, adhesion layer 116 does not affect or does not significantly affect the first work function of first gate structure 112 or the second work function of second gate structure 212. Instead, a first work function of the first gate structure 112 is dominated by the first conductive layer 124 and the passivation layer 126, and a second work function of the second gate structure 212 is dominated by the second conductive layer 224.
In some embodiments, contact hole 302 is formed in adhesion layer 116, as shown in cross-section 2600 of FIG. 26. In some embodiments, the contact hole 302 may comprise, for example, tungsten (tungsten), aluminum (aluminum), copper (copper), or some other suitable conductive material. In some embodiments, the contact hole 302 may be formed by various steps including deposition processes (e.g., Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), PE-CVD, Atomic Layer Deposition (ALD), etc.), removal processes (e.g., wet etching, dry etching, Chemical Mechanical Polishing (CMP), etc.), and/or patterning processes (e.g., photolithography/etching). In operation, in some embodiments, contact hole 302 may be coupled to a gate electrode source. Because the first work function of the first gate structure 112 is different from the second gate structure 212, the first NSFET101 may have a first threshold voltage different from that of the second NSFET 201. Thus, in some embodiments, the gate source may selectively "turn on" either the first NSFET101 or the second NSFET 201.
Fig. 27, corresponding to fig. 4-13, 14A, 14B, 15-26, illustrate a flow chart of some embodiments of a method 2700 of forming a first NSFET field effect transistor (nsffet) next to a second NSFET field effect transistor (NSFET).
While method 2700 is illustrated and described as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments described herein. Further, one or more of the acts described herein may be performed in one or more separate acts and/or phases.
In act 2702, a first nanoplatelet channel structure is formed vertically spaced apart from a second nanoplatelet channel structure and on a substrate.
In act 2704, a third nanoplatelet channel structure is formed vertically spaced from and laterally alongside a fourth nanoplatelet channel structure, which is laterally alongside the second nanoplatelet channel structure. FIGS. 4-14B illustrate various views 400-1400B of some embodiments corresponding to acts 2702 and 2704.
In act 2706, a gate dielectric layer is formed to completely cover the first, second, third, and fourth nanosheet channel structures. Fig. 15 illustrates a cross-sectional view 1500 of some embodiments corresponding to act 2706.
In act 2708, a dummy mask structure is formed directly between the third and fourth nanosheet channel structures and between the third nanosheet channel structure and the substrate. FIGS. 16-18 illustrate cross-sectional views 1600-1800 of some embodiments corresponding to act 2708.
In act 2710, a first ALD process is performed to form a first conductive layer around the first and second nanosheet channel structures. Fig. 19 shows a cross-sectional view 1900 of some embodiments of corresponding action 2710.
In act 2712, a second ALD process is performed to form a passivation layer on the first conductive layer and directly between the first and second nanosheet channel structures. Fig. 20 illustrates a cross-sectional view 2000 of some embodiments corresponding to act 2712.
In act 2714, a mask structure is formed over the first and second nanoplatelet channel structures. Fig. 21 shows a cross-sectional view 2100 of some embodiments of corresponding action 2714.
In act 2716, the first conductive layer, the passivation layer, and the dummy mask structure are removed from the third and fourth nanoplate channel structures. Fig. 22 and 23 show cross-sectional views 2200 and 2300, respectively, of some embodiments of corresponding action 2716.
In act 2718, a third ALD process is performed to deposit a second conductive layer over the third and fourth nanoplate channel structures. Fig. 24 shows a cross-sectional view 2400 of some embodiments corresponding to act 2718.
Accordingly, the present disclosure is directed to a method of forming a first NSFET having a first gate structure laterally adjacent to a second NSFET having a second gate structure, wherein device density is increased by forming a dummy mask structure and performing an ALD process while still maintaining reliability of the first and second NSFETs.
Accordingly, in some embodiments, the present disclosure relates to an integrated chip comprising: a first nanosheet field effect transistor, comprising: the first nanosheet channel structure is arranged on the substrate; the second nano-sheet channel structure is directly arranged on the first nano-sheet channel structure and extends from the first source electrode/drain electrode region to the second source electrode/drain electrode region in parallel; and a first gate structure comprising: the nano-film structure comprises a first conducting ring, a second conducting ring and a passivation layer, wherein the first conducting ring comprises a first material and completely surrounds a plurality of outer side walls of a first nano-film channel structure, the second conducting ring comprises a first material and completely surrounds a plurality of outer side walls of a second nano-film channel structure, the passivation layer completely surrounds the first conducting ring and the second conducting ring, the first conducting ring and the second conducting ring are directly arranged between the first nano-film channel structure and the second nano-film channel structure, and the first conducting ring and the second conducting ring comprise a second material different from.
In some embodiments, the present disclosure relates to an integrated chip comprising: a first nanosheet field effect transistor (NSFET) comprising: a first source/drain region and a second source/drain region having a first doping type and arranged on the substrate; a first nanosheet channel structure and a second nanosheet channel structure arranged on the substrate and extending in parallel between the first and second source/drain regions, wherein the second nanosheet channel structure is directly arranged on the first nanosheet channel structure; a first gate structure comprising: a first conducting ring completely surrounding the first nanosheet channel structure, and a second conducting ring completely surrounding the second nanosheet channel structure; and a second NSFET arranged laterally next to the first NSFET, and including: a third source/drain region and a fourth source/drain region having a second doping type different from the first doping type and arranged on the substrate; a third nanosheet channel structure and a fourth nanosheet channel structure arranged on the substrate and extending in parallel between the third and fourth source/drain regions, wherein the fourth nanosheet channel structure is directly arranged on the third nanosheet channel structure; and a second gate structure comprising: a third conductive ring completely surrounding the third nanosheet channel structure, a fourth conductive ring completely surrounding the fourth nanosheet channel structure, and a passivation layer surrounding the third and fourth conductive rings and directly separating the third conductive ring from the fourth conductive ring.
In still other embodiments, the present disclosure relates to a method of forming an integrated chip, comprising: forming a first nanosheet channel structure and a second nanosheet channel structure on the substrate, and extending in parallel between the first source/drain region and the second source/drain region, wherein the second nanosheet channel structure is directly arranged on the first nanosheet channel structure; forming a first dielectric ring and a second dielectric ring respectively covering a plurality of outer surfaces of the first nanosheet channel structure and the second nanosheet channel structure; performing a first Atomic Layer Deposition (ALD) process to form a first conductive layer on the substrate, including a first conductive ring on the first dielectric ring and a second conductive ring on the second dielectric ring; and performing a second ALD process to form a passivation layer on the first and second conductive rings, wherein the passivation layer separates the first and second conductive rings.
The components of several embodiments are summarized above so that those skilled in the art can more easily understand the aspects of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions and processes do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the appended claims.

Claims (1)

1. An integrated chip, comprising:
a first nanosheet field effect transistor, comprising:
the first nanosheet channel structure is arranged on a substrate;
a second nanosheet channel structure directly arranged on the first nanosheet channel structure and extending in parallel from a first source/drain region to a second source/drain region; and
a first gate structure comprising:
a first conductive ring comprising a first material and completely surrounding the outer sidewalls of the first nanosheet channel structure,
a second conductive ring comprising the first material and completely surrounding a plurality of outer sidewalls of the second nanosheet channel structure, and
a passivation layer completely surrounding the first conductive ring and the second conductive ring, directly arranged between the first nanosheet channel structure and the second nanosheet channel structure, and comprising a second material different from the first material.
CN202011187561.9A 2019-10-30 2020-10-30 Integrated chip Pending CN112750910A (en)

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US201962927866P 2019-10-30 2019-10-30
US62/927,866 2019-10-30
US16/819,632 US11502168B2 (en) 2019-10-30 2020-03-16 Tuning threshold voltage in nanosheet transitor devices
US16/819,632 2020-03-16

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