CN112737532A - Novel variable gain amplifier with high gain precision and low additional phase shift - Google Patents
Novel variable gain amplifier with high gain precision and low additional phase shift Download PDFInfo
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- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
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Abstract
The invention belongs to the technical field of wireless communication, and particularly provides a novel variable gain amplifier with high gain precision and low additional phase shift, which is used for solving the problems that the additional phase shift is large in a high gain state and the high DAC bit requirement is high in high gain precision of the traditional variable gain amplifier. According to the invention, an asymmetric capacitance technology is introduced on the basis of a differential circuit structure, so that on one hand, the problem of large phase change under a high-gain state caused by different parasitic capacitances of two paths of differential circuits under different biases can be effectively solved; on the other hand, the technology also has a gain precision adjusting function, only the size of the asymmetric capacitor needs to be configured reasonably, and high-gain precision control can be realized under the condition that the DAC digit is not increased. In summary, compared with the conventional variable gain amplifier structure, the present invention realizes a lower additional phase shift in the high gain state and high gain precision control with the same DAC bit number.
Description
Technical Field
The invention belongs to the technical field of wireless communication, relates to a variable gain amplifier in a transceiver of a wireless communication system, and particularly provides a novel variable gain amplifier with high gain precision and low additional phase shift.
Background
In a wireless communication system receiver, because different areas have different distances from wireless communication equipment, the transmission process is affected differently by noise, loss and the like, and the receiving equipment needs to amplify different powers according to different received signals. In a wireless communication system transmitter, in order to better suppress sidelobe emission and higher signal quality, the gain of each channel needs to be adjusted; as a result, Variable Gain Amplifiers (VGAs) have been developed, and have played a crucial role in the front end of transceiver systems for wireless communications.
With the development of communication systems, miniaturization, portability and high performance are required for the communication systems, and integrated circuits are developed to meet these requirements. Silicon-based processes have attracted attention in the art of integrated circuit fabrication because of their low cost, low power consumption, and increased speed. The silicon-based process comprises two processes of SiGe and CMOS, most VGA designs adopt the SiGe process at present, and more high-gain precision and low-additional phase shift technologies are provided on the basis of the SiGe process. For example, in 2016, f.padovan et al, based on SiGe technology, implemented low additional phase shift for VGA by using zero-pole compensation method (f.padovan, m.tiebout, a.neviani and a.bevilacqua, "a 15.5-39 GH z BiCMOS VGA with phase shift compensation for 5G mobility transmission," escirc Conference 2016: 42)ndEuropean Solid-State Circuits Conference, Lausane, 2016, pp.363-366); in 2017, B.Sadhu et al realized low additional Phase shift of VGA by using a local feedback method based on SiGe process (B.Sadhu et al, "A28-GHz 32-Element TRX Phase-Array IC WithConcurrant Dual-Polarized Operation and Orthogonal Phase and gain control for 5G Communication," in IEEE Journal of Solid-State information, vol.52, No.12, pp.3373-3391, Dec.2017). Since the SiGe process is more expensive to manufacture than the CMOS process, it is more expensive to implementLow manufacturing cost, it is very important to develop a high gain accuracy and low phase change VGA based on CMOS process; however, since the SiGe process is based on a Heterojunction Bipolar Transistor (HBT) to achieve the control of the dB linearity and the CMOS process is based on a metal-oxide semiconductor field effect transistor (MOS FET) to achieve the control of the dB linearity, and the HBT and the MOSFET have different operation principles, the high gain accuracy and low phase variation technique based on the SiGe process are not suitable for the CMOS process.
In 2019, wu Tianjun, university of electronic technology, proposed a VGA design with Low additional Phase shift based on CMOS process (t.wu, c.zhao, h.liu, y.wu, y.yu and k.kang, "a 20-43 GHz VGA with 21.5dB Gain Tuning Range and Low Phase Variation for 5G Communications in 65-nm CM OS,"2019IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Boston, MA, US a,2019, pp.71-74.); the design scheme adopts the parasitic capacitance elimination and the layout isolation enhancement technology to realize low additional phase shift. In the VGA gain change process, the main reason of phase change is caused by parasitic capacitance, so that the elimination of the influence of the parasitic capacitance is the most effective method for realizing VGA low additional phase shift. As shown in fig. 7(a), the scheme adopts a differential common source circuit structure to realize low additional phase shift of the VGA, and as shown in fig. 7(b), a small-signal equivalent model of the differential common source circuit is shown, and it can be seen from the model that, due to the adoption of the differential structure, the current flow direction (I) of the parasitic capacitance of the two transistors is enabled to be (I)1、I2) The opposite is true, thereby achieving cancellation of parasitic capacitances and hence low additional phase shift. However, the parasitic capacitance cannot be completely cancelled out by the scheme, because the parasitic capacitance of the transistors is different under different biases; therefore, although the scheme reduces the phase change caused by parasitic capacitance to a certain extent, the phase change cannot be completely eliminated, so that the VGA still has certain additional phase shift in the gain change process; especially in the high gain state, the bias of the two transistors has a large difference, so that the parasitic capacitances of the two transistors also have a large difference, and the above scheme can only cancel a small part of the parasitic capacitance, so that the phase of the VGA changes greatly in the high gain state. Further, the scheme is to realize low additionThe phase shift, on the one hand, utilizes parasitic capacitance cancellation techniques and, on the other hand, trades off the sacrifice gain for lower additional phase shift. In addition, the gain control of the scheme depends on external manual voltage mediation, and a digital-to-analog converter (DAC) control module is not integrated, so that the scheme cannot realize high-precision gain control of the VGA; in the scheme of implementing gain control of VGA by DAC, the control bit number of DAC is generally increased to implement high gain precision control, but the design difficulty, cost and power consumption are also greatly increased due to the increase of DAC bit number.
In summary, in the conventional Variable Gain Amplifier (VGA) designed based on the CMOS process, on one hand, the gain control precision is low, and in order to realize high-gain precision control, the number of bits of the analog-to-digital converter (DAC) is generally increased, but due to the increase of the number of bits of the DAC, the design difficulty, the cost and the power consumption are also greatly increased; on the other hand, the additional phase shift caused in the VGA gain change process is large, and the currently adopted low additional phase shift technology is generally realized on the basis of sacrificing the gain. Therefore, the VGA designed based on CMOS process can realize high gain precision control and low additional phase shift without increasing DAC bit number and sacrificing gain.
Disclosure of Invention
The present invention is directed to provide a novel variable gain amplifier with high gain accuracy and low additional phase shift. In the variable gain amplifier structure, firstly, an asymmetric capacitance technology is introduced on the basis of a differential circuit structure; secondly, the on-chip DAC control circuit is matched, so that high-gain precision control can be realized; furthermore, the introduction of the asymmetric capacitance technology can effectively solve the problem of large phase change under a high-gain state caused by different parasitic capacitances of two paths of differential circuits under different biases; on the other hand, the technology also has a gain precision adjusting function, only the size of the asymmetric capacitor needs to be reasonably configured, and high-gain precision control can be realized under the condition that the DAC digit is not increased; therefore, the VGA in the CMOS process is based on the asymmetric capacitance technology, and the problems of large additional phase shift in a high-gain state and high DAC digit requirement in high-gain precision are perfectly solved.
In order to achieve the purpose, the invention adopts the technical scheme that:
a novel high gain precision low additional phase shifted variable gain amplifier comprising: 4 transistors M1-M4, 2 matching capacitors C1 and two matching capacitors C2; the variable gain amplifier is characterized in that a differential structure is adopted, a differential input signal Vin + passes through a matching capacitor C1 and then is input into a grid electrode of a transistor M1, a differential input signal Vin + passes through a matching capacitor C2 and then is input into a grid electrode of a transistor M2, a differential input signal Vin-passes through a matching capacitor C2 and then is input into a grid electrode of a transistor M3, a differential input signal Vin-passes through a matching capacitor C1 and then is input into a grid electrode of a transistor M4, a drain electrode of the transistor M1 is connected with a drain electrode of a transistor M3 and outputs a signal Vout +, a drain electrode of the transistor M2 is connected with a drain electrode of a transistor M4 and outputs a signal Vout-, and source electrodes of the transistors M1-M4; the gates of the transistor M1 and the transistor M4 are connected with a bias resistor in series and then connected with a control voltage VaThe transistor M2 is connected with the control voltage V after being connected with the gate of the transistor M3 in series with a bias resistorb(ii) a The transistors M1-M4 are of the same size, and the capacitance value of the matching capacitor C1 is smaller than that of the matching capacitor C2.
Furthermore, the capacitance value of the matching capacitor C2 is greater than or equal to 1pF, and the capacitance value of the matching capacitor C1 is greater than or equal to 200 fF.
Furthermore, the matching capacitor C1 adopts a plate capacitor structure to reduce the capacitance value deviation caused by the processing error; the matching capacitor C2 adopts an interdigital capacitor structure so as to save the chip area.
The invention has the beneficial effects that:
the invention provides a novel variable gain amplifier with high gain precision and low additional phase shift.A non-symmetric capacitor technology is introduced on the basis of a differential circuit structure, namely the capacitance value of a matching capacitor C1 is smaller than that of a matching capacitor C2; the asymmetric capacitor technology compensates the unbalanced problem caused by different biases of two paths in a differential structure, and the unbalanced problem caused by different biases of the two paths can be completely compensated only by reasonably configuring the capacitance values of the asymmetric capacitors C1 and C2 on the premise that the capacitance value of the matching capacitor C1 is smaller than that of the matching capacitor C2, so that the parasitic capacitors of the two paths are more thoroughly offset, and the design of a Variable Gain Amplifier (VGA) with low additional phase shift in a high-gain state is realized;
on the other hand, the asymmetric capacitors belong to the matching capacitors of the respective paths, different capacitance values cause different impedance matching, and different impedance matching can change the gain of the transistor, so that the gain control of the VGA can be realized by reasonably configuring the capacitance value of the asymmetric capacitor on the premise that the capacitance value of the matching capacitor C1 is smaller than that of the matching capacitor C2, and thus, the higher gain precision control can be realized by using the asymmetric capacitor technology without increasing the number of DAC bits. In summary, the present invention only needs to reasonably configure the capacitance values of C1 and C2, which is equivalent to realize lower additional phase shift and higher gain accuracy control in the high gain state without increasing any design complexity and cost;
in summary, compared with the traditional VGA design, the invention realizes lower additional phase shift in the high-gain state and high-gain precision control under the same DAC digit; the problems that the traditional variable gain amplifier is large in additional phase shift in a high gain state and high in DAC digit requirement under high gain precision are perfectly solved.
Drawings
FIG. 1 is a schematic diagram of the structure of the novel variable gain amplifier with high gain precision and low additional phase shift according to the present invention,
FIG. 2 is a schematic diagram of an on-chip DAC overall control circuit according to an embodiment of the present invention.
FIG. 3 is a graph illustrating the relationship between the capacitance C1 and the circuit stability according to an embodiment of the present invention.
Fig. 4 is a simulation result of a variable gain amplifier based on symmetric capacitors according to an embodiment of the present invention, in which (a) is the gain in different states, and (b) is the phase change in different gains.
Fig. 5 is a simulation result of the variable gain amplifier based on the asymmetric capacitors in the embodiment of the present invention, in which (a) is the gain in different states, and (b) is the phase change in different gains.
Fig. 6 is a Layout of a variable gain amplifier based on asymmetric capacitors in an embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a conventional differential common-source variable-gain amplifier, in which (a) is a simplified circuit schematic diagram, and (b) is a small-signal equivalent circuit model.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
The embodiment provides a novel high-gain precision low-additional-phase-shift Variable Gain Amplifier (VGA), which is based on a CMOS (complementary metal oxide semiconductor) process and realizes high-gain precision control of low additional phase shift and low DAC (digital-to-analog converter) digit in a high-gain state by adopting an asymmetric capacitor and an on-chip integrated DAC (digital-to-analog converter) technology. The schematic diagram of the VGA circuit based on the asymmetric capacitance technology and the schematic diagram of the on-chip DAC overall control circuit are shown in figure 1:
as can be seen from fig. 1, the VGA proposed in this embodiment includes: four transistors M1-M4, two matching capacitors C1 and C2, and VaAnd VbTwo control voltages; the circuit adopts a differential structure, a differential input signal Vin + passes through a matching capacitor C1 and then is input into a gate of a transistor M1, a differential input signal Vin + passes through a matching capacitor C2 and then is input into a gate of a transistor M2, a differential input signal Vin-passes through a matching capacitor C2 and then is input into a gate of a transistor M3, a differential input signal Vin-passes through a matching capacitor C1 and then is input into a gate of a transistor M4, a drain of the transistor M1 is connected with a drain of a transistor M3 and outputs a signal Vout +, a drain of the transistor M2 is connected with a drain of a transistor M4 and outputs a signal Vout-, and sources of the transistors M1-M4 are all grounded; the gates of the transistor M1 and the transistor M4 are connected with a bias resistor in series and then connected with a control voltage VaThe transistor M2 is connected with the control voltage V after being connected with the gate of the transistor M3 in series with a bias resistorb。
In the embodiment, in order to eliminate the problem of phase change caused by parasitic capacitance of a transistor, the VGA design with low additional phase shift based on the CMOS process is realized; on one hand, the four transistors from M1 to M4 are made to have the same size, so that the parasitic capacitance difference between the transistors is reduced; on the other hand, a differential structure is adopted, so that the parasitic capacitance current flow directions of the two transistors are opposite, the cancellation of the parasitic capacitance is realized, the parasitic capacitance of the transistors is further reduced, and the additional phase shift of the VGA is further reduced. Meanwhile, in order to solve the problem that the phase of the VGA is greatly changed in a high gain state, the invention provides an asymmetric capacitor technology, as shown in fig. 1, matching capacitors C1 and C2 of the differential two-way transistors are unequal to form an asymmetric capacitor structure; the asymmetric capacitor compensates the unbalanced problem of the differential structure caused by different biases of the two paths, and the unbalanced problem of the differential two paths caused by different biases can be completely solved only by reasonably configuring the capacitance values of the asymmetric capacitors C1 and C2, so that the VGA design with low additional phase shift in a high-gain state is realized. For the capacitance value configuration of the capacitor C2, in order to obtain better blocking effect, the capacitance value is generally about 1 pF; for the capacitance value configuration of the capacitor C1, on one hand, the compensation effect of the unbalanced problem of the differential structure caused by different two-way bias is determined, and the reasonable value of C1 can minimize the additional phase shift of the VGA in different gain states; on the other hand, depending on the gain accuracy control requirement of the VGA, the higher the required gain accuracy is, the larger the difference between C1 and C2 is; however, the value of C1 cannot be infinitely small, and the stability of the whole circuit is also considered, as shown in fig. 3, when the value of C1 is less than 200fF, the whole circuit is unstable, and the value of C1 needs to be greater than 200 fF; in summary, for the capacitance value configuration of the asymmetric capacitors C1 and C2, C2 is about 1pF, and the value of C1 minimizes the additional phase shift of the VGA and ensures the circuit to be stable.
In order to realize high-gain precision control of VGA, this embodiment further provides a control circuit matched with the Variable Gain Amplifier (VGA), the DAC is integrated on a chip, and the DAC overall control circuit is shown in fig. 2, and includes: an analog current source bias circuit (realizing a constant current source) and a current mirror DAC circuit are arranged in the circuit; total current I of current mirrortotalThe DAC of the PMOS current mirror is controlled by a switch to distribute different IaAnd IbCorrespondingly generating a control voltage VaAnd VbThereby realizing the gain control of the VGA; constant current source Iref and bias VBIASAll are realized in a chip by adopting an analog circuit. Asymmetric capacitance technique oneOn the other hand, different impedance matching is caused because the asymmetric capacitors belong to matching capacitors of respective paths, and different capacitance values cause different impedance matching, and the gain of the transistor is changed due to different impedance matching, so that the gain control of the VGA can be realized by reasonably configuring the capacitance values of the asymmetric capacitors, and the higher gain precision control is realized by using the asymmetric capacitor technology under the condition of not increasing the DAC digits.
The beneficial effects of the invention are explained by combining the simulation results as follows:
as shown in fig. 4, the result of the gain and phase simulation of the conventional VGA designed by using a symmetric capacitor (C1 ═ C2 ═ 1pF), at 27GHz, the VGA achieves a maximum gain of 25.2dB, a maximum additional phase shift of 12.2 °, and a gain accuracy of 0.5 dB; as shown in fig. 5, as a result of the simulation of the gain and the phase of the novel VGA designed for the asymmetric capacitor (C1 ═ 200fF, C2 ═ 1pF) provided in this embodiment, the novel VGA of this embodiment adopts the same circuit structure and the same transistor size as the conventional VGA, and also under 27GHz, the novel VGA of the present invention achieves a maximum gain of 25.5dB, and the maximum additional phase shift is only 4.3 °, which is 65% lower than that of the conventional VGA; under the same DAC control digit, the gain precision of 0.2dB is realized, and the gain precision is improved by 60 percent compared with the gain precision of the traditional VGA.
In summary, compared with the conventional VGA design based on symmetric capacitors, the novel VGA based on asymmetric capacitor technology provided by the present invention realizes lower additional phase shift in the high-gain state without increasing any design complexity and cost, and realizes higher gain precision control without increasing DAC bit number, thereby perfectly solving the problems of large additional phase shift in the high-gain state and high DAC bit number requirement in the high-gain precision.
Fig. 6 shows a layout of the novel VGA with high gain, high precision and low additional phase shift provided by this embodiment, wherein M3 layer and M4 layer are used as ground planes; the gate and the drain of the transistor respectively reach the M9 layer through a via hole, wherein the gate is led out by the M8 layer of metal, and the drain is led out by the M9 layer of metal; the capacitance value of the capacitor C1 is small, and a flat capacitor structure is adopted for reducing the capacitance value deviation caused by processing errors; the capacitance value of the capacitor C2 is large, and an interdigital capacitor structure is adopted for saving the chip area.
While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.
Claims (4)
1. A novel high gain precision low additional phase shifted variable gain amplifier comprising: 4 transistors M1-M4, 2 matching capacitors C1 and two matching capacitors C2; the differential input signal Vin + passes through a matching capacitor C1 and then is input to the gate of a transistor M1, the differential input signal Vin + passes through a matching capacitor C2 and then is input to the gate of a transistor M2, the differential input signal Vin-passes through a matching capacitor C2 and then is input to the gate of a transistor M3, the differential input signal Vin-passes through a matching capacitor C1 and then is input to the gate of a transistor M4, the drain of the transistor M1 is connected with the drain of a transistor M3 and outputs a signal Vout +, the drain of the transistor M2 is connected with the drain of a transistor M4 and outputs a signal Vout-, and the sources of the transistors M1-M4 are all grounded; the gates of the transistor M1 and the transistor M4 are connected with a bias resistor in series and then connected with a control voltage VaThe transistor M2 is connected with the control voltage V after being connected with the gate of the transistor M3 in series with a bias resistorb(ii) a The capacitance value of the matching capacitor C1 is smaller than that of the matching capacitor C2.
2. The variable gain amplifier of claim 1 wherein said transistors M1-M4 are of the same size.
3. The high gain precision low additive phase shift variable gain amplifier of claim 1 wherein said matching capacitor C2 has a capacitance of ≥ 1pF, and said matching capacitor C1 has a capacitance of ≥ 200 fF.
4. The high gain precision low additive phase shift variable gain amplifier of claim 1 wherein said matching capacitor C1 is a plate capacitor structure and said matching capacitor C2 is an interdigital capacitor structure.
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| CN114499426A (en) * | 2021-12-29 | 2022-05-13 | 电子科技大学 | Bidirectional variable gain amplifier based on active cross-coupling structure |
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| CN112737532B (en) | 2022-12-23 |
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