CN112735486A - Audio playing method based on a-law algorithm - Google Patents
Audio playing method based on a-law algorithm Download PDFInfo
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- CN112735486A CN112735486A CN202011526690.6A CN202011526690A CN112735486A CN 112735486 A CN112735486 A CN 112735486A CN 202011526690 A CN202011526690 A CN 202011526690A CN 112735486 A CN112735486 A CN 112735486A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/00007—Time or data compression or expansion
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/00007—Time or data compression or expansion
- G11B2020/00014—Time or data compression or expansion the compressed signal being an audio signal
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Abstract
The invention provides an audio playing method based on an a-law algorithm, which comprises the following steps: s1, converting the sound source file 1 into a sound source file 2 through audio processing software; s2, converting the sound source file 2 into a binary file through binary file synthesis software and burning the binary file into a memory; s3, reading the address and length of the sound source file 2 from the memory; s4, decompressing the sound source by using an A-Law compression algorithm, and putting the decompressed sound source into an audio bus; and S5, finally, transmitting the signal into a power amplifier for playing. The invention compresses the sound source file by half, thus greatly saving the memory space.
Description
Technical Field
The invention relates to the field of audio playing, in particular to an audio playing method based on an a-law algorithm.
Background
During the use of the meter, the situation of insufficient memory often occurs for various reasons: for example, a new language is added when the overseas edition needs to be developed; in this case, it is necessary to compress a part of the content in the memory, and the sound source file is usually compressed.
Disclosure of Invention
The invention aims to at least solve the technical problems in the prior art, and particularly creatively provides an audio playing method based on an a-law algorithm.
In order to achieve the above object, the present invention provides an audio playing method based on an a-law algorithm, comprising:
s1, converting the sound source file 1 into a sound source file 2 through audio processing software;
s2, converting the sound source file 2 into a binary file through binary file synthesis software and burning the binary file into a memory;
s3, reading the address and length of the sound source file 2 from the memory;
s4, decompressing the sound source by using an A-Law compression algorithm, and putting the decompressed sound source into an audio bus;
and S5, finally, transmitting the signal into a power amplifier for playing.
Preferably, the sound source file 1 is in a WAV format, and the sound source file 2 is in an A-Law format;
the audio processing software is GoldWave;
the binary file synthesis software is binding;
the memory is FLASH;
the audio bus is I2S.
Preferably, the sound source file 1 includes: monophonic, at a rate of 16000 Hz.
Preferably, the decompressing comprises:
S-A, A decoding function defines A short integer character pointer dst, an unsigned byte character pointer src and A32-bit integer number len;
S-B, entering a loop, wherein the initial value of a 32-bit shaping number i is 0, and the value of i is equal to the value of i plus one in the last time;
S-C, the value of the unsigned byte-type number alaw is equal to the value of pointer src plus 1;
S-D, alaw equal to 0xD 5;
S-E, the integer sign is equal to alaw and 0x80 is operated according to the bitwise AND operation;
S-F, the integer exponent is equal to alaw and 0x70, and then the integer exponent is shifted to the right by 4 bits after bitwise AND operation;
S-G, the integer data is equal to alaw and 0x0f is operated according to the bitwise AND operation;
S-H, the value of the data is equal to the value of the data which is shifted left by 4 bits;
S-I, the value of the data is equal to the value of the data plus 8;
S-J, if the exponent is not equal to 0, the value of the data is equal to the data plus the value of 0x 100;
S-K, if the exponent is more than 1, the value of the data is equal to the difference value of the data left-shifted exponent minus 1;
S-L, putting each element in the short integer number sign into a pointer dst according to the position; if sign is equal to 0, assigning data to sign; if sign is not equal to 0, assigning-data to sign;
S-M, the value of the pointer dst plus one is equal to sign;
S-N, if i is less than len, executing the step S-B, and if i is not less than len, executing the step S15;
S-O, the cycle is ended.
The invention also discloses a working circuit of the audio playing method based on the a-law algorithm, which comprises the following steps: the power supply module, the microcontroller U1 and the programming port P2;
the power supply module is connected with the programming port P2 and the microcontroller U1,
microcontroller U1 is connected to a programming port P2,
the programming port P2 is used to program the sound source file 2 converted into binary file into the audio playing system,
the data transmission end of the programming port P2 is connected with the data transmission end of the microcontroller U1, the clock end of the programming port P2 is connected with the clock end of the microcontroller U1, the chip selection end of the programming port P2 is connected with the chip selection end of the microcontroller U1, and the reset end of the programming port P2 is connected with the reset end of the microcontroller U1.
Preferably, the method comprises the following steps:
the power end Vccfs of the digital chip U6 and the first end of the capacitor C30 are connected to the power supply Audio _ VCC, the power end Vccf of the digital chip U6 and the first end of the capacitor C31 are connected to the power supply Audio _ Flash _ VCC, the second end of the capacitor C30 and the second end of the capacitor C31 are connected to the power supply ground,
a data input terminal FDI of the digital chip U6 is connected with a first terminal of a resistor R22, a second terminal of the resistor R22 is connected with a data output terminal DO (IO1) of the memory U5, a chip selection terminal FCSB of the digital chip U6 is connected with a first terminal of a resistor R23, and a second terminal of the resistor R23 is connected with a chip selection terminal of the memory U5
The clock terminal FCLK of the digital chip U6 is connected with the first terminal of the resistor R24, the second terminal of the resistor R24 is connected with the clock terminal CLK of the memory U5, the data output terminal FDO of the digital chip U6 is connected with the first terminal of the resistor R25, and the second terminal of the resistor R25 is connected with the data input terminal DO (IO0) of the memory U5;
a serial output end MISO/GPIO1 of a digital chip U6 is connected with a first end of a resistor R26, a second end of the resistor R26 is connected with a sixth end of a JTAG interface P1 and a microcontroller U1, a serial clock input end SCLK of the digital chip U6 is connected with a first end of a resistor R27, a second end of the resistor R27 is connected with a seventh end of a JTAG interface P1 and the microcontroller U1, a selection input end SSB of the digital chip U6 is connected with a first end of the resistor R28, a second end of the resistor R28 is connected with a fourth end of the JTAG interface P1 and the microcontroller U1, a serial input end MOSI/0 of the digital chip U6 is connected with a first end of a resistor R29, and a second end of the resistor R29 is connected with a fifth end of the JTAG interface P1 and the microcontroller U1.
Preferably, the method further comprises the following steps:
an interrupt request terminal INTB/GPIO3 of the digital chip U6 is connected with a first end of a resistor R31 and a third end of a JTAG interface P1, a second end of the resistor R31 and a first end of a capacitor C39 are connected with a power supply A udio _ VCC,
the output state terminal RDY/BSYB/GPIO2 of the digital chip U6 is connected with the second terminal of JTAG interface P1,
the RESET terminal RESET of the digital chip U6 is connected to the first terminal of the resistor R33, the first terminal of the resistor R34, the second terminal of the capacitor C39, and the first terminal of the JTAG interface P1,
a second terminal of the resistor R33 is connected with the microcontroller U1, and a second terminal of the resistor R34 is connected with the power ground;
the intermediate voltage reference terminal VMID of the digital chip U6 is connected to a first terminal of a capacitor C41, a second terminal of a capacitor C41 is connected to power ground,
a power supply terminal VCCD of the digital chip U6, a first terminal of a resistor R21 and a first terminal of a capacitor C32 are connected with a power supply Audio _ VCC, a second terminal of the resistor R21 is connected with a power supply VCC _5V, a second terminal of the capacitor C32, a grounding terminal VSSD of the digital chip U6 and a first terminal of a capacitor C33 are connected with a power supply ground, and a coupling and stabilizing terminal VREG of the digital chip U6 is connected with a second terminal of the capacitor C33.
Preferably, the method further comprises the following steps:
a power supply terminal Vccspk of the digital chip U6, a first end of a capacitor C34, a first end of a capacitor C35, a first end of a capacitor C36 and a first end of an inductor L5 are connected with a power supply AVCC _5V, a second end of an inductor L5 and a first end of a capacitor C37 are connected with a power supply SPKAudio _ VCC,
the power supply terminal Vssspk of the digital chip U6, the second terminal of the capacitor C34, the second terminal of the capacitor C35, the second terminal of the capacitor C36, and the second terminal of the capacitor C37 are connected to the power ground,
the positive output terminal SPK + of the PWM driver of the digital chip U6 is connected to the first terminal of the speaker Bk1 and the first terminal of the transient diode TVS1, the negative output terminal SPK-of the PWM driver of the digital chip U6 is connected to the second terminal of the speaker Bk1 and the first terminal of the transient diode TVS2,
a second terminal of the transient diode TVS1 and a second terminal of the transient diode TVS2 are connected to power ground,
the reference current terminal XTALIN of the digital chip U6 is connected to a first terminal of a resistor R30, a second terminal of the resistor R30 is connected to power ground,
a power supply terminal VCCA of the digital chip U6 is connected to a first terminal of a capacitor C40, a first terminal of a capacitor C38, and a first terminal of a resistor R32, a second terminal of the resistor R32 is connected to a power supply Audio _ VCC,
a ground terminal VSSA of the digital chip U6, a second terminal of the capacitor C40, and a second terminal of the capacitor C38 are connected to a power ground, and a chip PAD terminal PAD of the digital chip U6 is connected to the power ground;
the ninth terminal of the JTAG interface P1 and the tenth terminal of the JTAG interface P1 are connected to the power ground, and the eighth terminal of the JTAG interface P1 is connected to the power VCC _ 5V.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
the invention makes the sound source file compressed by half, the compression ratio is 1: and 2, the memory space is greatly saved.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a data flow diagram of the present invention before modification;
FIG. 2 is a data flow diagram of the present invention before modification;
FIG. 3 is a diagram of the decompression code of the present invention;
FIG. 4 is a circuit diagram of memory U5 of the present invention;
FIG. 5 is a circuit diagram of the digital chip U6 of the present invention;
FIG. 6 is a circuit diagram of JTAG interface P1 of the present invention;
fig. 7 is a circuit diagram of the speaker Bk1 of the present invention;
FIG. 8 is a circuit diagram of microcontroller U1 of the present invention;
FIG. 9 is a circuit diagram of the power module of the present invention;
fig. 10 is a partial circuit diagram of the power module of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
The invention provides an audio playing method based on an a-law algorithm, as shown in figure 1:
before software modification, the WAV sound source is converted into a binary file through a binding tool and is burnt into FLASH,
then the sound source data is put into I2S, and finally the sound source data is transmitted into a power amplifier to be played.
After software modification, as shown in fig. 2:
s1, converting the sound source file 1 into a sound source file 2 through audio processing software;
s2, converting the sound source file 2 into a binary file through binary file synthesis software and burning the binary file into a memory;
s3, reading the address and length of the sound source file 2 from the memory;
s4, decompressing the sound source by using an A-Law compression algorithm, and putting the decompressed sound source into an audio bus;
and S5, finally, transmitting the signal into a power amplifier for playing.
Preferably, the sound source file 1 is in a WAV format, and the sound source file 2 is in an A-Law format;
the audio processing software is GoldWave;
the binary file synthesis software is binding;
the memory is FLASH;
the audio bus is I2S.
Preferably, the sound source file 1 includes: monophonic, at a rate of 16000 Hz.
Preferably, as shown in fig. 3, the decompressing includes:
S-A, A decoding function defines A short integer character pointer dst, an unsigned byte character pointer src and A32-bit integer number len;
S-B, entering circulation, setting the initial value of a 32-bit shaping number i to be 0, and setting the value of i in each circulation to be equal to the value of i in the last time plus one;
S-C, the value of the unsigned byte-type number alaw is equal to the value of pointer src plus 1;
S-D, alaw equal to 0xD 5;
S-E, the integer sign is equal to alaw and 0x80 is operated according to the bitwise AND operation;
S-F, the integer exponent is equal to alaw and 0x70, and then the integer exponent is shifted to the right by 4 bits after bitwise AND operation;
S-G, the integer data is equal to alaw and 0x0f is operated according to the bitwise AND operation;
S-H, the value of the data is equal to the value of the data which is shifted left by 4 bits;
S-I, the value of the data is equal to the value of the data plus 8;
S-J, if the exponent is not equal to 0, the value of the data is equal to the data plus the value of 0x 100;
S-K, if the exponent is more than 1, the value of the data is equal to the difference value of the data left-shifted exponent minus 1;
S-L, putting each element in the short integer number sign into a pointer dst according to the position; if sign is equal to 0, assigning data to sign; if sign is not equal to 0, assigning the-data, namely the negative number of the data, to the sign;
S-M, the value of the pointer dst plus one is equal to sign;
S-N, if i is less than len, executing the step S-B, and if i is not less than len, executing the step S15;
S-O, the cycle is ended.
As shown in fig. 4-10, the present invention also discloses a working circuit of an audio playing method based on an a-law algorithm, comprising: the device comprises a power supply module, a microcontroller U1, a programming port P2, a memory U5, a digital chip U6, a JTAG interface P1 and a loudspeaker Bk 1;
the power module is connected with a microcontroller U1, a programming port P2, a memory U5, a digital chip U6 and a JTAG interface P1, the microcontroller U1 is connected with a programming port P2, the digital chip U6, the memory U5, a JTAG interface P1 and a loudspeaker Bk1, and the digital chip U6 is connected with the memory U5, the JTAG interface P1 and the loudspeaker Bk 1.
Preferably, the method comprises the following steps:
the power end Vccfs of the digital chip U6 and the first end of the capacitor C30 are connected to the power supply Audio _ VCC, the power end Vccf of the digital chip U6 and the first end of the capacitor C31 are connected to the power supply Audio _ Flash _ VCC, the second end of the capacitor C30 and the second end of the capacitor C31 are connected to the power supply ground,
a data input terminal FDI of the digital chip U6 is connected with a first terminal of a resistor R22, a second terminal of the resistor R22 is connected with a data output terminal DO (IO1) of the memory U5, a chip selection terminal FCSB of the digital chip U6 is connected with a first terminal of a resistor R23, and a second terminal of the resistor R23 is connected with a chip selection terminal of the memory U5
The clock terminal FCLK of the digital chip U6 is connected to the first terminal of the resistor R24, the second terminal of the resistor R24 is connected to the clock terminal CLK of the memory U5, and the data output terminal FDO of the digital chip U6 is connected to the first terminal of the resistor R25The second end of the resistor R25 is connected with the data input end DO (IO0) of the memory U5;
a serial output end MISO/GPIO1 of a digital chip U6 is connected with a first end of a resistor R26, a second end of the resistor R26 is connected with a sixth end of a JTAG interface P1 and a microcontroller U1, a serial clock input end SCLK of the digital chip U6 is connected with a first end of a resistor R27, a second end of the resistor R27 is connected with a seventh end of a JTAG interface P1 and the microcontroller U1, a selection input end SSB of the digital chip U6 is connected with a first end of the resistor R28, a second end of the resistor R28 is connected with a fourth end of the JTAG interface P1 and the microcontroller U1, a serial input end MOSI/0 of the digital chip U6 is connected with a first end of a resistor R29, and a second end of the resistor R29 is connected with a fifth end of the JTAG interface P1 and the microcontroller U1.
The model of the microcontroller U1 is FS32K142HAT0VLHT, the model of the memory U5 is W25Q16DVSSAG, the model of the digital chip U6 is ISD15D00YY, the resistances of the resistor R22, the resistor R23, the resistor R24, the resistor R25, the resistor R26, the resistor R27, the resistor R28 and the resistor R29 are 22 Ω, the capacitance of the capacitor C30 is 100nF, and the capacitance of the capacitor C31 is 1 uF.
Preferably, the method further comprises the following steps:
an interrupt request terminal INTB/GPIO3 of the digital chip U6 is connected with a first end of a resistor R31 and a third end of a JTAG interface P1, a second end of the resistor R31 and a first end of a capacitor C39 are connected with a power supply A udio _ VCC,
the output state terminal RDY/BSYB/GPIO2 of the digital chip U6 is connected with the second terminal of JTAG interface P1,
the RESET terminal RESET of the digital chip U6 is connected to the first terminal of the resistor R33, the first terminal of the resistor R34, the second terminal of the capacitor C39, and the first terminal of the JTAG interface P1,
a second terminal of the resistor R33 is connected with the microcontroller U1, and a second terminal of the resistor R34 is connected with the power ground;
the intermediate voltage reference terminal VMID of the digital chip U6 is connected to a first terminal of a capacitor C41, a second terminal of a capacitor C41 is connected to power ground,
a power supply terminal VCCD of the digital chip U6, a first terminal of a resistor R21 and a first terminal of a capacitor C32 are connected with a power supply Audio _ VCC, a second terminal of the resistor R21 is connected with a power supply VCC _5V, a second terminal of the capacitor C32, a grounding terminal VSSD of the digital chip U6 and a first terminal of a capacitor C33 are connected with a power supply ground, and a coupling and stabilizing terminal VREG of the digital chip U6 is connected with a second terminal of the capacitor C33.
The resistance values of the resistor R31 and the resistor R34 are 10K, the resistance value of the resistor R33 is 22 omega, the capacitance value of the capacitor C39 is 100nF, and the capacitance value of the capacitor C41 is 4.7 uF.
Preferably, the method further comprises the following steps:
a power supply terminal Vccspk of the digital chip U6, a first end of a capacitor C34, a first end of a capacitor C35, a first end of a capacitor C36 and a first end of an inductor L5 are connected with a power supply AVCC _5V, a second end of an inductor L5 and a first end of a capacitor C37 are connected with a power supply SPKAudio _ VCC,
the power supply terminal Vssspk of the digital chip U6, the second terminal of the capacitor C34, the second terminal of the capacitor C35, the second terminal of the capacitor C36, and the second terminal of the capacitor C37 are connected to the power ground,
the positive output terminal SPK + of the PWM driver of the digital chip U6 is connected to the first terminal of the speaker Bk1 and the first terminal of the transient diode TVS1, the negative output terminal SPK-of the PWM driver of the digital chip U6 is connected to the second terminal of the speaker Bk1 and the first terminal of the transient diode TVS2,
a second terminal of the transient diode TVS1 and a second terminal of the transient diode TVS2 are connected to power ground,
the reference current terminal XTALIN of the digital chip U6 is connected to a first terminal of a resistor R30, a second terminal of the resistor R30 is connected to power ground,
a power supply terminal VCCA of the digital chip U6 is connected to a first terminal of a capacitor C40, a first terminal of a capacitor C38, and a first terminal of a resistor R32, a second terminal of the resistor R32 is connected to a power supply Audio _ VCC,
a ground terminal VSSA of the digital chip U6, a second terminal of the capacitor C40, and a second terminal of the capacitor C38 are connected to a power ground, and a chip PAD terminal PAD of the digital chip U6 is connected to the power ground;
the ninth terminal of the JTAG interface P1 and the tenth terminal of the JTAG interface P1 are connected to the power ground, and the eighth terminal of the JTAG interface P1 is connected to the power VCC _ 5V.
The model of the loudspeaker Bk1 is KPB3642SP1-8222, the model of the inductor L5 is MPZ1608S601ATD25, the models of the transient diode TVS1 and the transient diode TVS2 are S-LESD8LL5.0CT5G, the capacitance values of the capacitor C32, the capacitor C34, the capacitor C35, the capacitor C37, the capacitor C38 and the capacitor C40 are 100nF, and the capacitance value of the capacitor C36 is 22 uF.
Preferably, the power supply module includes:
battery power supply Battery _ IN is connected with a first end of a transient diode TVS6, a first end of a capacitor C68, a first end of a diode D2 and a first end of a diode D3, a second end of the transient diode TVS6 and a second end of a capacitor C68 are connected with a power ground, a second end of a diode D2 and a second end of a diode D3 are connected with a second end of a diode D4, a second end of a diode D5, a first end of a capacitor C65, a first end of a capacitor C64 and a first end of an inductor L6, and a second end of a diode D2 outputs power supply P _ Battery outwards; the second end of the capacitor C65 and the second end of the capacitor C64 are connected to the power ground, and the second end of the inductor L6 outputs a power supply B _ Battery to the outside;
the ignition power supply IGN _ IN is connected with a first end of a transient diode TVS7, a first end of a capacitor C69, a first end of a diode D4, a first end of a diode D5 and a first end of a diode D6, a second end of a transient diode TVS7 and a second end of a capacitor C69 are connected with the power ground, a second end of a diode D6 is connected with a first end of the capacitor C70 and a first end of a resistor R164, and a second end of a diode D6 outputs the ignition power supply P _ IGN outwards; a second terminal of the capacitor C70 and a second terminal of the resistor R164 are connected to power ground.
The transient diodes TVS6 and TVS7 are S-SMBJ26CA, the diodes D2, D3, D4, D5 and D6 are S-FMAF407, the capacitor C65 is VEJ471M1ETR-1010L, and the inductor L6 is VLS6045 EX-220M-H.
Preferably, the power supply module further includes:
a power supply B _ Batttery is connected with a first end of a capacitor C22, a first end of a capacitor C23, a first end of a capacitor C24, a first end of a resistor R17 and a power supply input end VIN of a voltage stabilizer U3, a second end of a resistor R17 is connected with an enable end EN of the voltage stabilizer U3, a second end of a resistor R16 and a second end of a capacitor C16, a first end of a resistor R16 and a first end of a capacitor C16 are connected with a power supply ground, a resistor timing end RT/SYNC of a voltage stabilizer U3 is connected with a first end of a resistor RT1, a soft start control end SS of a voltage stabilizer U3 is connected with a first end of a resistor R221 and a first end of a capacitor Css1, a second end of a capacitor C1 and a first end of a capacitor C28, a second end of a capacitor C22, a second end of a capacitor C23, a second end of a capacitor C24, a second end of a resistor RT1, a second end of a heat dissipation end of a CsRT 3, a Thermal terminal Thermal Pad, a power supply;
a second end of the capacitor C28 is connected to a second end of the resistor R221, a bootstrap terminal BOOT of the regulator U3 is connected to a second end of the resistor R15, a first end of the resistor R15 is connected to a first end of the capacitor C17, a regulator switch output terminal SW of the regulator U3 is connected to a second end of the capacitor C17, a first end of the inductor L3, and a first end of the diode D1, a second end of the inductor L3 is connected to a first end of the capacitor C18, a first end of the capacitor C19, a first end of the capacitor C20, a first end of the capacitor C21, a first end of the resistor RFBT1, and a first end of the capacitor C27, and a second end of the inductor L3 outputs a power VCC _ 5V; a second terminal of the diode D1, a second terminal of the capacitor C18, a second terminal of the capacitor C19, a second terminal of the capacitor C20, and a second terminal of the capacitor C21 are connected to the power ground, and a feedback input terminal FB of the voltage regulator U3 is connected to a second terminal of the resistor RFBT1, a first terminal of the resistor RFBT2, and a second terminal of the capacitor C27.
The input power supply B _ Battery maintains a stable output power supply VCC _5V through the voltage stabilizer.
The model of the voltage stabilizer U3 is LMR14030SSQDDARQ1, the model of the diode D1 is NRVBAF440T3G, the model of the capacitor C22 is VEJ471M1ETR-1010L, and the model of the inductor L3 is VLS6045 EX-100M-H.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (5)
1. An audio playing method based on an a-law algorithm is characterized by comprising the following steps:
s1, converting the sound source file 1 into a sound source file 2 through audio processing software;
s2, converting the sound source file 2 into a binary file through binary file synthesis software and burning the binary file into a memory;
s3, reading the address and length of the sound source file 2 from the memory;
s4, decompressing the sound source by using an A-Law compression algorithm, and putting the decompressed sound source into an audio bus;
and S5, finally, transmitting the signal into a power amplifier for playing.
2. The audio playing method based on the a-law algorithm as claimed in claim 1, comprising:
the sound source file 1 is in a WAV format, and the sound source file 2 is in an A-Law format;
the audio processing software is GoldWave;
the binary file synthesis software is binding;
the memory is FLASH;
the audio bus is I2S.
3. The audio playing method based on a-law algorithm as claimed in claim 1, wherein the audio source file 1 comprises: monophonic, at a rate of 16000 Hz.
4. The audio playing method based on the a-law algorithm as claimed in claim 1, wherein the decompressing comprises:
S-A, A decoding function defines A short integer character pointer dst, an unsigned byte character pointer src and A32-bit integer number len;
S-B, entering circulation, setting the initial value of a 32-bit shaping number i to be 0, and setting the value of i in each circulation to be equal to the value of i in the last time plus one;
S-C, the value of the unsigned byte-type number alaw is equal to the value of pointer src plus 1;
S-D, alaw equal to 0xD 5;
S-E, the integer sign is equal to alaw and 0x80 is operated according to the bitwise AND operation;
S-F, the integer exponent is equal to alaw and 0x70, and then the integer exponent is shifted to the right by 4 bits after bitwise AND operation;
S-G, the integer data is equal to alaw and 0x0f is operated according to the bitwise AND operation;
S-H, the value of the data is equal to the value of the data which is shifted left by 4 bits;
S-I, the value of the data is equal to the value of the data plus 8;
S-J, if the exponent is not equal to 0, the value of the data is equal to the data plus the value of 0x 100;
S-K, if the exponent is more than 1, the value of the data is equal to the difference value of the data left-shifted exponent minus 1;
S-L, putting each element in the short integer number sign into a pointer dst according to the position; if sign is equal to 0, assigning data to sign; if sign is not equal to 0, assigning-data to sign;
S-M, the value of the pointer dst plus one is equal to sign;
S-N, if i is less than len, executing the step S-B, and if i is not less than len, executing the step S15;
S-O, the cycle is ended.
5. The operating circuit of an audio playing method based on an a-law according to any one of claims 1 to 4, characterized in that it comprises: the power supply module, the microcontroller U1 and the programming port P2;
the power supply module is connected with the programming port P2 and the microcontroller U1,
microcontroller U1 is connected to a programming port P2,
the programming port P2 is used to program the sound source file 2 converted into binary file into the audio playing system,
the data transmission end of the programming port P2 is connected with the data transmission end of the microcontroller U1, the clock end of the programming port P2 is connected with the clock end of the microcontroller U1, the chip selection end of the programming port P2 is connected with the chip selection end of the microcontroller U1, and the reset end of the programming port P2 is connected with the reset end of the microcontroller U1.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0057753A1 (en) * | 1981-02-09 | 1982-08-18 | Siemens Aktiengesellschaft | Method of converting linear PCM words into non-linear PCM words and reversely non-linear PCM words into linear PCM words according to a 13 segments characteristic obeying the A-law |
| KR20030038095A (en) * | 2001-11-08 | 2003-05-16 | 엘지전자 주식회사 | Method and apparatus for recording announcement message of electronic exchange |
| US20070206676A1 (en) * | 2006-03-01 | 2007-09-06 | Tatsuji Yamazaki | Data processing apparatus, data processing method, data processing program, data structure, recording medium, reproducing apparatus, reproducing method, and reproducing program |
| CN101534308A (en) * | 2009-03-20 | 2009-09-16 | 中兴通讯股份有限公司 | Voice data processing method and system |
| CN201805219U (en) * | 2010-05-10 | 2011-04-20 | 侯民 | Storage battery protector provided with time control function |
| CN102479233A (en) * | 2010-11-30 | 2012-05-30 | 腾讯科技（北京）有限公司 | Audio information storage method and device based on Adobe Flash software |
| CN202713142U (en) * | 2012-03-07 | 2013-01-30 | 北京经纬恒润科技有限公司 | Power supply filtering protection circuit |
| CN104952469A (en) * | 2014-03-31 | 2015-09-30 | 联发科技（新加坡）私人有限公司 | Audio file processing method and player |
| CN105702272A (en) * | 2016-01-12 | 2016-06-22 | 深圳市德赛工业研究院有限公司 | Audio play equipment |
| CN106921609A (en) * | 2015-12-25 | 2017-07-04 | 中兴通讯股份有限公司 | Calling playback control method and device |
| CN107484077A (en) * | 2017-09-28 | 2017-12-15 | 广州国光音频科技有限公司 | A kind of implementation method of automobile audio Karaoke |
| CN111122960A (en) * | 2020-01-12 | 2020-05-08 | 东莞锐视光电科技有限公司 | Circuit and method for multi-channel detection of branch current of LED driving circuit |
| CN210776655U (en) * | 2019-12-27 | 2020-06-16 | 广东旭龙物联科技股份有限公司 | Multi-serial port burner |
| CN211577331U (en) * | 2019-10-28 | 2020-09-25 | 深圳米飞泰克科技有限公司 | Testing device for I2S audio bus power amplifier decoding chip |
-
2020
- 2020-12-22 CN CN202011526690.6A patent/CN112735486B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0057753A1 (en) * | 1981-02-09 | 1982-08-18 | Siemens Aktiengesellschaft | Method of converting linear PCM words into non-linear PCM words and reversely non-linear PCM words into linear PCM words according to a 13 segments characteristic obeying the A-law |
| KR20030038095A (en) * | 2001-11-08 | 2003-05-16 | 엘지전자 주식회사 | Method and apparatus for recording announcement message of electronic exchange |
| US20070206676A1 (en) * | 2006-03-01 | 2007-09-06 | Tatsuji Yamazaki | Data processing apparatus, data processing method, data processing program, data structure, recording medium, reproducing apparatus, reproducing method, and reproducing program |
| CN101534308A (en) * | 2009-03-20 | 2009-09-16 | 中兴通讯股份有限公司 | Voice data processing method and system |
| CN201805219U (en) * | 2010-05-10 | 2011-04-20 | 侯民 | Storage battery protector provided with time control function |
| CN102479233A (en) * | 2010-11-30 | 2012-05-30 | 腾讯科技（北京）有限公司 | Audio information storage method and device based on Adobe Flash software |
| CN202713142U (en) * | 2012-03-07 | 2013-01-30 | 北京经纬恒润科技有限公司 | Power supply filtering protection circuit |
| CN104952469A (en) * | 2014-03-31 | 2015-09-30 | 联发科技（新加坡）私人有限公司 | Audio file processing method and player |
| US20150277853A1 (en) * | 2014-03-31 | 2015-10-01 | Mediatek Singapore Pte. Ltd. | Audio file processing method and player using the same |
| CN106921609A (en) * | 2015-12-25 | 2017-07-04 | 中兴通讯股份有限公司 | Calling playback control method and device |
| CN105702272A (en) * | 2016-01-12 | 2016-06-22 | 深圳市德赛工业研究院有限公司 | Audio play equipment |
| CN107484077A (en) * | 2017-09-28 | 2017-12-15 | 广州国光音频科技有限公司 | A kind of implementation method of automobile audio Karaoke |
| CN211577331U (en) * | 2019-10-28 | 2020-09-25 | 深圳米飞泰克科技有限公司 | Testing device for I2S audio bus power amplifier decoding chip |
| CN210776655U (en) * | 2019-12-27 | 2020-06-16 | 广东旭龙物联科技股份有限公司 | Multi-serial port burner |
| CN111122960A (en) * | 2020-01-12 | 2020-05-08 | 东莞锐视光电科技有限公司 | Circuit and method for multi-channel detection of branch current of LED driving circuit |
Non-Patent Citations (2)
| Title |
|---|
| ITEYE_13493: "从认识WAV PCM A LAW MuLaw入门音频世界", 《HTTPSBLOG.CSDN.NETITEYE_13493ARTICLEDETAILS81785078》 * |
| 王心水: "语音信号的A律编解码的DSP实现", 《电子技术研发》 * |
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