CN211577331U - Testing device for I2S audio bus power amplifier decoding chip - Google Patents
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Abstract
The utility model belongs to the technical field of electronics, and discloses a testing device of an I2S audio bus power amplifier decoding chip, which is used for testing the decoding chip to be tested and comprises a tester, an encoding circuit and a differential signal processing circuit; the tester generates and outputs an analog audio signal; the coding circuit converts the received analog audio signal into an I2S audio signal and outputs the audio signal to a decoding chip to be detected; the decoding chip to be tested generates a pair of differential audio signals according to the I2S audio signals; the differential signal processing circuit superposes the differential audio signals to generate superposed signals; the tester obtains the characteristic parameters of the decoding chip to be tested according to the superposed signals; therefore, important parameter tests such as output power, gain, harmonic distortion, signal-to-noise ratio, left and right sound channel isolation and the like of the decoding chip to be tested are realized, and the test accuracy of the chip is improved.
Description
Technical Field
The utility model belongs to the technical field of the electron, especially, relate to a testing arrangement of I2S audio frequency bus power amplifier decoding chip.
Background
The traditional testing device for the I2S audio bus power amplifier decoding chip comprises an external interface, a D/A conversion circuit, a testing interface, a memory and a transmission interface, wherein the external interface is used for receiving an external coded audio/video code stream to the decoding chip to be tested; the test interface is communicated with the tested decoding chip; the video D/A conversion circuit converts the video digital signal decoded by the test decoding chip into a video analog signal and outputs the video analog signal; the audio D/A conversion circuit converts the audio digital signal decoded by the test decoding chip into an audio analog signal and outputs the audio analog signal; the memory is used for being used by the operation of the decoding chip to be tested; the transmission interface is used for transmitting the audio/video analog signal output by the D/A conversion circuit to the outside for display or playing.
However, whether the function of the I2S audio bus power amplifier decoding chip is normal can only be judged through external display or playing, and the characteristic parameters of the I2S audio bus power amplifier decoding chip cannot be tested.
Therefore, the conventional testing device for the I2S audio bus power amplifier decoding chip has the defect that whether the function of the chip is normal is judged only through external display or playing, so that the characteristic parameters of the chip cannot be tested.
SUMMERY OF THE UTILITY MODEL
The utility model provides a testing arrangement of I2S audio frequency bus power amplifier chip of decoding aims at solving whether normal only through the function that outside demonstration or broadcast judge the chip that traditional I2S audio frequency bus power amplifier chip of decoding's testing arrangement exists to lead to the unable problem of testing the characteristic parameter to the chip.
The utility model discloses a test device of I2S audio bus power amplifier decoding chip, which is used for testing the decoding chip to be tested and comprises a tester, an encoding circuit and a differential signal processing circuit;
the tester is configured to generate and output an analog audio signal; the coding circuit is connected with the tester, converts the received analog audio signal into an I2S audio signal and outputs the audio signal to the decoding chip to be tested; the decoding chip to be tested generates a pair of differential audio signals according to the I2S audio signals; the differential signal processing circuit is connected with the decoding chip to be detected and is used for superposing the differential audio signals to generate superposed signals; the tester is connected with the differential signal processing circuit and obtains the characteristic parameters of the decoding chip to be tested according to the superposed signals.
In one embodiment, the apparatus for testing the I2S audio bus power amplifier decoding chip further includes:
the first filter circuit is connected with the decoding chip to be detected and used for filtering the differential audio signal;
the differential signal processing circuit is connected to the first filter circuit, and is specifically configured to superimpose the filtered differential audio signals to generate a superimposed signal.
In one embodiment, the first filter circuit comprises a first inductor, a second inductor, a first capacitor and a second capacitor;
the first end of the first inductor and the first end of the first capacitor jointly form a first differential audio signal input end of the first filter circuit, the first end of the second inductor and the first end of the first capacitor jointly form a first differential audio signal output end of the first filter circuit, the first end of the second inductor and the first end of the second capacitor jointly form a second differential audio signal output end of the first filter circuit, and the second end of the first capacitor and the second end of the second capacitor are jointly connected to a power ground.
In one embodiment, the apparatus for testing the I2S audio bus power amplifier decoding chip further includes:
the second filtering module is connected with the decoding chip to be detected and used for filtering a power supply to generate a first power supply;
and the decoding chip to be tested generates the pair of differential audio signals according to the first power supply and the I2S audio signals.
In one embodiment, the second filter circuit comprises a third capacitor and a fourth capacitor;
the first end of the third capacitor and the first end of the fourth capacitor jointly form an input end and an output end of the second filter circuit, and the second end of the third capacitor and the second end of the fourth capacitor are connected to a power ground in common.
In one embodiment, the encoding circuit comprises an audio analog-digital converter, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;
the master clock end of the audio analog-digital converter, the first end of the first resistor and the first end of the second resistor jointly form an analog audio signal input end of the coding circuit, the second end of the first resistor is connected with the first end of the ninth capacitor, the second end of the ninth capacitor is connected with the right channel analog input end of the audio analog-digital converter, the second end of the second resistor is connected with the first end of the tenth capacitor, the second end of the tenth capacitor is connected with the left channel analog input end of the audio analog-digital converter, the static voltage end of the audio analog-digital converter is connected with the first ends of the eleventh capacitor and the twelfth capacitor, and the positive phase reference voltage end of the audio analog-digital converter is connected with the first ends of the fifth capacitor and the sixth capacitor, an audio serial data output end of the audio analog-digital converter is connected with a first end of the seventh capacitor, a first end of the eighth capacitor, a first end of the third resistor and a first end of the fourth resistor, a serial clock end of the audio analog-digital converter is connected with a first end of the fifth resistor, left and right channel clock ends of the audio analog-digital converter are connected with a first end of the sixth resistor, a second end of the fourth resistor, a second end of the fifth resistor and a second end of the sixth resistor jointly form an I2S audio signal output end of the coding circuit, a ground end of the audio analog-digital converter, a second end of the fifth capacitor, a second end of the sixth capacitor, a second end of the seventh capacitor, a second end of the eighth capacitor, a second end of the eleventh capacitor and a second end of the twelfth capacitor are commonly connected to a power ground, and the second end of the third resistor is connected with a second power supply.
In one embodiment, the I2S left and right channel frame clock end of the decoding chip to be tested, the I2S bit clock end of the decoding chip to be tested, and the I2S serial data end of the decoding chip to be tested together form an I2S audio signal input end of the decoding chip to be tested, the positive output end of the decoding chip to be tested is a first differential audio signal output end of the decoding chip to be tested, the negative output end of the decoding chip to be tested is a second differential audio signal output end of the decoding chip to be tested, the power supply end of the decoding chip to be tested is connected with a first power supply, and the ground end of the decoding chip to be tested is connected with a power ground; and the control end of the decoding chip to be detected is the control signal input end of the decoding chip to be detected.
In one embodiment, the differential signal processing circuit comprises an audio differential signal processor, a thirteenth capacitor and a fourteenth capacitor;
the positive power supply end of the audio differential signal processor is connected with the third power supply and the first end of the fourteenth capacitor, the negative power supply end of the audio differential signal processor is connected with the fourth power supply and the first end of the thirteenth capacitor, the positive phase input end of the audio differential signal processor and the reverse phase input end of the audio differential signal processor jointly form a differential audio signal input end of the differential signal processing circuit, the output end of the audio differential signal processor and the detection end of the audio differential signal processor jointly form a superposed signal output end of the differential signal processing circuit, and the reference voltage end of the audio differential signal processor, the second end of the fourteenth capacitor and the second end of the thirteenth capacitor are jointly connected with a power ground.
In one embodiment, the tester is the TR6850S tester.
The embodiment of the utility model generates and outputs analog audio signals through the tester; the coding circuit converts the received analog audio signal into an I2S audio signal and outputs the audio signal to a decoding chip to be detected; the decoding chip to be tested generates a pair of differential audio signals according to the I2S audio signals; the differential signal processing circuit superposes the differential audio signals to generate superposed signals; the tester obtains the characteristic parameters of the decoding chip to be tested according to the superposed signals; therefore, important parameter tests such as output power, gain, harmonic distortion, signal-to-noise ratio, left and right sound channel isolation and the like of the decoding chip to be tested are realized, and the test accuracy of the chip is improved.
Drawings
In order to more clearly illustrate the technical utility model in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a block diagram of a testing apparatus for an I2S audio bus power amplifier decoding chip according to an embodiment of the present invention;
fig. 2 is another module structure diagram of the testing apparatus for I2S audio bus power amplifier decoding chip according to the embodiment of the present invention;
fig. 3 is another module structure diagram of the testing apparatus for I2S audio bus power amplifier decoding chip according to the embodiment of the present invention;
fig. 4 is a circuit diagram of an example of a testing apparatus for an I2S audio bus power amplifier decoding chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Fig. 1 shows a module structure of a testing apparatus for an I2S audio bus power amplifier decoding chip provided by an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment of the present invention are shown, and detailed descriptions are as follows:
the testing device of the I2S audio bus power amplifier decoding chip is used for testing the decoding chip 03 to be tested, and the testing device of the I2S audio bus power amplifier decoding chip comprises a tester 01, an encoding circuit 02 and a differential signal processing circuit 04.
In a specific implementation, tester 01 may be a TR6850S tester.
The test instrument 01 may specifically generate and output an analog audio signal as follows: a test program is compiled by relying on a waveform generator board card configured by a TR6850S tester, so that the TR6850S tester outputs a sinusoidal signal with the frequency of 1KHZ and the effective value of 0.25V as an analog audio signal; meanwhile, a vector program is programmed to generate a square wave with the frequency of 12MHZ and the amplitude of 3.3V as a main clock of sampling and digital filtering of the coding circuit 02 by relying on a TR6850S tester.
In one embodiment, the characteristic parameters include output power, gain, harmonic distortion, signal-to-noise ratio, and left-right channel isolation.
As shown in fig. 2, the testing apparatus for the I2S audio bus power amplifier decoding chip further includes a first filter circuit 05.
The first filter circuit 05 is connected with the decoding chip 03 to be tested and is used for filtering the differential audio signal; the differential signal processing circuit 04 is connected to the first filter circuit 05, and is specifically configured to superimpose the filtered differential audio signals to generate a superimposed signal.
Since the output of the decoding chip 03 to be tested is a digital modulation signal, and the sampling of the digitizer card configured in the TR6850S tester can only input a sinusoidal analog signal, it must be converted into a sinusoidal analog signal for the final function test, so a first filter circuit 05 (such as an LC low-pass filter) is provided to realize the function.
As shown in fig. 3, the testing apparatus for the I2S audio bus power amplifier decoding chip further includes a second filtering module 06.
The second filtering module 06 is connected to the to-be-detected decoding chip 03 and configured to filter the power supply to generate a first power supply; the decoding chip 03 to be tested generates a differential audio signal according to the first power supply and the I2S audio signal.
Fig. 4 shows an example circuit structure of a testing apparatus for an I2S audio bus power amplifier decoding chip provided in an embodiment of the present invention, which only shows the relevant parts of the embodiment of the present invention for convenience of description, and the detailed description is as follows:
the first filter circuit 05 includes a first inductor L1, a second inductor L2, a first capacitor C1, and a second capacitor C2.
The first end of the first inductor L1 is a first differential audio signal input end of the first filter circuit 05, the second end of the first inductor L1 and the first end of the first capacitor C1 jointly form a first differential audio signal output end of the first filter circuit 05, the first end of the second inductor L2 is a second differential audio signal input end of the first filter circuit 05, the second end of the second inductor L2 and the first end of the second capacitor C2 jointly form a second differential audio signal output end of the first filter circuit 05, and the second end of the first capacitor C1 and the second end of the second capacitor C2 are jointly connected to the power ground.
The second filter circuit comprises a third capacitor C3 and a fourth capacitor C4.
The first end of the third capacitor C3 and the first end of the fourth capacitor C4 form the input/output end of the second filter circuit, and the second end of the third capacitor C3 and the second end of the fourth capacitor C4 are connected to the power ground in common.
The encoding circuit 02 includes an audio analog-digital converter U1, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.
The master clock terminal MCLK of the audio adc U1, the first terminal of the first resistor R1 and the first terminal of the second resistor R2 together form an analog audio signal input terminal of the encoding circuit 02, the second terminal of the first resistor R1 is connected to the first terminal of a ninth capacitor C9, the second terminal of the ninth capacitor C9 is connected to the right channel analog input terminal alnr of the audio adc U1, the second terminal of the second resistor R2 is connected to the first terminal of a tenth capacitor C10, the second terminal of the tenth capacitor C10 is connected to the left channel analog input terminal alnl of the audio adc U1, the static voltage terminal VQ of the audio adc U1 is connected to the first terminal of the eleventh capacitor C11 and the first terminal of the twelfth capacitor C12, the positive-phase reference voltage terminal FILT + of the audio adc U1 is connected to the first terminal of the fifth capacitor C5 and the first terminal of the sixth capacitor C6, and the serial data output terminal SDOUT of the audio adc U1 is connected to the seventh serial data output terminal sdc 36 of the audio adc U7, A first end of the eighth capacitor C8, a first end of the third resistor R3, and a first end of the fourth resistor R4 are connected, a serial clock end SCLK of the audio adc U1 is connected to a first end of the fifth resistor R5, a left-right channel clock end LRCLK of the audio adc U1 is connected to a first end of the sixth resistor R6, a second end of the fourth resistor R4, a second end of the fifth resistor R5, and a second end of the sixth resistor R6 together form an I2S audio signal output terminal of the encoder circuit 02, a ground terminal GND of the audio adc U1, a second end of the fifth capacitor C5, a second end of the sixth capacitor C6, a second end of the seventh capacitor C7, a second end of the eighth capacitor C8, a second end of the eleventh capacitor C11, and a second end of the twelfth capacitor C12 are connected to a power ground, and a second end of the third resistor R3 is connected to a second power source.
The I2S left and right sound channel frame clock end LRCLK of the decoding chip 03 to be tested, the I2S bit clock end BCLK of the decoding chip 03 to be tested and the I2S serial data end SDATA of the decoding chip 03 to be tested jointly form an I2S audio signal input end of the decoding chip 03 to be tested, the positive output end VOP of the decoding chip 03 to be tested is a first differential audio signal output end of the decoding chip 03 to be tested, the negative output end VON of the decoding chip 03 to be tested is a second differential audio signal output end of the decoding chip 03 to be tested, the power supply end VDD of the decoding chip 03 to be tested is connected with a first power supply VAA, the ground end GND of the decoding chip 03 to be tested is connected with a power supply ground, and the control end CTRL of the decoding chip U2 to be tested is a control.
The differential signal processing circuit 04 includes an audio differential signal processor U3, a thirteenth capacitor C13, and a fourteenth capacitor C14.
The positive power supply terminal V + of the audio differential signal processor U3 is connected to the third power supply VCC and the first terminal of the fourteenth capacitor C14, the negative power supply terminal V-of the audio differential signal processor U3 is connected to the fourth power supply VDD and the first terminal of the thirteenth capacitor C13, the positive phase input terminal + IN of the audio differential signal processor U3 and the negative phase input terminal-IN of the audio differential signal processor U3 jointly constitute a differential audio signal input terminal of the differential signal processing circuit 04, the output terminal OUT of the audio differential signal processor U3 and the detection terminal SENCE of the audio differential signal processor U3 jointly constitute a superimposed signal output terminal of the differential signal processing circuit 04, and the reference voltage terminal REF1 of the audio differential signal processor U3, the second terminal of the fourteenth capacitor C14 and the second terminal of the thirteenth capacitor C13 are jointly connected to the power ground.
Since the decoding chip 03 to be tested outputs differential audio signals, in order to finally facilitate the test of the digital board card configured by the TR6850S tester, the audio differential signal processor U3 performs subtraction and superposition processing of signals, so that VOUT is equal to the difference between VP and VN.
The signal output by the audio differential signal processor U3 is a sinusoidal 1KHZ analog audio signal, and the analog audio signal is sampled by a digital board card configured by a TR6850S tester; and setting sampling parameters of the digital board card according to the actually measured signals, and compiling a test program to test important parameters of the decoding chip 03 to be tested, such as output power, gain, harmonic distortion, signal-to-noise ratio, left and right channel isolation and the like.
The description of fig. 4 is further described below in conjunction with the working principle:
the tester 01 generates and outputs an analog audio signal and sends the analog audio signal to a main clock terminal MCLK of the audio analog-digital converter U1, a right channel analog input terminal AINR of the audio analog-digital converter U1 and a left channel analog input terminal AINL of the audio analog-digital converter U1, the audio analog-digital converter U1 converts the analog audio signal into an I2S audio signal and outputs the audio signal from an audio serial data output terminal SDOUT of the audio analog-digital converter U1, a serial clock terminal SCLK of the audio analog-digital converter U1 and a left and right channel clock terminal LRCLK of the audio analog-digital converter U1; the I2S-bit clock end LRCLK of the left and right sound channel frame clock end of the I2S of the decoding chip 03 to be tested, the I2S-bit clock end BCLK of the decoding chip 03 to be tested and the I2S serial data end SDATA of the decoding chip 03 to be tested receive the I2S audio signal, and the decoding chip 03 to be tested generates a pair of differential audio signals according to the I2S audio signal and outputs the differential audio signals from the output positive end VOP of the decoding chip 03 to be tested and the output negative end VON of the decoding chip 03 to be tested; the non-inverting input terminal + IN of the audio differential signal processor U3 and the inverting input terminal-IN of the audio differential signal processor U3 receive the differential audio signal, and the audio differential signal processor U3 performs subtraction-addition processing on the differential audio signal to generate a superimposed signal and outputs the superimposed signal from the output terminal OUT of the audio differential signal processor U3 to the tester 01. The tester 01 obtains the characteristic parameters of the decoding chip 03 to be tested according to the superimposed signals.
When the left and right channel isolation of the decoding chip 03 to be tested is detected, only the right channel analog input end AINR input signal of the audio analog-to-digital converter U1 is input, and the control end CTRL of the decoding chip 03 to be tested is set to decode only the I2S audio signal of the left channel, so theoretically, the output of the left channel of the decoding chip 03 to be tested should be 0, that is, the right channel does not interfere with the left channel, and thus the left and right channel isolation of the decoding chip 03 to be tested is detected.
The embodiment of the utility model provides a through including tester, encoding circuit, the decoding chip and the difference signal processing circuit that await measuring; the tester generates and outputs an analog audio signal; the coding circuit converts the received analog audio signal into an I2S audio signal and outputs the audio signal to a decoding chip to be detected; the decoding chip to be tested generates a pair of differential audio signals according to the I2S audio signals; the differential signal processing circuit superposes the differential audio signals to generate superposed signals; the tester obtains the characteristic parameters of the decoding chip to be tested according to the superposed signals; therefore, important parameter tests such as output power, gain, harmonic distortion, signal-to-noise ratio, left and right sound channel isolation and the like of the decoding chip to be tested are realized, and the test accuracy of the chip is improved.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.
Claims (9)
1. A testing device of an I2S audio bus power amplifier decoding chip is used for testing the decoding chip to be tested and is characterized by comprising a tester, an encoding circuit and a differential signal processing circuit;
the tester is configured to generate and output an analog audio signal; the coding circuit is connected with the tester, converts the received analog audio signal into an I2S audio signal and outputs the audio signal to the decoding chip to be tested; the decoding chip to be tested generates a pair of differential audio signals according to the I2S audio signals; the differential signal processing circuit is connected with the decoding chip to be detected and is used for superposing the differential audio signals to generate superposed signals; the tester is connected with the differential signal processing circuit and obtains the characteristic parameters of the decoding chip to be tested according to the superposed signals.
2. The device for testing an I2S audio bus power amplifier decoding chip as claimed in claim 1, wherein the device for testing an I2S audio bus power amplifier decoding chip further comprises:
the first filter circuit is connected with the decoding chip to be detected and used for filtering the differential audio signal;
the differential signal processing circuit is connected to the first filter circuit, and is specifically configured to superimpose the filtered differential audio signals to generate a superimposed signal.
3. The device for testing the I2S audio bus power amplifier decoding chip of claim 2, wherein the first filter circuit comprises a first inductor, a second inductor, a first capacitor and a second capacitor;
the first end of the first inductor and the first end of the first capacitor jointly form a first differential audio signal input end of the first filter circuit, the first end of the second inductor and the first end of the first capacitor jointly form a first differential audio signal output end of the first filter circuit, the first end of the second inductor and the first end of the second capacitor jointly form a second differential audio signal output end of the first filter circuit, and the second end of the first capacitor and the second end of the second capacitor are jointly connected to a power ground.
4. The device for testing an I2S audio bus power amplifier decoding chip as claimed in claim 1, wherein the device for testing an I2S audio bus power amplifier decoding chip further comprises:
the second filtering module is connected with the decoding chip to be detected and used for filtering a power supply to generate a first power supply;
and the decoding chip to be tested generates the pair of differential audio signals according to the first power supply and the I2S audio signals.
5. The device for testing the I2S audio bus power amplifier decoding chip of claim 4, wherein the second filtering module comprises a third capacitor and a fourth capacitor;
the first end of the third capacitor and the first end of the fourth capacitor jointly form an input end and an output end of the second filtering module, and the second end of the third capacitor and the second end of the fourth capacitor are connected to a power ground in a shared mode.
6. The device for testing the I2S audio bus power amplifier decoding chip of claim 1, wherein the coding circuit comprises an audio analog-to-digital converter, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;
the master clock end of the audio analog-digital converter, the first end of the first resistor and the first end of the second resistor jointly form an analog audio signal input end of the coding circuit, the second end of the first resistor is connected with the first end of the ninth capacitor, the second end of the ninth capacitor is connected with the right channel analog input end of the audio analog-digital converter, the second end of the second resistor is connected with the first end of the tenth capacitor, the second end of the tenth capacitor is connected with the left channel analog input end of the audio analog-digital converter, the static voltage end of the audio analog-digital converter is connected with the first ends of the eleventh capacitor and the twelfth capacitor, and the positive phase reference voltage end of the audio analog-digital converter is connected with the first ends of the fifth capacitor and the sixth capacitor, an audio serial data output end of the audio analog-digital converter is connected with a first end of the seventh capacitor, a first end of the eighth capacitor, a first end of the third resistor and a first end of the fourth resistor, a serial clock end of the audio analog-digital converter is connected with a first end of the fifth resistor, left and right channel clock ends of the audio analog-digital converter are connected with a first end of the sixth resistor, a second end of the fourth resistor, a second end of the fifth resistor and a second end of the sixth resistor jointly form an I2S audio signal output end of the coding circuit, a ground end of the audio analog-digital converter, a second end of the fifth capacitor, a second end of the sixth capacitor, a second end of the seventh capacitor, a second end of the eighth capacitor, a second end of the eleventh capacitor and a second end of the twelfth capacitor are commonly connected to a power ground, and the second end of the third resistor is connected with a second power supply.
7. The device for testing the I2S audio bus power amplifier decoding chip as claimed in claim 1, wherein the I2S left and right channel frame clock terminal of the decoding chip to be tested, the I2S bit clock terminal of the decoding chip to be tested, and the I2S serial data terminal of the decoding chip to be tested together constitute the I2S audio signal input terminal of the decoding chip to be tested, the positive output terminal of the decoding chip to be tested is the first differential audio signal output terminal of the decoding chip to be tested, the negative output terminal of the decoding chip to be tested is the second differential audio signal output terminal of the decoding chip to be tested, the power terminal of the decoding chip to be tested is connected to a first power supply, and the ground terminal of the decoding chip to be tested is connected to a power ground; and the control end of the decoding chip to be detected is the control signal input end of the decoding chip to be detected.
8. The device for testing the I2S audio bus power amplifier decoding chip of claim 1, wherein the differential signal processing circuit comprises an audio differential signal processor, a thirteenth capacitor and a fourteenth capacitor;
the positive power supply end of the audio differential signal processor is connected with the third power supply and the first end of the fourteenth capacitor, the negative power supply end of the audio differential signal processor is connected with the fourth power supply and the first end of the thirteenth capacitor, the positive phase input end of the audio differential signal processor and the reverse phase input end of the audio differential signal processor jointly form a differential audio signal input end of the differential signal processing circuit, the output end of the audio differential signal processor and the detection end of the audio differential signal processor jointly form a superposed signal output end of the differential signal processing circuit, and the reference voltage end of the audio differential signal processor, the second end of the fourteenth capacitor and the second end of the thirteenth capacitor are jointly connected with a power ground.
9. The device for testing the I2S audio bus power amplifier decoding chip of claim 1, wherein the tester is a TR6850S tester.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112735486A (en) * | 2020-12-22 | 2021-04-30 | 重庆德科电子仪表有限公司 | Audio playing method based on a-law algorithm |
| CN115550101A (en) * | 2022-09-20 | 2022-12-30 | 中国第一汽车股份有限公司 | Automobile audio bus test system |
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2019
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112735486A (en) * | 2020-12-22 | 2021-04-30 | 重庆德科电子仪表有限公司 | Audio playing method based on a-law algorithm |
| CN115550101A (en) * | 2022-09-20 | 2022-12-30 | 中国第一汽车股份有限公司 | Automobile audio bus test system |
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