CN112732005A - Power supply circuit and operation method - Google Patents
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- CN112732005A CN112732005A CN201910975062.7A CN201910975062A CN112732005A CN 112732005 A CN112732005 A CN 112732005A CN 201910975062 A CN201910975062 A CN 201910975062A CN 112732005 A CN112732005 A CN 112732005A
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- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
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Abstract
A power supply circuit and an operation method thereof are provided. The power supply circuit is used for providing a power signal to a de-encoder of an audio device. The power supply circuit includes a random number sequence generating circuit, a control circuit and a power circuit. The random number sequence generating circuit is used for generating a random number sequence. The control circuit is used for outputting a first control signal according to the random number sequence, a first reference signal and the power signal. The power circuit is used for generating a power signal according to the first control signal, so that the power signal is spread in response to the random number sequence.
Description
Technical Field
Embodiments described in the present disclosure relate to a circuit technology, and more particularly, to a power supply circuit and an operating method thereof.
Background
When the audio device operates in the power saving mode, the power supply system of the audio device usually employs a voltage Pulse Frequency (PFM) method to reduce the overall power consumption. However, the power of the audio device is also variable, and therefore, noise spikes (noise spikes) of the power supply system enter the audio device along with the operating frequency of the voltage pulse frequency, thereby causing discomfort to the human ear.
Disclosure of Invention
Some embodiments of the present disclosure relate to a power supply circuit. The power supply circuit is used for providing a power signal to a de-encoder of an audio device. The power supply circuit includes a random number sequence generating circuit, a control circuit and a power circuit. The random number sequence generating circuit is used for generating a random number sequence. The control circuit is used for outputting a first control signal according to the random number sequence, a first reference signal and the power signal. The power circuit is used for generating a power signal according to the first control signal, so that the power signal is spread in response to the random number sequence.
Some embodiments of the present disclosure relate to a method of operating a power supply circuit. The power supply circuit is used for providing a power signal to a de-encoder of an audio device. The operation method comprises the following steps: generating a random number sequence by a random number sequence generating circuit; outputting a first control signal through a control circuit according to the random number sequence, a first reference signal and the power signal; and generating, by a power circuit, a power signal in accordance with the first control signal such that the power signal is spread in response to the random number sequence.
In summary, the power supply circuit and the operating method of the present disclosure can reduce the discomfort of human ears caused by the power signal of the audio device.
Drawings
In order to make the above and other objects, features, advantages and embodiments of the present disclosure more comprehensible, the following description is given:
FIG. 1 is a schematic diagram of a power supply circuit according to some embodiments of the present disclosure;
FIG. 2A is a schematic diagram of a random number sequence generation circuit according to some embodiments of the present disclosure;
FIG. 2B is a schematic diagram of a random number sequence generation circuit according to some embodiments of the present disclosure;
FIG. 2C is a schematic diagram of a random number sequence generation circuit according to some embodiments of the present disclosure;
FIG. 2D is a schematic diagram of a random number sequence generation circuit according to some embodiments of the present disclosure;
FIG. 3 is a circuit diagram illustrating a control circuit according to some embodiments of the present disclosure;
FIG. 4 is a waveform diagram illustrating various signals in the control circuit of FIG. 3 according to some embodiments of the present disclosure; and
fig. 5 is a flow chart illustrating a method of operating a power supply circuit according to some embodiments of the present disclosure.
Description of the symbols
100: power supply circuit
120. 120A, 120B, 120C, 120D: random number sequence generating circuit
121: pseudo-random number binary sequence generator
122: processor with a memory having a plurality of memory cells
123: memory device
124: frequency eliminator
125: triangular wave generator
126: serial-to-parallel circuit
127: multiplexer
128: filter with a filter element having a plurality of filter elements
140. 140A: control circuit
141: switched capacitor circuit
142. 144, and (3) 144: comparator with a comparator circuit
143. 146: inverter with a capacitor having a capacitor element
145: flip-flop (trigger)
160: power supply circuit
500: method of operation
RA [ 3: 0]: redistribution of signals
And RS [ 3: 0]: random number sequence
RS [0] -RS [3 ]: bit cell
VREF1, VREF 2: reference signal
OUT: electric power signal
CS1, CS2, CS3, CS 4: control signal
DR1, DR 2: driver
VCC: supply voltage
VSS: ground voltage
VC: charging signal
PG, NG: drive signal
M1-M3: transistor with a metal gate electrode
L01: inductance
C01: capacitor with a capacitor element
LX: node point
CLK1, CLK 2: clock signal
LUT: lookup table
SC1, SC 2: speed controller
C0-C3: capacitor with a capacitor element
S0-S4: switch with a switch body
IS: current source
EN: enabling signal
T1-T4: time interval
D1, D2: period of responsibility
S502, S504, S506: operation of
Detailed Description
The term "coupled", as used herein, may also mean "electrically coupled", and the term "connected", as used herein, may also mean "electrically connected". "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.
Refer to fig. 1. Fig. 1 is a schematic diagram of a power supply circuit 100 shown in accordance with some embodiments of the present disclosure. In some embodiments, the power supply circuit 100 is applied to an audio device. For example, the audio device includes a power supply circuit 100, a de-encoder, and other circuits. The power supply circuit 100, the de-encoder, and other circuits operate cooperatively to generate an audio signal. The power supply circuit 100 is used for providing a power signal OUT to the de-encoder.
For the example of fig. 1, the power supply circuit 100 includes a random number sequence generating circuit 120, a control circuit 140, and a power circuit 160. The control circuit 140 is coupled to the random number sequence generating circuit 120. The power circuit 160 is coupled to the control circuit 140.
The random number sequence generating circuit 120 is used to generate a random number sequence RS [ 3: 0]. In this example, the random number sequence RS [ 3: the number of bits of 0] is merely exemplary, and various suitable numbers are within the scope of the present disclosure. The control circuit 140 is used for receiving the random number sequence RS [ 3: 0), a reference signal VREF1, and a feedback power signal OUT to generate a random number according to a random number sequence RS [ 3: 0), the reference signal VREF1, and the power signal OUT generate the control signal CS 1. Accordingly, the duty cycle of the control signal CS1 is set in response to the random number sequence RS [ 3: 0]. The power circuit 160 receives the control signal CS1 to generate the power signal OUT according to the control signal CS 1.
For the example of fig. 1, the power circuit 160 includes a driver DR1, a driver DR2, a transistor M1, a transistor M2, an inductor L01, and a capacitor C01. The transistor M1 is used for receiving the power voltage VDD. Transistor M1 is coupled in series with transistor M2. In this example, the transistor M1 is implemented as a P-type transistor and the transistor M2 is implemented as an N-type transistor.
When the control signal CS1 has a low voltage level (e.g., logic value 0), the driver DR1 outputs the driving signal PG having a low voltage level to the control terminal of the transistor M1 according to the control signal CS 1. The driver DR2 outputs the driving signal NG with a low voltage level to the control terminal of the transistor M2 according to the control signal CS 1. In this case, the transistor M1 is turned on and the transistor M2 is turned off. The voltage level at the node LX is pulled up based on the power supply voltage VDD. Accordingly, the voltage signal at the node LX is output through the filter circuit formed by the inductor L01 and the capacitor C01, such that the power signal OUT is pulled up in response to the voltage signal at the node LX.
When the control signal CS1 has a high voltage level (e.g., logic value 1), the driver DR1 outputs the driving signal PG having a high voltage level to the control terminal of the transistor M1 according to the control signal CS 1. The driver DR2 outputs the driving signal NG with a high voltage level to the control terminal of the transistor M2 according to the control signal CS 1. In this case, the transistor M1 is turned off and the transistor M2 is turned on. The voltage level at the node LX is pulled low based on the ground voltage VSS. Accordingly, the voltage signal at the node LX is output through the filter circuit formed by the inductor L01 and the capacitor C01, such that the power signal OUT is pulled low in response to the voltage signal at the node LX.
As previously mentioned, the duty cycle of the control signal CS1 is responsive to the random number sequence RS [ 3: 0]. Accordingly, the duty cycle of the power signal OUT generated according to the control signal CS1 is also responsive to the random number sequence RS [ 3: 0]. Equivalently, the power signal OUT can be considered as being spread.
By the configuration of the power supply circuit 100, the power signal OUT supplied to the encoder of the audio device is spread. Accordingly, the energy of the power signal OUT can be dispersed to a larger frequency range, so that the energy corresponding to each frequency is reduced. Therefore, the discomfort of human ears caused by the power signal of the audio equipment can be reduced.
Refer to fig. 2A. Fig. 2A is a schematic diagram of a random number sequence generating circuit 120A according to some embodiments of the disclosure. In some embodiments, the random number sequence generating circuit 120A is applied to the random number sequence generating circuit 120 of fig. 1, but the disclosure is not limited thereto. For the example of fig. 2A, the random number Sequence generating circuit 120A is a Pseudo Random Binary Sequence (PRBS) generator. The random number sequence generating circuit 120A generates a pseudo random number binary sequence according to the clock signal CLK1, as a random number sequence RS [ 3: 0].
Refer to fig. 2B. Fig. 2B is a schematic diagram of a random number sequence generating circuit 120B according to some embodiments of the disclosure. In some embodiments, the random number sequence generating circuit 120B is applied to the random number sequence generating circuit 120 of fig. 1, but the disclosure is not limited thereto. For the example of fig. 2B, the random number sequence generating circuit 120B includes a pseudo random number binary sequence generator 121, a processor 122, a memory 123, a frequency divider 124, a triangular wave generator 125, a series-to-parallel (series-to-parallel) circuit 126, a multiplexer 127, a filter 128, and speed controllers SC1-SC 2. The memory 123 stores therein a look-up table LUT. The look-up table LUT contains translation information.
The frequency divider 124 is used for generating a clock signal CLK1 according to a clock signal CLK2 to control the speed of the pseudo-random number binary sequence generator 121 for generating the pseudo-random number binary sequence. The serial-to-parallel circuit 126 is used for converting the pseudo-random binary sequence from a serial form to a parallel form according to a clock signal CLK 1. The triangular wave generator 125 is used for generating a triangular wave signal. The speed controller SC1 is used for controlling the speed of the triangular wave generator 125 generating the triangular wave signal according to the clock signal CLK 1. The multiplexer 127 outputs the triangular wave signal from the triangular wave generator 125 or the pseudo-random number binary sequence in parallel form from the serial-to-parallel circuit 126 according to a selection signal (not shown). Processor 122 then converts the triangular wave signal or pseudo-random number binary sequence in parallel form from multiplexer 127 to redistribution signal RA [ 3: 0].
In some embodiments, the triangle wave signal has the same bit length (bit length) as the pseudo random number binary sequence in parallel form.
Regarding how processor 122 utilizes the look-up table LUT to generate reassignment signal RA [ 3: 0], for example, the lookup table LUT states that "000000" corresponds to "0001", "000001" corresponds to "0101", "000010" corresponds to "0010" … …, and so on. In this case, when the triangular wave signal from the multiplexer 127 or the pseudo random number binary sequence in parallel form from the sequence-to-parallel circuit 126 has seven bits and corresponds to 000000, RA [ 3: 0] corresponds to "0001". When the triangular wave signal from the multiplexer 127 or the pseudo random number binary sequence in parallel form from the serial-to-parallel circuit 126 corresponds to 000001, RA [ 3: 0] corresponds to "0101". When the triangular wave signal from the multiplexer 127 or the pseudo random number binary sequence in parallel form from the serial-to-parallel circuit 126 corresponds to 000010, RA [ 3: 0] corresponds to "0010".
The speed controller SC2 is used for controlling the processing speed of the processor 122 according to the clock signal CLK 1. The filter 128 further generates a redistribution signal RA [ 3: 0] after a filtering procedure, a random number sequence RS [ 3: 0]. In some embodiments, Filter 128 may be implemented using a Low-Pass Filter (LPF).
Refer to fig. 2C. Fig. 2C is a schematic diagram of a random number sequence generation circuit 120C according to some embodiments of the present disclosure. In some embodiments, the random number sequence generating circuit 120C is applied to the random number sequence generating circuit 120 of fig. 1, but the disclosure is not limited thereto. For the example of FIG. 2C, the random number sequence generating circuit 120C includes only the frequency divider 124, the speed controllers SC1-SC2, the triangular wave generator 125, the processor 122, the memory 123, and the filter 128. In these embodiments, processor 122 converts the triangular wave signal from triangular wave generator 125 to redistribution signal RA [ 3: 0]. The rest of the operation is similar to that of fig. 2B, and thus is not described herein again.
Refer to fig. 2D. Fig. 2D is a schematic diagram of the random number sequence generating circuit 120D according to some embodiments of the disclosure. In some embodiments, the random number sequence generating circuit 120D is applied to the random number sequence generating circuit 120 of fig. 1, but the disclosure is not limited thereto. For the example of fig. 2D, the random number sequence generating circuit 120D includes only a frequency divider 124, a pseudo random number binary sequence generator 121, a sequence-to-parallel circuit 126, a processor 122, a memory 123, a filter 128, and a speed controller SC 2. In these embodiments, processor 122 converts the pseudo-random number binary sequence in parallel form from sequence to parallel circuit 126 to a redistribution signal RA [ 3: 0]. The rest of the operation is similar to that of fig. 2B, and thus is not described herein again.
In fig. 2B to 2D, the look-up table LUT containing conversion information may cause the random number sequence RS [ 3: 0] can be more elevated.
Refer to fig. 3. Fig. 3 is a circuit diagram of a control circuit 140A shown in accordance with some embodiments of the present disclosure. In some embodiments, the control circuit 140A is applied to the control circuit 140 of fig. 1, but the disclosure is not limited thereto. In some embodiments, the control circuit 140A generates the random number sequence RS [ 3: 0] run.
For the example of fig. 3, the control circuit 140A includes a transistor M3, a switched capacitor circuit 141, a switch S4, a comparator 142, an inverter 143, a comparator 144, a flip-flop 145, and an inverter 146. In this example, the transistor M3 and the switch S4 may be implemented as N-type transistors.
The switched capacitor circuit 141 is configured to generate the random number sequence RS [ 3: 0] generates the charge signal VC. Specifically, the switched-capacitor circuit 141 includes capacitors C0-C3 and switches S0-S3. The switches S0-S3 are coupled in series with the capacitors C0-C3, respectively. Switches S0-S3 are respectively controlled by random number sequences RS [ 3: 0, a plurality of bits RS 0-RS 3 control the on or off. The switched capacitor circuit 141 is coupled to the transistor M3. The transistor M3 is coupled to the ground voltage VSS and is controlled to be turned on or off by the driving signal PG. Switched-capacitor circuit 141 receives the current provided by current source IS through switch S4. The switch S4 is controlled to be turned on or off by the enable signal EN. The switched capacitor circuit 141 generates the charging signal VC in cooperation with the switch S4 and the transistor M3. In some embodiments, the capacitances of the capacitances C0-C3 are different from each other. For example, the capacitance C3 is one time the unit capacitance value, the capacitance C2 is two times the unit capacitance value, the capacitance C1 is four times the unit capacitance value, and the capacitance C0 is eight times the unit capacitance value. Accordingly, since switches S0-S3 are respectively subject to random number sequences RS [ 3: 0] and the capacitances of the capacitors C0-C3 are different from each other, so the charging speed (slope) of the charging signal VC (e.g., the charging signal VC shown in fig. 4) is variable.
The comparator 142 is used for comparing the charging signal VC and the reference signal VREF2 to generate the control signal CS 2. The inverter 143 generates an inverted signal of the control signal CS2 (the control signal CS 3). The comparator 144 compares the reference signal VREF1 and the power signal OUT to generate the control signal CS 4. The flip-flop 145 is configured to generate the enable signal EN according to the control signal CS4 and the control signal CS 3. The inverter 146 is used to generate an inverted signal of the enable signal EN (the control signal CS 1).
Refer to fig. 4. Fig. 4 is a waveform diagram illustrating a plurality of signals in the control circuit 140A of fig. 3 according to some embodiments of the present disclosure. For ease of understanding, FIG. 4 will be discussed in conjunction with FIG. 1 and FIG. 3.
At time interval T1, the power signal OUT gradually falls, but is still greater than the reference signal VREF 1. In this case, the control signal CS4 output by the comparator 144 has a low voltage level.
At time interval T2, when the power signal OUT is smaller than the reference signal VREF1, the control signal CS4 output by the comparator 144 goes to a high voltage level. Since the control signal CS4 changes from the low voltage level to the high voltage level and the control signal CS3 has the low voltage level, the enable signal EN output from the flip-flop 145 has the high voltage level. Accordingly, the switch S4 of fig. 3 is turned on and the control signal CS1 output by the inverter 146 has a low voltage level. In this case, the driving signals PG and NG also have low voltage levels. Accordingly, the transistor M1 of fig. 1 is turned on, and the transistors M2 of fig. 1 and M3 of fig. 3 are turned off. In this case, the power supply voltage VCC of fig. 1 charges the node LX through the transistor M1, so that the voltage level of the power signal OUT is pulled up. Meanwhile, the current source IS in fig. 3 charges the switch capacitor circuit 141 through the switch S4 and the current does not flow to the ground through the transistor M3, so as to increase the voltage level of the charging signal VC.
In the time interval T3, when the power signal OUT is greater than the reference signal VREF1, the control signal CS4 output by the comparator 144 goes to a low voltage level. Since the control signal CS4 changes from the high voltage level to the low voltage level and the control signal CS3 has the low voltage level, the enable signal EN output from the flip-flop 145 still has the high voltage level. Accordingly, the switch S4 of fig. 3 is turned on and the control signal CS1 output by the inverter 146 has a low voltage level. In this case, the driving signals PG and NG also have low voltage levels. Accordingly, the transistor M1 of fig. 1 is turned on, and the transistors M2 of fig. 1 and M3 of fig. 3 are turned off. In this case, the power supply voltage VCC of fig. 1 charges the node LX through the transistor M1, so that the voltage level of the power signal OUT is pulled up. Meanwhile, the current source IS in fig. 3 charges the switch capacitor circuit 141 through the switch S4 and the current does not flow to the ground through the transistor M3, so as to increase the voltage level of the charging signal VC.
At time interval T4, when the charging signal VC is greater than the reference signal VREF2, the control signal CS2 output by the comparator 142 has a low voltage level. Accordingly, the control signal CS3 output from the inverter 143 goes to a high voltage level. Since the control signal CS4 has a low voltage level and the control signal CS3 changes from the low voltage level to the high voltage level, the enable signal EN output from the flip-flop 145 has a low voltage level. Accordingly, the switch S4 of fig. 3 is turned off and the control signal CS1 output from the inverter 146 has a high voltage level. In this case, the driving signals PG and NG also have high voltage levels. Accordingly, the transistor M1 of fig. 1 is turned off, and the transistors M2 of fig. 1 and M3 of fig. 3 are turned on. In this case, the voltage level of the node LX of fig. 1 is pulled low by the ground voltage VSS via the transistor M2, so that the voltage level of the power signal OUT is pulled low. Meanwhile, the voltage level of the charging signal VC in fig. 3 is pulled low by the ground voltage VSS via the transistor M3.
Fig. 1 and 4 are also referred to. Since the power signal OUT is pulled low through the inductor L01 and the transistor M2, and the capacitance of the capacitor C01 is large (e.g., 4.7uF), the power signal OUT drops slowly. The charge signal VC is pulled low only through the transistor M3, and the capacitance values of the capacitors C0-C3 are small (e.g., less than 100pF), so the charge signal VC falls rapidly.
As previously described, the random number sequence RS [ 3: 0] the charging speed of the generated charging signal VC is variable. Accordingly, the duty cycle of the control signal CS1 generated based on the charging signal VC is not fixed. For the example of fig. 4, the duty cycle D1 of the control signal CS1 is longer, while the duty cycle D2 of the control signal CS1 is shorter. Thus, the power signal OUT output by the power circuit 160 is spread.
Refer to fig. 5. Fig. 5 is a flow chart illustrating a method 500 for operating a power supply circuit according to some embodiments of the present disclosure. The execution method 500 includes operations S502, S504, and S506. In some embodiments, the operation method 500 is applied to the power supply circuit 100 of fig. 1, but the disclosure is not limited thereto. For ease of understanding, the operational method 500 will be discussed in conjunction with FIG. 1.
In operation S502, a random number sequence RS [ 3: 0]. Random number sequence RS [ 3: the number of bits of 0] is merely exemplary, and various suitable numbers are within the scope of the present disclosure.
In operation S504, the random number sequence RS [ 3: 0), the reference signal VREF1, and the power signal OUT output control signal CS 1. Accordingly, the duty cycle of the control signal CS1 is responsive to the random number sequence RS [ 3: 0].
In operation S506, the power signal OUT is generated by the power circuit 160 according to the control signal CS 1. As previously mentioned, the duty cycle of the control signal CS1 is responsive to the random number sequence RS [ 3: 0]. Accordingly, the duty cycle of the power signal OUT generated according to the control signal CS1 is also responsive to the random number sequence RS [ 3: 0]. In this case, the duty cycle of the power signal OUT is not fixed, so that the power signal OUT is spread.
In summary, the power supply circuit and the operating method of the present disclosure can reduce the discomfort of human ears caused by the power signal of the audio device.
Various functional elements and blocks have been disclosed herein. It will be apparent to those skilled in the art that functional blocks may be implemented by circuits (whether dedicated circuits or general purpose circuits that operate under the control of one or more processors and coded instructions), which generally comprise transistors or other circuit elements for controlling the operation of the electrical circuits in accordance with the functions and operations described herein. As will be further appreciated, the specific structure and interconnections of circuit elements in general may be determined by a compiler, such as a Register Transfer Language (RTL) compiler. The register transfer language compiler operates on instruction codes (script) that are substantially similar to assembly language codes (assembly language codes) to compile the instruction codes into a form for layout or fabrication of the final circuit. Indeed, register transfer languages are known for their role and purpose in facilitating the design process of electronic and digital systems.
Although the present disclosure has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be determined by that of the appended claims.
Claims (10)
1. A power supply circuit for providing a power signal to a de-encoder of an audio device, the power supply circuit comprising:
a random number sequence generating circuit for generating a random number sequence;
a control circuit for outputting a first control signal according to the random number sequence, a first reference signal and the power signal; and
a power circuit for generating the power signal according to the first control signal such that the power signal is spread in response to the random number sequence.
2. The power supply circuit of claim 1, wherein a first duty cycle of the first control signal is different from a second duty cycle of the first control signal.
3. The power supply circuit of claim 1, wherein the random number sequence generating circuit comprises:
a pseudo-random number binary sequence generator is used for generating a pseudo-random number binary sequence according to a first clock signal and using the pseudo-random number binary sequence as the random number sequence.
4. The power supply circuit of claim 1, wherein the random number sequence generating circuit comprises:
a pseudo-random number binary sequence generator for generating a pseudo-random number binary sequence according to a first clock signal; and
a processor for generating a redistribution signal according to the first clock signal and the pseudo-random number binary sequence based on a lookup table to generate the random number sequence.
5. The power supply circuit of claim 4, wherein the random number sequence generating circuit further comprises:
a frequency divider for dividing a second clock signal to generate the first clock signal.
6. The power supply circuit of claim 4, wherein the random number sequence generating circuit further comprises:
a filter for performing a filtering procedure on the redistribution signal according to the first clock signal to generate the random number sequence.
7. The power supply circuit of claim 1, wherein the random number sequence generating circuit comprises:
a triangular wave generator for generating a triangular wave signal according to the first clock signal; and
a processor for generating the random number sequence according to the first clock signal and the triangular wave signal based on a lookup table.
8. The power supply circuit of claim 1, wherein the control circuit comprises:
a switch capacitor circuit for generating a charging signal according to the random number sequence;
a first comparator for comparing the charging signal with a second reference signal to generate a second control signal;
a first inverter for generating a third control signal according to the second control signal;
a second comparator for comparing the first reference signal with the power signal to generate a fourth control signal;
a positive and negative device for generating an enable signal according to the fourth control signal and the third control signal; and
a second inverter for generating the first control signal according to the enable signal, wherein a duty cycle of the first control signal is responsive to the random number sequence.
9. The power supply circuit of claim 8, wherein the switched-capacitor circuit comprises:
a plurality of capacitors; and
and the switches are respectively coupled with the capacitors in series and are used for being switched on or switched off according to a plurality of bits of the random number sequence so as to generate the charging signal.
10. A method of operating a power supply circuit for providing a power signal to a de-encoder of an audio device, the method comprising:
generating a random number sequence by a random number sequence generating circuit;
outputting a first control signal through a control circuit according to the random number sequence, a first reference signal and the power signal; and
the power signal is generated by a power circuit according to the first control signal, so that the power signal is spread in response to the random number sequence.
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| JP2005033534A (en) * | 2003-07-14 | 2005-02-03 | Fuji Electric Holdings Co Ltd | Signal transmitting method |
| CN101199132A (en) * | 2005-05-13 | 2008-06-11 | 艾利森电话股份有限公司 | System for rapid frequency hopping radio |
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