CN112713237A - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN112713237A CN112713237A CN202110329856.3A CN202110329856A CN112713237A CN 112713237 A CN112713237 A CN 112713237A CN 202110329856 A CN202110329856 A CN 202110329856A CN 112713237 A CN112713237 A CN 112713237A
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
- H10N30/081—Shaping or machining of piezoelectric or electrostrictive bodies by coating or depositing using masks, e.g. lift-off
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N30/50—Piezoelectric or electrostrictive devices having a stacked or multilayer structure
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Abstract
The invention provides a semiconductor device and a forming method thereof. The first metal material layer is formed on the surface of the piezoelectric layer, so that the mass loading layer can be prepared by utilizing a stripping process before the upper electrode layer, stable thickness detection can be carried out on the mass loading layer in the process of preparing the mass loading layer, and the interference of the upper electrode layer is avoided. And based on the existence of the first metal material layer, the metal ring can be prepared before the upper electrode layer, so that the flexibility of the preparation process of the device is greatly improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
A crystal oscillator and a filter (for example, a bulk acoustic wave filter) can be further generally configured by applying a resonant structure made of a piezoelectric material having an inverse piezoelectric effect to a semiconductor device. The resonant structure of the semiconductor device generally includes an upper electrode, a lower electrode, and a piezoelectric layer sandwiched between the upper electrode and the lower electrode, and at present, in order to prepare resonant structures with different frequencies, a mass loading layer is usually further provided, and the frequency adjustment of the resonant structure is further realized by adjusting the thickness of the mass loading layer.
In a semiconductor device for practical use, it is common that a mass loading layer is provided in a partial resonant structure and not in a partial resonant structure, and the thickness of the mass loading layer may also be different in different resonant structures. For example, as shown in fig. 1, a semiconductor device includes a substrate 10, and a lower electrode layer 21, a piezoelectric layer 22, and an upper electrode layer 23 sequentially formed on the substrate 10. A mass loading layer 25 is also formed on the upper electrode layer 23 in a partial resonance region (e.g., the first resonance region 10A shown in fig. 1), and a mass loading layer is not provided in a partial resonance region (e.g., the second resonance region 10B shown in fig. 1).
In addition, in a specific device process, after the mass loading layer 25 is prepared, the thickness of the mass loading layer 25 is usually measured, but since the upper electrode layer 23 is also provided below the mass loading layer 25, the measurement of the mass loading layer 25 is easily interfered, and the thickness of the mass loading layer 25 is difficult to be measured accurately.
Disclosure of Invention
The invention aims to provide a semiconductor device and a forming method thereof, and aims to solve the problem that the thickness of a mass loading layer of the semiconductor device prepared by the existing process is difficult to accurately measure.
In order to solve the above technical problem, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein at least one resonance area is arranged on the substrate; sequentially forming a lower electrode layer and a piezoelectric layer in each resonance region of the substrate; performing a sputtering process at a first temperature to form a first metallic material layer overlying the piezoelectric layer; performing a sputtering process and a lift-off process at a second temperature to form a mass loading layer on a first metallic material layer of at least one resonance region, the second temperature and the first temperature differing by at most 10 ℃; and forming an upper electrode layer and a metal ring in each resonance region, the metal ring being located at an edge position of the resonance region and within a region of the upper electrode layer, wherein the upper electrode layer is formed by performing a sputtering process and an etching process at a third temperature, the third temperature being higher than the first temperature or the second temperature by at least 150 ℃, and the metal ring is formed by performing a sputtering process and a lift-off process.
Optionally, the method for forming the mass loading layer includes: forming a patterned photoresist layer on the first metal material layer; performing a sputtering process at a second temperature to form a second metal material layer, wherein the second metal material layer is formed in the region exposed from the patterned photoresist layer and is also formed on the patterned photoresist layer; and stripping the patterned photoresist layer by using a stripping liquid to remove the metal material on the patterned photoresist layer, and forming the mass loading layer by using the reserved metal material.
Optionally, the thickness of the first metal material layer is less than or equal to 200 a.
Optionally, both the first temperature and the second temperature are less than or equal to 50 ℃, and the third temperature is greater than or equal to 200 ℃. Further, the second temperature is the same as the first temperature.
Optionally, the upper electrode layer and the mass loading layer both comprise the same metal material.
Optionally, the metal ring is prepared before the upper electrode layer, and an end of the upper electrode layer covers the metal ring; alternatively, the metal ring is formed on the upper electrode layer and located at an end portion of the upper electrode layer.
Optionally, the method for forming the mass loading layer further includes performing thickness measurement on the mass loading layer, and the method for measuring the thickness includes: and taking the piezoelectric layer as a signal reflection layer, and obtaining the thickness value of the film layer above the piezoelectric layer according to the reflection signal reflected by the piezoelectric layer.
Optionally, the substrate has a first resonance region and a second resonance region, the mass loading layer is formed in the first resonance region, and the mass loading layer is not formed in the second resonance region; and the method of forming the upper electrode layer further includes also performing a thickness measurement of the upper electrode layer in the second resonance region, the thickness measurement method including: and taking the piezoelectric layer as a signal reflection layer to obtain a film layer thickness value above the piezoelectric layer according to a reflection signal reflected by the piezoelectric layer.
The present invention also provides a semiconductor device comprising: a substrate having at least one resonant region thereon; a lower electrode layer provided at least on the substrate of each resonance region; a piezoelectric layer formed on the substrate and covering each resonance region; a bottom metal layer contacting and covering the piezoelectric layer; a mass loading layer disposed on the bottom metal layer of the at least one resonance region; and the upper electrode layer and the metal ring are arranged in each resonance area, and the metal ring surrounds the edge of each resonance area and is positioned in the area range of the upper electrode layer.
Optionally, the semiconductor device further includes: the end part of the upper electrode layer covers the metal ring; alternatively, the metal ring is formed on the upper electrode layer at an end portion of the upper electrode layer.
According to the semiconductor device and the forming method thereof, the first metal material layer is formed on the surface of the piezoelectric layer, so that the mass loading layer can be prepared before the upper electrode layer by utilizing a stripping process, the metal ring can be prepared before the upper electrode layer, and the flexibility of the preparation process of the device is greatly improved. Meanwhile, compared with the upper electrode layer, the mass loading layer is preferentially prepared, so that stable thickness detection can be carried out on the mass loading layer when the mass loading layer is prepared, and the interference of the upper electrode layer is avoided.
Drawings
Fig. 1 is a schematic structural view of a semiconductor device.
Fig. 2 is a schematic flow chart of a method for forming a semiconductor device according to the present invention.
Fig. 3 to 8 are schematic structural diagrams of a method for forming a semiconductor device in a first embodiment of the invention during a manufacturing process thereof.
Fig. 9 is a schematic structural view of a semiconductor device in a second embodiment of the present invention.
Wherein the reference numbers are as follows:
10/100-a substrate;
110 a-a cavity;
110-a sacrificial layer;
10A/100A-first resonance region;
10B/100B-second resonance region;
21/210-lower electrode layer;
22/220-a piezoelectric layer;
23/230 — upper electrode layer;
24/240-metal ring;
25/250-mass-loading layer;
260-bottom metal layer;
260' -a first metallic material layer.
Detailed Description
The core idea of the invention is to provide a semiconductor device and a forming method thereof, which particularly adjust the preparation process of the mass loading layer to make the measurement process of the mass loading layer more stable and improve the thickness measurement precision of the mass loading layer. Specifically, the method for forming the semiconductor device provided by the present invention can be referred to as fig. 2, which includes the following steps.
Step S100, providing a substrate having at least one resonance region thereon.
Step S200 of sequentially forming a lower electrode layer and a piezoelectric layer in each resonance region of the substrate.
Step S300, performing a sputtering process at a first temperature to form a first metallic material layer, wherein the first metallic material layer covers the piezoelectric layer.
Step S400 of performing a sputtering process and a lift-off process at a second temperature to form a mass loading layer on the first metallic material layer of the at least one resonance region, the second temperature and the first temperature having a temperature difference of at most 10 ℃.
Step S500, forming an upper electrode layer and a metal ring in each resonance region, where the metal ring is located at an edge of the resonance region and in a region of the upper electrode layer, where the forming method of the upper electrode layer includes performing a sputtering process and an etching process at a third temperature, where the third temperature is higher than the first temperature or the second temperature by at least 150 ℃, and the forming method of the metal ring includes performing a sputtering process and a lift-off process.
The semiconductor device and the method for forming the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. It will be understood that relative terms, such as "above," "below," "top," "bottom," "above," and "below," may be used in relation to various elements shown in the figures. These relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the figures. For example, if the device were inverted relative to the view in the drawings, an element described as "above" another element, for example, would now be below that element.
< example one >
In step S100, referring to fig. 3 in particular, a substrate 100 is provided, where the substrate 100 has at least one resonance region, and the resonance region is a region for forming a resonance structure. In the present embodiment, only two resonance regions are illustrated as an example for explanation, and as shown in fig. 3, the substrate 100 has a first resonance region 100A and a second resonance region 100B.
Wherein the substrate 100 may be adjusted accordingly depending on the particular application of the semiconductor device being formed. For example, the semiconductor device may be a Bulk Acoustic Wave (BAW) filter, in which case the substrate may include multiple layers of bragg reflectors to further form a solid-state fabricated resonator (SMR); alternatively, the substrate may further include a cavity to further constitute a film bulk acoustic resonator Filter (FBAR).
In this embodiment, a film bulk acoustic resonator filter is formed as an example. Based on this, a cavity 110a is formed in each resonant region of the substrate 100, and a sacrificial layer 110 is further filled in the cavity 110a, and the sacrificial layer 110 is removed after the resonant structure is completed in the subsequent preparation, so as to release the cavity.
In step S200, specifically referring to fig. 4, a lower electrode layer 210 and a piezoelectric layer 220 are sequentially formed in each resonance region of the substrate 100. In this embodiment, the lower electrode layer 210 at least partially covers the cavity 110a, and the piezoelectric layer 220 continuously covers each resonance region and correspondingly covers the lower electrode layer 210.
The material of the lower electrode layer 210 may include a metal material, for example, one or a combination of molybdenum, gold, tungsten, platinum, ruthenium, titanium-tungsten, aluminum, and titanium. And, the material of the piezoelectric layer 220 includes, for example, at least one of zinc oxide (ZnO), aluminum nitride (AlN), and lead zirconate titanate (PZT).
In step S300, and with particular reference to fig. 5, a sputtering process is performed at a first temperature T1 to form a first metallic material layer 260 ', the first metallic material layer 260' overlying the piezoelectric layer 220.
Specifically, the sputtering process is performed at a first temperature T1, which may be: the film quality of the first metal material layer 260' sputter formed at the first temperature T1 is controlled by adjusting the temperature of the surface of the substrate 100 to about the first temperature T1 and performing a sputtering process.
In this embodiment, the first temperature T1 is not higher than 100 ℃ and may be further equal to or lower than 50 ℃. For example, a sputtering process may be performed at a normal temperature or a greenhouse to form the first metallic material layer 260'. In this way, the first metal material layer 260' with low temperature material property is formed by sputtering under low temperature condition.
It should be noted that, in the subsequent processes, a lift-off process is used to form the mass loading layer and the metal ring, and in order to avoid the influence on the piezoelectric layer 220 caused by the photoresist layer directly contacting the piezoelectric layer 220 in the lift-off process, in this embodiment, the first metal material layer 260' is preferably coated before the lift-off process is performed to space the subsequently formed photoresist layer. Wherein the thickness of the first metallic material layer 260 'may be controlled within a small range, for example the thickness of the first metallic material layer 260' may be made less than or equal to 200 a.
In addition, in the present embodiment, the first metal material layer 260 'is formed by sputtering at a low temperature, so that the first metal material layer 260' can be matched with a mass loading layer which is subsequently formed by sputtering at a low temperature.
In step S400, and with particular reference to fig. 6, a sputtering process and a lift-off process are performed at a second temperature T2 to form a mass loading layer 250 on the first metallic material layer 260' of the at least one resonance region.
Specifically, the substrate 100 has a plurality of resonance regions, a part of the resonance regions is formed with the mass loading layer 250, and the other part of the resonance regions is not formed with the mass loading layer 250. For example, referring to fig. 6, the mass loading layer 250 is formed in the first resonance region 100A, and the mass loading layer 250 is not formed in the second resonance region 100B.
The method for forming the mass loading layer 250 by performing the sputtering process and the lift-off process may specifically include the following steps.
In a first step, a patterned photoresist layer (not shown) is formed on the first metal material layer 260', wherein the patterned photoresist layer may be an organic photoresist layer, and the material thereof includes polyimide, for example.
The patterned photoresist layer exposes the resonance area where the mass loading layer is required to be formed and covers the resonance area where the mass loading layer is not required to be formed. In this embodiment, the patterned photoresist layer (not shown) exposes the first resonant region 100A and covers the second resonant region 100B.
A second step of performing a sputtering process at a second temperature T2 to form a second metallic material layer, the second metallic material layer being formed on the resonance region exposed from the patterned photoresist layer and also formed on the patterned photoresist layer.
Wherein, the second metal material layer and the first metal material layer 260' may adopt the same metal material, and the metal material may further include one or a combination of molybdenum, gold, tungsten, platinum, ruthenium, titanium tungsten, aluminum and titanium.
In this embodiment, the second temperature T2 and the first temperature T1 are the same or similar, for example, the temperature difference between the second temperature T2 and the first temperature T1 is at most 10 ℃. That is, the second metal material layer and the first metal material layer 260' are formed by sputtering at a relatively low temperature, and have the same or similar film quality. For example, the second metal material layer and the first metal material layer 260' are both formed by sputtering under normal temperature or room temperature conditions.
Note that the second metal material layer is formed by sputtering under low temperature conditions, and one reason for this is that: the method can avoid the influence of high temperature environment on the patterned photoresist layer on the substrate, such as the problem that the organic photoresist layer is easy to deform under the high temperature environment, and further the pattern precision is influenced. Based on this, in the present embodiment, as for the mass loading layer formed by the lift-off process, a low-temperature metal material is formed by sputtering under a low-temperature condition.
In addition, in this embodiment, the first metal material layer 260 'is also formed by sputtering at a low temperature, and the same metal material may be used for the first metal material layer 260' and the second metal material layer. That is, the first metal material layer 260 'and the second metal material layer are both low-temperature metal materials formed by the same sputtering process based on the same metal material, have the same film properties, and avoid an unstable interface between the first metal material layer 260' and the second metal material layer. That is, it is equivalent to avoid an unstable interface between the first metal material layer 260' and the mass loading layer 250, so that when the thickness of the mass loading layer 250 is measured, it is beneficial to ensure that the measurement result is stable and the measurement accuracy is improved.
A third step of stripping the patterned photoresist layer with a stripping solution to remove the metal material on the patterned photoresist layer, and forming the mass loading layer 250 with the remaining metal material. In this embodiment, after the patterned photoresist layer is stripped, the mass loading layer 250 may be formed in the first resonance region 100A, and no mass loading layer may be formed in the second resonance region 100B.
As described above, the first metal material layer 260' is further disposed between the patterned photoresist layer and the piezoelectric layer 220, so as to effectively block the stripping liquid and prevent the piezoelectric layer 220 from being corroded. It is considered that the patterning process using the lift-off process on the piezoelectric layer 220 can be realized by providing the first metallic material layer 260' in the present embodiment.
In a further aspect, the method for forming the mass loading layer 250 further includes: a thickness measurement is made of the mass loading layer 250. Specifically, the method for measuring the thickness of the mass loading layer 250 includes: the piezoelectric layer 220 is used as a signal reflection layer, so that the thickness value of the metal material layer above the piezoelectric layer 220 is obtained according to the reflection signal reflected by the piezoelectric layer 220.
As described above, since the first metal material layer 260 ' and the mass loading layer 250 above the piezoelectric layer 220 are formed by sputtering at a low temperature, and the same metal material is used, so that there is no unstable interface (even no interface) between the first metal material layer 260 ' and the mass loading layer 250, when the thickness measurement is performed, the reflected signal reflected from the piezoelectric layer 220 can be stably obtained, and thus the sum of the thicknesses of the mass loading layer 250 and the first metal material layer 260 ' can be stably obtained. Of course, before the mass loading layer 250 is prepared, the thickness of the first metal material layer 260 ' may also be measured, so that after the sum of the thicknesses of the mass loading layer 250 and the first metal material layer 260 ' is obtained, the accurate thickness of the mass loading layer 250 may be precisely obtained by further removing the thickness of the first metal material layer 260 '.
It should be appreciated that, when the mass loading layer 250 is measured, the stability of the measurement of the mass loading layer 250 can be improved because there is no interfering upper electrode layer below the mass loading layer. In particular, when the upper electrode layer and the mass supporting layer 250 are formed based on the same metal material and prepared at different temperatures, a problem of interfacial instability between the upper electrode layer and the mass supporting layer 250 often occurs. For example, a mass loading layer formed by sputtering at a low temperature (e.g., a low-temperature molybdenum layer formed by sputtering at a low temperature) and an upper electrode layer formed by sputtering at a high temperature (e.g., a high-temperature molybdenum layer formed by sputtering at a high temperature) have an unstable interface therebetween. At this time, if the mass loading layer formed at a low temperature is disposed on the upper electrode layer formed at a high temperature and the thickness of the upper mass loading layer is measured, the measurement result is also unstable due to the presence of an unstable interface.
In step S500, referring to fig. 7 and 8 in particular, an upper electrode layer 230 and a metal ring 240 are formed in each resonance area, and the metal ring 240 is located at an edge position of the resonance area and within an area of the upper electrode layer 230.
In this embodiment, the upper electrode layer 230 is prepared after the metal ring 240 is preferentially formed. At this time, in a resonance region (for example, the first resonance region 100A shown in fig. 7) where the mass loading layer 250 is formed, the metal ring 240 is formed on the mass loading layer 250 and may be further located at an edge of the mass loading layer 250.
Specifically, the forming method of the metal ring 240 includes performing a sputtering process and a lift-off process. In this way, etching damage to the mass loading layer 250 is avoided when using an etching process. The process temperature of the sputtering process of the metal ring 240 may be lower than 100 ℃, for example, the temperature difference from the first temperature T1 or the second temperature T2 is at most 10 ℃, so as to sputter form the metal ring 240 under low temperature conditions. And, in the lift-off process of the metal ring 240, the piezoelectric layer 220 may also be protected by the first metallic material layer 260'. That is, in the present embodiment, in order to ensure the quality of the metal ring 240 and the mass loading layer 250, both are formed by using the lift-off process, and the piezoelectric layer 220 is protected based on the first metal material layer 260' when the lift-off process is performed, so that the lift-off process is implemented.
Wherein the metal ring 240 and the mass loading layer 250 may comprise the same metal material, for example, each comprising one or a combination of molybdenum, gold, tungsten, platinum, ruthenium, titanium tungsten, aluminum, and titanium. It can be understood that, by forming the metal ring 240 at the edge of the resonance region, the thickness of the film layer at the edge of the resonance region is increased, which is beneficial to adjusting the frequency of the edge position of the resonance structure to be different from the frequency of the main body portion of the resonance structure, thereby reducing the energy loss at the edge position of the resonance structure and improving the quality factor (Q value) of the device.
Further, the method of forming the upper electrode layer 230 includes performing a sputtering process and an etching process at the third temperature T3. The third temperature T3 is at least 150 ℃ higher than the first temperature T1 or the second temperature T2, for example, the third temperature T3 is not lower than 200 ℃ (more specifically, the third temperature T3 may be further equal to or higher than 300 ℃). In a specific embodiment, the upper electrode layer 230 having high-temperature material properties may be formed by heating the substrate 100 to adjust the surface temperature of the substrate 100 to about the third temperature T3 and performing a sputtering process.
Also, in the resonance region having the mass loading layer 250, the upper electrode layer 230 covers the mass loading layer 250. And, an end portion of the upper electrode layer 230 covers the metal ring 240. Wherein the upper electrode layer 230 and the mass loading layer 250 may both comprise the same metal material, for example, both comprise one or a combination of molybdenum, gold, tungsten, platinum, ruthenium, titanium tungsten, aluminum, and titanium.
Specifically, the method of performing the sputtering process and the etching process to form the upper electrode layer 230 may include: first, a sputtering process is performed at a third temperature T3 to form a third metallic material layer for constituting the upper electrode layer; next, an etching process is performed to pattern the third metal material layer to form the upper electrode layer 230. The upper electrode layer 230 has high requirements for film quality, and is formed by sputtering under high temperature conditions to ensure uniformity of the high temperature metal material formed to constitute the upper electrode layer 230 and film stress. In this embodiment, after performing an etching process to pattern the third metal material layer, the exposed first metal material layer may be further etched, so as to pattern the first metal material layer to form the bottom metal layer 260.
It should be noted that, in the present embodiment, the preparation process of the upper electrode layer 230 is adjusted to be formed after the mass loading layer 250, so as to preferentially ensure that the thickness of the mass loading layer 250 can be stably measured. The thickness measurement of the upper electrode layer 230 can be obtained by measuring the area where the mass loading layer is not formed. At this time, the piezoelectric layer 220 can also be used as a signal reflection layer, so that the thickness value of the film layer above the piezoelectric layer 220 can be obtained according to the reflection signal reflected by the piezoelectric layer 220.
For example, the resonance region where the mass loading layer is not formed is measured to obtain the thickness of the upper electrode layer 230. Taking fig. 8 as an example, the thickness measurement of the second resonance region 100B may be performed before or after patterning the third metal material layer. Alternatively, the third metallic material layer between adjacent resonance regions may be measured before patterning the third metallic material layer, for example, the third metallic material layer between the first resonance region 100A and the second resonance region 100B.
It should be further appreciated that although the first metal material layer 260 'is still present under the upper electrode layer 230 in the second resonance region 100B, the thickness of the first metal material layer 260' is much smaller than that of the upper electrode layer 230, and thus does not significantly affect the measurement result. For example, the upper electrode layer 230 has a thickness of 1000A-4000A, and the first metal material layer 260' has a thickness equal to or less than 200A.
In addition, after the upper electrode layer 230 is prepared, the method further includes: the sacrificial layer in the cavity 110a is removed to release the space of the cavity 110 a.
< example two >
The difference from the first embodiment is that, in the present embodiment, the metal ring 240 is formed on the upper electrode layer 230. Referring specifically to fig. 9, the metal ring 240 is formed at an end of the upper electrode layer 230.
In this embodiment, the forming method of the upper electrode layer 230 and the metal ring 240 includes, for example: first, a sputtering process is performed at a third temperature T3 to form a third metallic material layer for constituting the upper electrode layer; then, forming the metal ring 240 on the third metal material layer, wherein the metal ring 240 may be formed by a lift-off process to avoid etching damage to the third metal material layer; then, an etching process is performed to pattern the third metal material layer to form the upper electrode layer 230.
Likewise, in the sputtering process of the third metallic material layer, the third temperature T3 is at least 150 ℃ higher than the first temperature T1 or the second temperature T2, for example, the third temperature T3 is not lower than 200 ℃. And, the upper electrode layer 230 having high temperature material properties may be formed by heating the substrate 100 to adjust the surface temperature of the substrate 100 to about the third temperature T3 and performing a sputtering process. And in the etching process of the third metal material layer, the method specifically comprises the following steps: the etching process is performed under a mask of a patterned mask layer, which covers the electrode regions of the respective resonance regions (in this case, correspondingly covers the metal rings 240 in the respective resonance regions), so that the metal rings 240 are not damaged during the etching process.
Based on the above-mentioned forming method, the structure of the prepared semiconductor device is described below, and specifically, referring to fig. 8 and 9, the semiconductor device includes: a substrate 100 and a resonant structure formed on the substrate 100.
Specifically, the substrate 100 has at least one resonance region, and a first resonance region 100A and a second resonance region 100B are illustrated in this embodiment. And, the resonance structure formed in each resonance region includes the lower electrode layer 210, the piezoelectric layer 220, and the upper electrode layer 230.
As described with continued reference to fig. 8 and 9, among the plurality of resonance regions of the semiconductor device, a mass loading layer 250 may be provided in a part of the resonance regions, and a mass loading layer may also be not provided in another part of the resonance regions. In this way, the plurality of resonant structures in the semiconductor device have different resonant frequencies. Wherein the thickness of the mass loading layer 250 can be correspondingly adjusted as desired, e.g., the thickness of the mass loading layer 250 can be less than or equal to 1000 a, or greater than 1000 a.
Further, in the resonance region where the mass loading layer 250 is disposed, the mass loading layer 250 is disposed below the upper electrode layer 230, that is, the upper electrode layer 230 covers the mass loading layer 250. Based on the structure thus configured, the mass loading layer 250 is preferably prepared during the preparation process, and then the upper electrode layer 230 is formed. Therefore, interference of the upper electrode layer 230 can be shielded during the process of preparing the mass loading layer 250, thereby achieving stable and accurate thickness measurement of the mass loading layer 250.
It should be noted that, when the upper electrode layer 230 is formed after the mass loading layer 250, for a resonance region (for example, the first resonance region 100A) where the mass loading layer 250 and the upper electrode layer 230 are disposed at the same time, the thickness measurement of the upper electrode layer 230 at this time may cause instability of the measurement result due to the presence of the mass loading layer 250 therebelow. In particular, when the upper electrode layer 230 and the mass loading layer 250 are made of the same metal material and are formed at different temperatures (for example, the upper electrode layer 230 is a high-temperature molybdenum layer formed by sputtering at a high temperature, and the mass loading layer 250 is a low-temperature molybdenum layer formed by sputtering at a low temperature), an interface between the upper electrode layer 230 and the mass loading layer 230 is unstable, which leads to a problem of unstable detection results during the thickness measurement process.
However, it should be appreciated that the substrate 100 also has regions on it where the mass loading layer 250 is not located, such as: the region between the adjacent resonance regions, or the resonance region where the mass loading layer 250 is not disposed (i.e., the second resonance region 100B). The mass loading layer 250 can be avoided by the region where the mass loading layer is not disposed, and the thickness of the upper electrode layer 230 can be stably and accurately measured.
With continued reference to fig. 8 and 9, the semiconductor device further includes: a bottom metal layer 260 contacting and covering the piezoelectric layer 220 and located at least between the mass loading layer 250 and the piezoelectric layer 260. Wherein a thickness of the underlying metal layer 260 is, for example, equal to or less than 200 a. It is considered that the present embodiment is implemented by disposing the bottom metal layer 260 on the piezoelectric layer 220, so that the mass loading layer 250 can be prepared prior to the upper electrode layer 230.
In this embodiment, the bottom metal layer 260 is disposed in each resonance region and is located below the upper electrode layer 230, that is, the bottom metal layer 260 and the upper electrode layer 230 are disposed in each resonance region. Thus, it can be understood that: the bottom metal layer 260 forms a part of an upper electrode structure, and the bottom metal layer 260 and the upper electrode layer 230 together form an upper electrode structure. In this case, the process of preparing the upper electrode structure includes: a first metal material layer is prepared before the mass loading layer 250, and a third metal material layer is prepared after the mass loading layer 250, and simultaneously a patterning process is performed on the third metal material layer and the first metal material layer to form the upper electrode layer 230 and the underlying metal layer 260 for constituting the upper electrode structure.
Further, the semiconductor device further includes: a metal ring 240, wherein the metal ring 240 is disposed at an edge position of the resonance region and above the mass loading layer 250. Wherein the metal ring 240 may be disposed between the mass loading layer 250 and the upper electrode layer 230 and covered by an end of the upper electrode layer 230; alternatively, the metal ring 240 may be further disposed on the upper electrode layer 230 at an end of the upper electrode layer 230.
In summary, in the method for forming a semiconductor device provided by the present invention, the mass loading layer is preferentially prepared, so that the mass loading layer can be stably and accurately measured in the preparation process without being interfered by the upper electrode layer. In a specific scheme, the first metal material layer is formed on the piezoelectric layer, so that the mass loading layer can be preferentially prepared by using a stripping process.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. Also, while the present invention has been described with reference to the preferred embodiments, the embodiments are not intended to be limiting. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (11)
1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein at least one resonance area is arranged on the substrate;
sequentially forming a lower electrode layer and a piezoelectric layer in each resonance region of the substrate;
performing a sputtering process at a first temperature to form a first metallic material layer overlying the piezoelectric layer;
performing a sputtering process and a lift-off process at a second temperature to form a mass loading layer on a first metallic material layer of at least one resonance region, the second temperature and the first temperature differing by at most 10 ℃; and the number of the first and second groups,
and forming an upper electrode layer and a metal ring in each resonance region, wherein the metal ring is located at an edge position of the resonance region and within a region of the upper electrode layer, the upper electrode layer is formed by performing a sputtering process and an etching process at a third temperature, the third temperature is higher than the first temperature or the second temperature by at least 150 ℃, and the metal ring is formed by performing a sputtering process and a stripping process.
2. The method of forming a semiconductor device according to claim 1, wherein the method of forming the mass loading layer comprises:
forming a patterned photoresist layer on the first metal material layer;
performing a sputtering process at a second temperature to form a second metal material layer, wherein the second metal material layer is formed in the region exposed from the patterned photoresist layer and is also formed on the patterned photoresist layer; and the number of the first and second groups,
and stripping the patterned photoresist layer by using a stripping liquid to remove the metal material on the patterned photoresist layer, and forming the mass loading layer by using the reserved metal material.
3. The method of forming a semiconductor device according to claim 1, wherein a thickness of the first metal material layer is less than or equal to 200 a.
4. The method for forming a semiconductor device according to claim 1, wherein the first temperature and the second temperature are both 50 ℃ or lower, and wherein the third temperature is 200 ℃ or higher.
5. The method for forming a semiconductor device according to claim 1, wherein the second temperature is the same as the first temperature.
6. The method of forming a semiconductor device according to claim 1, wherein the upper electrode layer and the mass loading layer each include the same metal material.
7. The method for forming a semiconductor device according to claim 1, wherein the metal ring is prepared prior to the upper electrode layer, an end portion of the upper electrode layer covering the metal ring; alternatively, the metal ring is formed on the upper electrode layer and located at an end portion of the upper electrode layer.
8. The method of forming a semiconductor device of claim 1, wherein the method of forming the mass loading layer further comprises performing a thickness measurement of the mass loading layer, the method of thickness measurement comprising: and taking the piezoelectric layer as a signal reflection layer, and obtaining the thickness value of the film layer above the piezoelectric layer according to the reflection signal reflected by the piezoelectric layer.
9. The method for forming a semiconductor device according to claim 1, wherein the substrate has a first resonance region in which the mass loading layer is formed and a second resonance region in which the mass loading layer is not formed;
and the method of forming the upper electrode layer further includes also performing a thickness measurement of the upper electrode layer in the second resonance region, the thickness measurement method including: and taking the piezoelectric layer as a signal reflection layer to obtain a film layer thickness value above the piezoelectric layer according to a reflection signal reflected by the piezoelectric layer.
10. A semiconductor device manufactured by the method for forming as claimed in any one of claims 1 to 9, comprising:
a substrate having at least one resonant region thereon;
a lower electrode layer provided at least on the substrate of each resonance region;
a piezoelectric layer formed on the substrate and covering each resonance region;
a bottom metal layer contacting and covering the piezoelectric layer;
a mass loading layer disposed on the bottom metal layer of the at least one resonance region; and the number of the first and second groups,
and the upper electrode layer and the metal ring are arranged in each resonance area, and the metal ring surrounds the edge of each resonance area and is positioned in the area range of the upper electrode layer.
11. The semiconductor device according to claim 10, wherein an end portion of the upper electrode layer covers the metal ring; alternatively, the metal ring is formed on the upper electrode layer at an end portion of the upper electrode layer.
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| CN1929303A (en) * | 2005-09-09 | 2007-03-14 | 安华高科技无线Ip（新加坡）私人有限公司 | Adjusted frequency temperature coefficient resonator |
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