CN112689792A - Liquid crystal display device having a plurality of pixel electrodes - Google Patents

Liquid crystal display device having a plurality of pixel electrodes Download PDF

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Publication number
CN112689792A
CN112689792A CN201880097489.5A CN201880097489A CN112689792A CN 112689792 A CN112689792 A CN 112689792A CN 201880097489 A CN201880097489 A CN 201880097489A CN 112689792 A CN112689792 A CN 112689792A
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electrode
semiconductor film
liquid crystal
display device
crystal display
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奥本惠隆
山本明弘
长谷川浩二
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Sakai Display Products Corp
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Sakai Display Products Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Abstract

The liquid crystal display device includes a TFT substrate having a thin film transistor and a pixel electrode connected to the thin film transistor; a semiconductor film laminated on the gate electrode via a gate insulating film and having a planar shape with a first side and a second side respectively overlapping the gate electrode in a plan view; and a first electrode and a second electrode formed on the semiconductor film and connected to the pixel electrode, respectively, wherein the second electrode is disposed to face the first electrode, the first side and the second side of the semiconductor film are adjacent to each other at a predetermined angle, and the first electrode at least partially covers the first side and the second side of the semiconductor film, respectively.

Description

Liquid crystal display device having a plurality of pixel electrodes
Technical Field
The present invention relates to a liquid crystal display device.
Background
A liquid crystal display device includes two substrates sandwiching a liquid crystal layer including liquid crystal molecules, and a pixel circuit for applying a voltage to an electrode (pixel electrode) of each of a plurality of pixels arranged in a matrix is formed on one of the two substrates (TFT substrate). In addition, a common electrode that faces the pixel electrode with the liquid crystal layer interposed therebetween is formed on the other substrate (counter substrate). The orientation of the liquid crystal molecules in the liquid crystal layer changes for each pixel according to the potential difference between the pixel electrode and the common electrode, and a desired image is displayed on the display screen. The pixel circuit is mainly composed of a Thin Film Transistor (TFT), and switches a state of applying a voltage to the pixel electrode by switching on and off of the TFT. For example, as shown in patent document 1, a TFT includes a gate electrode formed on a surface of a glass plate or the like; a semiconductor film formed over the gate electrode with an insulating film interposed therebetween; and a source electrode and a drain electrode formed on the semiconductor film, respectively. The TFT of patent document 1 includes a semiconductor film formed inside a gate electrode in a plan view, and a drain electrode and a source electrode formed on the semiconductor film so as to face each other, and the drain electrode is connected to a pixel electrode of a liquid crystal display device.
Fig. 7 shows an example of a pixel circuit in the liquid crystal display device, together with a liquid crystal layer LC and a pixel electrode 120 which are schematically shown. In fig. 7, the pixel circuit has a TFT103, and the source of the TFT103 is connected to a data bus line (source bus line) 111, the gate is connected to a scanning bus line (gate bus line) 112, and the drain is connected to a pixel electrode 120. Further, an auxiliary capacitance Cs is formed in parallel with the liquid crystal layer LC. When the TFT103 is turned on by the voltage of the scanning bus line 112, a voltage based on the image data is applied from the data bus line 111 to the pixel electrode 120, and charges corresponding to the image data are accumulated in the capacitance of the liquid crystal layer LC and the storage capacitor Cs. Therefore, even when the TFT103 is switched to the off state, the potential of the pixel electrode 120 is maintained, and light from the light source is transmitted through the liquid crystal layer LC by a light amount corresponding to the potential difference between the pixel electrode 120 and the common electrode 121 for each pixel.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open publication No. 10-20298
Disclosure of Invention
Technical problem to be solved by the invention
However, as shown in fig. 7, a parasitic capacitance Cgd exists in the TFT structure between the gate and the drain of the TFT 103. Therefore, when the TFT103 is turned off, part of the electric charge stored in the storage capacitor Cs and the like is introduced into the parasitic capacitance Cgd depending on the magnitude of the parasitic capacitance Cgd. Fig. 8 shows transition of the potential (pixel voltage Vd) of the pixel electrode 120 in two frames (N frame and N +1 frame) in the frame inversion driving. As shown in fig. 8, when the TFT103 is switched from the on state (H1 interval) to the off state (H2 interval), the pixel voltage Vd is lowered by a voltage (pull-in voltage or feed-through voltage) Δ V corresponding to the amount of electric charge introduced into the parasitic capacitance Cgd. Therefore, the original luminance based on the image data cannot be obtained in each pixel due to the variation of the parasitic capacitance value, and display unevenness such as luminance unevenness and color unevenness occurs in the screen of the liquid crystal display device, thereby deteriorating the display quality. It is considered that the image data is corrected based on the variation of the pull-in voltage Δ V, but since the parasitic capacitance Cgd can vary in size for each liquid crystal display device and each pixel, it is difficult to always appropriately correct the image data of all the pixels.
Accordingly, an object of the present invention is to provide a liquid crystal display device with less degradation of display quality due to variation in parasitic capacitance of TFTs that drive pixels.
Technical solution for solving technical problem
A liquid crystal display device according to an embodiment of the present invention includes: a TFT substrate including a thin film transistor and a pixel electrode connected to the thin film transistor; an opposite substrate having a common electrode facing the pixel electrode with a liquid crystal layer interposed therebetween, the thin film transistor including: a semiconductor film which is laminated on the gate electrode with a gate insulating film interposed therebetween and has a planar shape including a first side and a second side which overlap with the gate electrode in a plan view; a first electrode and a second electrode formed on the semiconductor film, respectively, the first electrode being connected to the pixel electrode, the second electrode being provided to face the first electrode; the first and second sides are adjacent to each other at a predetermined angle, and the first electrode at least partially covers the first and second sides, respectively.
Advantageous effects
According to one embodiment of the present invention, in a liquid crystal display device, it is possible to reduce a decrease in display quality due to a variation in parasitic capacitance of TFTs constituting a pixel circuit.
Drawings
Fig. 1 is a diagram showing an example of a cut line passing through a TFT of a liquid crystal display device according to a first embodiment of the present invention.
Fig. 2 is a plan view showing an example of a TFT in the liquid crystal display device of the first embodiment.
Fig. 3 is a plan view showing another example of the TFT in the liquid crystal display device of the first embodiment.
Fig. 4 is a plan view showing another example of the TFT in the liquid crystal display device of the first embodiment.
Fig. 5 is a plan view showing another example of the TFT in the liquid crystal display device of the first embodiment.
Fig. 6A is a plan view showing an example of a TFT of a liquid crystal display device according to a second embodiment of the present invention.
Fig. 6B is a plan view showing that the area of the channel does not substantially vary in the TFT of the example of fig. 6A.
Fig. 6C is a plan view showing that the area of the channel does not substantially vary in the TFT of the example of fig. 6A.
Fig. 7 is a circuit diagram showing an example of a pixel circuit of the liquid crystal display device.
Fig. 8 is a diagram showing transition of a pixel voltage of the liquid crystal display device.
Fig. 9 is a plan view showing an example of a TFT in a conventional liquid crystal display device.
Detailed Description
The present inventors have made extensive studies to reduce display unevenness caused by parasitic capacitance of a TFT for driving a pixel. Then, the present inventors have found that display unevenness can be suppressed by forming the semiconductor film and an electrode (for example, a drain electrode) connected to the pixel electrode to be appropriately overlapped with each other. In this regard, a plan view of the TFT103, which is an example of a TFT in a conventional liquid crystal display device, will be described with reference to fig. 9.
The TFT103 includes a gate electrode 104 formed on a base substrate (not shown) such as a glass plate; a semiconductor film 106 formed on the gate electrode 104 with a gate insulating film (not shown) therebetween and formed inside the gate electrode 104 in a plan view; and a drain electrode 107 and a source electrode 108 formed on the semiconductor film 106 so as to face each other. The drain electrode 107 is connected to a pixel electrode not shown. In addition, a region of the semiconductor film 106 sandwiched between the drain electrode 107 and the source electrode 108 and denoted by Ch denotes a channel formed in the semiconductor film 106.
In general, when a TFT for driving a pixel of a liquid crystal display device is configured in a bottom gate type as in the example of fig. 9, a semiconductor film 106 is formed inside a gate electrode 104 in a plan view. This prevents the semiconductor film 106 from being excited by light transmitted through the base substrate, not shown. Further, since the gate electrode 104 is larger than the semiconductor film 104, even a small pixel can be formed relatively easily, and the liquid crystal display device can be applied to high definition. Further, since the formation of a U-shaped source, which has been frequently used in the related art, tends to become difficult as the pixel is miniaturized, a configuration in which the drain 107 and the source 108 are opposed to each other in one direction as in the example of fig. 9 is used. However, the present inventors have found that in the configuration as in the example of fig. 9, the parasitic capacitance Cgd (see fig. 7) varies due to a factor that is not considered to be a problem in the configuration using the U-shaped source.
In the TFT103 configured as in the example of fig. 9, the parasitic capacitance Cgd is determined based on the area of the portion of the drain electrode 107 that overlaps the gate electrode 104. Here, when the TFT103 is in an on state, carriers are excited in the semiconductor film 106, and therefore the semiconductor film 106 functions as a conductor. That is, a region of the semiconductor film 106 closer to the drain electrode 107 than the intermediate line M passing through the middle between the drain electrode 107 and the source electrode 108 (hereinafter, also referred to as "second region") is considered to have the same effect as the drain electrode 107 on the formation of the parasitic capacitance Cgd. Therefore, the parasitic capacitance Cgd when the TFT103 is in the on state is determined by taking into consideration the sum of the area of the second region of the semiconductor film 106 and the area of a region (hereinafter, also referred to as "first region") of the drain electrode 107 that overlaps with the gate electrode 104, except for the portion that overlaps with the semiconductor film 106. Therefore, variation in parasitic capacitance Cgd between the TFTs 103, that is, variation in the pull-in voltage Δ V (see fig. 8) is caused by variation in the area of the second region of the semiconductor film 106 and variation in the area of the first region of the drain 107 between the TFTs 103.
In fig. 9, two-dot chain lines, reference numerals 106a and 107a denote examples of enlarged portions which are newly occupied when the second region of the semiconductor film 106 and the first region of the drain 107 move in the enlarging direction. As is apparent from fig. 9, in the case where the drain electrode 107 overlaps only one of the four sides of the semiconductor film 106 having a rectangular planar shape, the enlarged portion 106a of the semiconductor film 106 is much larger than the enlarged portion 107a of the drain electrode 107. Although not shown, even when the semiconductor film 106 and the drain electrode 107 are deviated in the direction of decreasing, the magnitude relationship between the respective reduced portions is the same as that between the enlarged portions shown in fig. 9.
Variations in the area of the second region of the semiconductor film 106 and the area of the first region of the drain 107 among the plurality of TFTs 103 are caused by, for example, shifts in the edge of an exposed portion and shifts in the edge of an etched portion when these regions are formed by using a photolithography technique. The variations occur independently of each other in the step of forming the semiconductor film 106 and the step of forming the drain electrode 107. As shown in the example of fig. 9, when the second region of the semiconductor film 106 and the first region of the drain electrode 107 vary in the expansion direction, if the expanded portion 106a of the semiconductor film 106 is much larger than the expanded portion 107 of the drain electrode 107, the parasitic capacitance Cgd varies greatly as long as the second region of the semiconductor film 106 varies. Both the area of the second region of the semiconductor film 106 and the area of the first region of the drain electrode 107 may vary, but it is considered that only one of them may vary in many cases. Therefore, even if either the area of the second region of the semiconductor film 106 or the area of the first region of the drain electrode 107 fluctuates independently, the occurrence of visible display unevenness can be reduced, for example, by forming the semiconductor film 106 and the drain electrode 107 so that the fluctuation amount falls within a certain range.
Further, one of the first region of the drain 107 and the second region of the semiconductor film 106 varies in the expansion direction or the contraction direction, and the other varies in the opposite direction. Therefore, by forming the second region of the semiconductor film 106 and the first region of the drain electrode 107 so that their respective amounts of fluctuation are as close as possible, the influence on the parasitic capacitance Cgd when the two change in opposite directions can be cancelled.
The area of the enlarged portion 107a when the first region of the drain 107 varies in the enlargement direction is a product of a length (hereinafter, also referred to as "first length") L1(═ L1a + L1b) of a portion of the outer edge of the drain 107 which overlaps with the gate electrode 104 without passing through the semiconductor film 106 and a displacement width S1 of the outer edge of the drain 107. The area of the enlarged portion 106a when the second region of the semiconductor film 106 varies in the enlargement direction is a product of the length of a portion of the outer edge of the second region of the semiconductor film 106 not covered with the drain 107 (hereinafter also referred to as "second length") L2 (L2 a + L2b + L2c + L2d) and the displacement width S2 of the outer edge of the second region of the semiconductor film 106, plus 2 × (S2)2(enlarged areas at both corners of the second region). The displacement widths S1 and S2 are not necessarily the same, but it is considered that a large difference does not occur on average. Therefore, by forming the drain electrode 107 so as to overlap with the semiconductor film 106 as appropriate and reducing the difference between the first length L1 and the second length L2, the amount of fluctuation in the first region of the drain electrode 107 and the amount of fluctuation in the second region of the semiconductor film 106 are suppressed to be close to each other. Therefore, if a difference occurs in either the area of the first region of the drain electrode 107 or the area of the second region of the semiconductor film 106, it is possible to reduce the occurrence of a large variation in the parasitic capacitance Cgd, and for example, the occurrence of display unevenness that is visually observed can be reduced. Further, by making the first length L1 of the drain electrode 107 and the second length L2 of the semiconductor film 106 substantially the same, even when the first region of the drain electrode 107 and the second region of the semiconductor film 106 fluctuate in opposite directions as described above, fluctuation of the parasitic capacitance Cgd and display unevenness can be extremely reduced.
The present inventors have conducted extensive studies and, as a result, have obtained the above findings. Hereinafter, a liquid crystal display device according to an embodiment based on this finding will be described with reference to the drawings. The materials, shapes, relative positional relationships of the components, and the like in the embodiments described below are merely examples, except for the case where they are clearly defined. The liquid crystal display device of the present invention is not to be construed as being limited by the above illustration.
[ embodiment 1]
In fig. 1, a liquid crystal display device 1 of embodiment 1 is shown by a cross-sectional view at a cut line passing through a TFT3 in a certain pixel. Fig. 2 is a plan view showing an example of the TFT3 in the liquid crystal display device according to the present embodiment. As shown in fig. 1, the liquid crystal display device 1 includes a TFT substrate 2 including a Thin Film Transistor (TFT)3 and a pixel electrode 9 connected to a TFT 3; and an opposite substrate 10 having a common electrode 11 facing the pixel electrode 9 through the liquid crystal layer LC. The TFT3 includes a gate electrode 4 formed on a base substrate 2 a; a semiconductor film 6 laminated on the gate electrode 4 with a gate insulating film 5 covering the gate electrode 4 interposed therebetween; a first electrode 7 and a second electrode 8 which are formed on the semiconductor film 6, respectively, and are opposed to the first electrode 7. Further, between the first electrode 7 and the semiconductor film 6, the contact layer 60 is formed of a semiconductor having a high impurity concentration, and the second electrode 8. A planarization film 14a is formed on the TFT3, and a pixel electrode 9 is formed on the surface of the planarization film 14 a. The first electrode 7 is connected to the pixel electrode 9 via a conductive contact 15. In fig. 1, a capacitor electrode 20 is formed on the base substrate 2a in parallel with the gate electrode 4, and an auxiliary capacitor Cs is formed between the capacitor electrode 20 and the first electrode 7 and between the capacitor electrode and the pixel electrode 9.
A first alignment film 17a is formed on the planarization film 14a and the pixel electrode 9, and a nematic liquid crystal or the like is injected between the first alignment film 17a and the second alignment film 17b to form a liquid crystal layer LC. The second alignment film 17b is laminated on the surface of the counter substrate 10 facing the TFT substrate 2 together with the color filter 19, the planarization film 14b, and the common electrode 11. The counter substrate 10 is disposed at a predetermined interval from the TFT substrate 2 by a spacer not shown. Further, although not shown, a polarizing plate may be provided on each of the surfaces of the TFT substrate 2 and the counter substrate 10 facing the opposite direction of the liquid crystal layer LC, and in the case where the liquid crystal display device 1 is transmissive, a light source such as an LED or a light guide plate (both not shown) may be provided so as to face the polarizing plate provided on the TFT substrate 2. Since each component such as the pixel electrode 9, the first and second alignment films 17a and 17b, and the liquid crystal layer LC may have a general structure, detailed description thereof will be omitted.
One of the first electrode 7 and the second electrode 8 is a drain, and the other is a source. In general, in a TFT, two electrodes formed over a semiconductor film have the same function as each other in structure, and therefore, the TFT3 can function appropriately regardless of whether one of a source electrode and a drain electrode is connected to the pixel electrode 9. Hereinafter, the liquid crystal display device of the embodiment will be described as an electrode connected to the pixel electrode 9 as a drain electrode. Therefore, the first electrode 7 and the second electrode 8 are referred to as a drain and a source, respectively.
As shown in fig. 2, the semiconductor film 6 is formed inside the gate electrode 4 in a plan view, and has a planar shape including a first side 61 and a second side 62 which overlap with the gate electrode 4 in a plan view. The first side 61 and the second side 62 are adjacent to each other at a prescribed angle. In the semiconductor film 6, a channel Ch is formed when a predetermined on voltage is applied to the gate electrode 4. In the example of fig. 2, the semiconductor film 6 has a rectangular, specifically, substantially square planar shape, and the first side 61 and the second side 62 are substantially perpendicular and adjacent to each other with one vertex therebetween. Also, the first electrode 7 at least partially covers the first and second sides 61, 62. In other words, the first electrode 7 is formed such that, of the two outer edges of the first electrode 7 that do not intersect the first edge 61 of the semiconductor film 6, the outer edge (first outer edge 71) that is close to the first edge 61 is positioned further outside the semiconductor film 6 than the first edge 61. As a result, the first side 61 and the second side 62 are respectively partially covered by the first electrode 7. In fig. 2, the line M represents an intermediate line set midway between the first electrode 7 and the second electrode 8, as in the intermediate line M in fig. 9 referred to previously.
In this manner, in this embodiment, the first electrode 7 connected to the pixel electrode 9 (see fig. 1) at least partially covers the first side 61 and the second side 62 of the semiconductor film 6. Therefore, the difference between the first length L1(═ L1a + L1b + P1) of the first electrode 7 and the second length L2(═ L2a + L2b + L2c) of the semiconductor film 6 can be reduced. Therefore, as described above, the variation in the parasitic capacitance Cgd (see fig. 1) between the drain (first electrode 7) and the gate 4 among the plurality of TFTs 3 can be reduced, and display unevenness can be reduced. In the above and the following description, unless otherwise specified, "length" is a (regular) length in design of the first electrode 7, the semiconductor film 6, and the like.
In the structure in which the drain electrode 107 overlaps only one side of the semiconductor film 106 as in the conventional TFT103 shown in fig. 9, the first length L1 of the drain electrode 107 is about twice as long as the width of a margin portion of the gate electrode 104 not covered with the semiconductor film 106, and is much shorter than the second length L2 of the semiconductor film 106. Even if the width of the drain 107 (the length in the vertical direction in fig. 9) is slightly increased, the first length L1 itself does not change. The first length L1 of the drain 107 can be increased by enlarging the gate 104 with respect to the semiconductor film 106, but such enlargement is not preferable from the viewpoint of downsizing of the pixel.
In contrast, in this embodiment, the first electrode 7 connected to the pixel electrode 9 overlaps not only the second side 62 of the semiconductor film 6, which is substantially orthogonal to the opposing direction (first direction X) of the first electrode 7 and the second electrode 8, but also the first side 61. As a result, the first length L1 of the first electrode 7 can be extended in the first direction X, and the second length L2 of the semiconductor film 6 can be reduced. That is, the first length L1 of the first electrode 7 can be made longer than conventional, and the second length L2 of the semiconductor film 6 can be made shorter than conventional. Therefore, the amount of fluctuation of the first region of the first electrode 7 (for example, the total of the enlarged portions 7a shown in fig. 2) and the amount of fluctuation of the second region of the semiconductor film 6 (for example, the total of the enlarged portions 6a shown in fig. 2) can be made close to each other. In addition, the fluctuation amount of the second region of the semiconductor film 6 can also be suppressed. Therefore, variations in the parasitic capacitance Cgd between the TFTs 3 can be reduced, and display unevenness can be reduced.
The term "planar view" means that the liquid crystal display device 1 is viewed with a line of sight parallel to the thickness direction of the TFT substrate 2. Further, "adjacent at a predetermined angle" means that the first side 61 and the second side 62 of the semiconductor film 6 are adjacent to each other with a corner portion of the planar shape of the semiconductor film 6 interposed therebetween. That is, the first side 61 and the second side 62 of the semiconductor film 6 may not be, for example, a set of parallel opposite sides in a rectangular shape, and the "predetermined angle" may be any angle other than 0 degree and 180 degrees. The corner portion sandwiched between the first side 61 and the second side 62 may be a vertex of a polygon as in the example of fig. 2, or may be a circle or the like chamfered.
According to this embodiment mode, the first length L1 of the first electrode 7 and the second length L2 of the semiconductor film 6 can be easily made close to each other. The first electrode 7 and the semiconductor film 6 are preferably formed so that the first length L1 of the first electrode 7 is substantially equal to the second length L2 of the semiconductor film 6. However, these lengths need not be the same.
Note that, the displacement width S1 of the first region of the first electrode 7 and the displacement width S2 of the second region of the semiconductor film 6 can be estimated in advance, and when they are different, the first length L1 of the first electrode 7 and the second length L2 of the semiconductor film 6 may be lengths based on the displacement width S1 and the displacement width S2, respectively. For example, the first length L1 of the first electrode 7 and the second length L2 of the semiconductor film 6 may be lengths in which the ratio of the second length L2 of the semiconductor film 6 to the first length L1 of the first electrode 7 is substantially equal to the ratio of the displacement width S1 to the displacement width S2.
In the example of fig. 2, the first electrode 7 is drawn out from a region on the gate electrode 4 to the outside along a first direction X in a direction in which the first electrode 7 and the second electrode 8 face each other (a direction in which the first electrode 7 and the second electrode 8 face each other), and is connected to the pixel electrode 9 (see fig. 1). By drawing the first electrode 7 in the first direction X, the first electrode 7 and the pixel electrode 9 can be connected in a short path when there is a connection point (for example, a via contact 15 in the example of fig. 1) with the pixel electrode 9 in the direction opposite to the second electrode 8. The second electrode 8 is also drawn out from a region above the gate electrode 4 along the first direction X, and is connected to, for example, a data bus line, not shown.
In the example of fig. 2, the first side 61 of the semiconductor film 6 extends substantially parallel to the first direction X and substantially orthogonal to the second side 62. The rectangular semiconductor film 6 and the first electrode 7 can be efficiently arranged. The first electrode 7 partially covers the first edge 61 so as to ensure a predetermined distance from the second electrode 8, not the entire first edge 61.
In the example of fig. 2, the width of the first electrode 7 in the direction along the second side 62 of the semiconductor film 6 (the second direction Y orthogonal to the first direction X) is shorter than the length of the second side 62. Therefore, the fluctuation amount of the first region of the first electrode 7 can be prevented from being larger than the fluctuation amount of the second region of the semiconductor film 6. The width of the first electrode 7 in the second direction Y may be the same as the length of the second side 62, or may be longer than the length of the second side 62. The width in the second direction Y in the first electrode 7 is arbitrarily selected from the viewpoint of reducing the deviation of the parasitic capacitance Cgd.
In the example of fig. 2, the first electrode 7 has the following planar shape in a plan view: the planar shape includes a first opposing side 70 opposing the second electrode 8, and a first outer side 71 extending from an end portion of the first opposing side 70 located outside the semiconductor film 6 substantially in parallel with the first side 61 of the semiconductor film 6. The first electrode 7 has a rectangular shape on the gate electrode 4, and has a first outer side 71 which is close to the first side 61 of the semiconductor film 6 and extends substantially parallel to the first side 61 in the outer edge thereof. The first outer side 71 is positioned between the outer edge 41 of the gate electrode 4 close to the first side 61 of the semiconductor film 6 and the first side 61 of the semiconductor film 6, and is positioned so as to overlap the gate electrode 4 without passing through the semiconductor film 6. That is, the first outer side 71 is disposed outside the semiconductor film 6 with respect to the first side 61 of the semiconductor film 6.
In manufacturing the liquid crystal display device 1, a relative positional shift may occur between the first electrode 7 and the semiconductor film 6. When the first outer side 71 of the first electrode 7 is shifted to the inside of the semiconductor film 6 due to the positional shift, the configuration of the present embodiment cannot be realized. Therefore, the distance P1 between the first outer side 71 of the first electrode 7 and the first side 61 of the semiconductor film 6 is preferably made larger than the maximum value of the relative positional deviation between the first electrode 7 and the semiconductor film 6. However, if the interval P1 is too large, the TFT3 is increased, and therefore, the interval P1 is preferably higher than the maximum value of the relative positional shift between the first electrode 7 and the semiconductor film 6 by about 0.5 μm. For example, the distance P1 between the first outer side 71 of the first electrode 7 and the first side 61 of the semiconductor film 6 is not less than l μm and not more than 2 μm, preferably 1.5 μm.
The semiconductor film 6 has a substantially square planar shape in the example of fig. 2. However, the semiconductor film 6 may have a planar shape as follows: other planar shapes including at least a first side 61 and a second side 62. For example, the planar shape of the semiconductor film 6 may be a polygon other than a quadrangle. In this case, since the first electrode 7 at least partially covers the first side 61 and the second side 62, the fluctuation amount of each of the first region of the first electrode 7 and the second region of the semiconductor film 6 can be made closer to each other than in the case where the first electrode 7 overlaps only one side of the semiconductor film 6.
The gate 4 also has a substantially square planar shape in the example of fig. 2, but may have another polygonal shape such as a rectangle, or may have any planar shape.
The gate electrode 4, the first electrode 7, and the second electrode 8 may be formed using, for example, titanium, aluminum, or a copper-titanium alloy. The semiconductor film 6 is formed using, for example, amorphous silicon, Low Temperature Polysilicon (LTPS), a mixed crystal semiconductor, or the like. Further, the gate insulating film 5 is formed of a silicon oxide film (SiO)2) Or a silicon nitride film (SiN)x) And the like.
Fig. 3 to 5 show other examples of the TFT3 in the liquid crystal display device according to the present embodiment. The description is made with reference to the drawings in turn.
Fig. 3 shows an example in which the entire second side 62 of the semiconductor film 6 along the second direction Y orthogonal to the first direction X as the opposing direction of the first electrode 7 and the second electrode 8 is covered with the first electrode 7. As shown in the example of fig. 3, the first electrode 7 may cover the entire second side 62 of the semiconductor film 6. Therefore, the width in the second direction Y in the first electrode 7 can be longer than the second side 62 of the semiconductor film 6. In other words, both sides of the first electrode 7 that are substantially parallel to the first direction X may be located outside the semiconductor film 6. For example, when the first electrode 7 cannot be formed long in the first direction X, the first length L1 of the first electrode 7 may be made to approach a desired length by covering the entire second side 62 of the semiconductor film 6 in this manner. In the example of fig. 3, the first length L1(═ L1a + L1b + L1c + P1) of the first electrode 7 is also substantially the same as the second length L2(═ L2a + L2c) of the semiconductor film 6.
In the example of fig. 4, the semiconductor film 6 has a shape in which four corners of a rectangular shape in a plan view are rounded by chamfering. However, in the example of fig. 4, the semiconductor film 6 also has the first side 61 and the second side 62 sandwiching the chamfered corner portion, and the first and second sides 61, 62 of the semiconductor film 6 are partially covered with the first electrode 7. Thus, the first length L1(═ L1a + L1b + P1) of the first electrode 7 can be made close to the second length L2(═ L2a + L2b + L2c- α) of the semiconductor film 6, and variation in parasitic capacitance Cgd (see fig. 1) can be suppressed. Further, α is the length of the rounded and shortened portion of the corner in the length L2.
In the example of fig. 5, the first electrode 7 is drawn from above the gate electrode 4 along a second direction Y substantially orthogonal to the first direction X which is the opposing direction of the first electrode 7 and the second electrode 8. For example, when a connection point with the pixel electrode 9 (see fig. 1) is located below or above in fig. 5, the first electrode 7 can be drawn out from above the gate electrode 4 in the second direction Y, whereby the first electrode 7 and the pixel electrode 9 can be connected in a short path. In the example of fig. 5, the first and second sides 61, 62 of the semiconductor film 6 are also partially covered by the first electrode 7. Therefore, the first length L1(═ L1a + L1b + L1c) of the first electrode 7 can be made close to the second length L2(═ L2a + L2b + L2c) of the semiconductor film 6, and variation in the parasitic capacitance Cgd (see fig. 1) can be suppressed.
The shape and size of the second electrode 8 and the direction of extraction from the gate 4 are not limited to those shown in fig. 2
Figure BDA0002973362750000131
In the example shown in fig. 5, the second electrode 8 may have any shape and size, and may be drawn from the gate electrode 4 in any direction.
[ embodiment 2]
Next, the TFT3a in the liquid crystal display device according to embodiment 2 will be described with reference to fig. 6A to 6C each showing a plan view of the TFT3 a. Note that, in the liquid crystal display device of embodiment 2, the components other than the TFT3a are the same as those in the liquid crystal display device 1 of embodiment 1, and therefore, a re-description of these similar components is omitted. FIG. 6A
Figure BDA0002973362750000132
Fig. 6C shows a TFT3a formed by the same design, and fig. 6A shows an example in which the first electrode 7 and the second electrode 8 are formed at regular positions in the design. On the other hand, FIGS. 6B andfig. 6C shows an example in which both electrodes are formed in a state shifted in position above or below the semiconductor film 6 in each drawing at the time of manufacturing.
As shown in FIG. 6A
Figure BDA0002973362750000141
As shown in fig. 6C, in this embodiment mode, the first electrode 7 partially covers the first side 61 and the second side 62 of the semiconductor film 6, respectively. Therefore, as in embodiment 1, the variation in the parasitic capacitance Cgd between the gate 4 and the drain electrode (first electrode 7) of the TFT3a among the plurality of TFTs 3 can be reduced, and display unevenness can be reduced. The semiconductor film 6 has a rectangular planar shape in a plan view, and particularly has a substantially square planar shape in the example of fig. 6A and the like. That is, the planar shape of the semiconductor film 6 includes a third side 63 facing the first side 61 and a fourth side 64 facing the second side 62 in a plan view in addition to the first side 61 and the second side 62. Further, the second electrode 8 partially covers the third side 63 and the fourth side 64 of the semiconductor film 6. Specifically, in FIG. 6A
Figure BDA0002973362750000142
In the example of fig. 6C, the second electrode 8 has a rectangular shape on the gate electrode 4, and of the two outer edges of the second electrode 8 that do not intersect with the third edge 63 of the semiconductor film 6, the outer edge (second outer edge 81) close to the third edge 63 is located further outside the semiconductor film 6 than the third edge 63.
The second electrode 8 has a planar shape including a second opposite side 80 facing the first electrode 7, and a second outer side 81 extending from an end portion of the second opposite side 80 located outside the semiconductor film 6 substantially in parallel with the third side 63 of the semiconductor film 6 in a plan view. The second outer side 81 is located between the outer side of the semiconductor film 6 and the outer edge 42 of the gate electrode 4 near the third side 63 of the semiconductor film 6, and is located at a position overlapping the gate electrode 4 without passing through the semiconductor film 6. In other words, the second outer side 81 of the second electrode 8 is disposed outside the semiconductor film 6 from the third side 63 of the semiconductor film 6.
As described above, a relative positional shift may occur between the first electrode 7 and the semiconductor film 6 at the time of manufacturing. The first electrode 7 and the second electrode 8 can be formed simultaneously from one metal layer formed on the semiconductor film 6 by etching or the like using a single mask, and are preferably formed efficiently by such a method. Therefore, the second electrode 8 is displaced from the semiconductor film 6, and is also displaced in conjunction with the displacement of the first electrode 7. In the conventional TFT103 shown in fig. 9, even if the drain 107 and the source 108 are shifted in position in the semiconductor film 106 in conjunction with each other, the channel Ch itself hardly changes, and a large problem hardly occurs.
However, in embodiment 1 described above, for example, when the first and second electrodes 7 and 8 in fig. 2 are displaced in the vertical direction, the length of the portion of the first opposing side 70 of the first electrode 7 located above the semiconductor film 6 changes. Therefore, the substantial channel width of the channel Ch varies. If the channel width varies, the amount of electric charge that can be stored in the storage capacitor Cs (see fig. 1) or the like varies during the on period of the TFT3, and as a result, the pixel voltage Vd (see fig. 8) varies, which leads to a reduction in display quality. In particular, in recent years, with the high definition of liquid crystal display devices, the on period of the TFT tends to be short, and therefore, variation in the channel width associated with the charging performance of the storage capacitor Cs is likely to be a problem.
In view of such a concern, in the TFT3a of embodiment 2, the second electrode 8 partially covers the third side 63 and the fourth side 64 of the semiconductor film 6, and therefore, even if the first and second electrodes 7 and 8 are formed in a state shifted upward or downward in fig. 6A and as shown in fig. 6B or 6C, a reduction in display quality hardly occurs. Specifically, the lengths W1, W2 of the portions of the first opposing edge 70 of the first electrode 7 and the second opposing edge 80 of the second electrode 8, respectively, which are located on the semiconductor film 6, vary with the positional deviation of the first and second electrodes 7, 8, respectively, as shown in fig. 6B and 6C. However, as long as the first outer side 71 of the first electrode 7 is located outside the semiconductor film 6 and the second outer side 81 of the second electrode 8 is located outside the semiconductor film 6, the sum (W1+ W2) thereof does not change. Therefore, the area of the channel Ch as viewed from above and the actual channel width do not vary, and therefore, the display quality is less likely to be degraded.
In the plan view shown in fig. 6A, it is preferable that the interval P1 between the first outer side 71 of the first electrode 7 and the first side 61 of the semiconductor film 6 and the interval P2 between the second outer side 81 of the second electrode 8 and the third side 63 of the semiconductor film 6 are substantially the same. Therefore, as described above, the first electrode 7 has the gap P2 between the first outer side 71 of the second electrode 8 and the third side 63 of the semiconductor film 6 of, for example, 1 μm to 2 μm, preferably 1.5 μm. It is estimated that the first and second electrodes 7 and 8 are displaced with substantially the same probability in both the upper and lower directions of fig. 6A. Therefore, by setting the intervals P1 and P2 to be substantially the same length as each other, the occurrence of display unevenness can be reduced.
In the examples of fig. 6A to 6C, the planar shape of the semiconductor film 6 has a rectangular shape, i.e., a point-symmetric shape. In this case, the first electrode 7 and the second electrode 8 may be symmetrical with respect to the center of the semiconductor film 6 at least inside the gate electrode 4 in a plan view. By forming the first electrode 7 and the second electrode 8 in this manner, the intervals P1 and P2 are substantially equal to each other, and thus the occurrence of display unevenness can be reduced.
The liquid crystal display device of each embodiment can be manufactured by forming them using an exposure mask having an appropriate opening in a conventional method for manufacturing a liquid crystal display device, for example, so that the gate electrode 4, the semiconductor film 6, the first electrode 7, and the second electrode 8 are formed in accordance with the gist described in each embodiment. The liquid crystal display device of each embodiment is not limited at all by the manufacturing method thereof.
[ conclusion ]
(1) A liquid crystal display device according to an embodiment of the present invention includes: a TFT substrate including a thin film transistor and a pixel electrode connected to the thin film transistor; an opposite substrate having a common electrode facing the pixel electrode with a liquid crystal layer interposed therebetween, the thin film transistor including: a semiconductor film which is laminated on the gate electrode with a gate insulating film interposed therebetween and has a planar shape including a first side and a second side which overlap with the gate electrode in a plan view; a first electrode and a second electrode which are formed on the semiconductor film and connected to the pixel electrode, respectively, the second electrode being provided to face the first electrode; the first and second sides are adjacent to each other at a predetermined angle, and the first electrode at least partially covers the first and second sides, respectively.
According to the structure, in the liquid crystal display device, the reduction of the display quality caused by the deviation of the parasitic capacitance of the TFT forming the pixel circuit can be reduced.
(2) In the liquid crystal display device according to the above (1), the first electrode may be drawn out from a region on the gate electrode to the outside along a first direction in which the first electrode and the second electrode face each other. In this case, the first electrode and the pixel electrode can be connected by a short path.
(3) In the liquid crystal display device according to the above (2), the first side extends substantially parallel to the first direction and substantially perpendicular to the second side, and the first electrode partially covers the first side and the second side, respectively. In this case, the semiconductor film and the first electrode can be laid out efficiently.
(4) In the liquid crystal display device according to the above (3), a width of the first electrode in a direction along the second side is shorter than a length of the second side. In this case, the fluctuation amount of the first electrode due to the variation can be prevented from becoming excessively large.
(5) In the liquid crystal display device of the above (3) or (4), the planar shape of the semiconductor film further includes a third side opposite to the first side and a fourth side opposite to the second side, and the second electrode partially covers the third side and the fourth side. In this case, fluctuation in the actual channel width of the channel formed in the semiconductor film can be suppressed, and deterioration in display quality is less likely to occur.
(6) In the liquid crystal display device according to the above (5), the first electrode has a planar shape including a first opposing side and a first outer side in a plan view, the first opposing side is opposed to the second electrode, the first outer side extends substantially parallel to the first side from an end portion of the first opposing side located outside the semiconductor film, the second electrode has a planar shape including a second opposing side and a second outer side in a plan view, the second opposing side is opposed to the first electrode, the second outer side extends substantially parallel to the third side from an end portion of the second opposing side located outside the semiconductor film, and a distance between the first side and the first outer side and a distance between the third side and the second outer side may be substantially the same. In this case, the occurrence of display unevenness can be further reduced.
(7) In the liquid crystal display device according to any one of (1) to (6), the planar shape of the semiconductor film may have a point-symmetrical shape, and the first electrode and the second electrode may be symmetrical with respect to a center of the semiconductor film at least inside the gate electrode in a plan view. In this case, the occurrence of display unevenness can be further reduced.
(8) In the above (1)
Figure BDA0002973362750000181
(7) In the liquid crystal display device of any one of the above items, a length of a portion of the outer edge of the semiconductor film which is not covered with the first electrode is substantially equal to a length of a portion of the outer edge of the first electrode which overlaps with the gate electrode without passing through the semiconductor film, in a region closer to the first electrode than a middle line passing through a middle between the first electrode and the second electrode in a plan view. In this case, when the first electrode and the semiconductor film are deviated in opposite directions with respect to the expansion and contraction of the respective areas, visible display unevenness is not generated.
Description of the reference numerals
1 liquid crystal display device
2 TFT substrate
3、3a TFT
4 grid electrode
5 Gate insulating film
6 semiconductor film
61 first side of semiconductor film
62 second side of the semiconductor film
63 a third side of the semiconductor film
64 fourth side of the semiconductor film
7 first electrode (drain electrode)
70 first opposite side
71 first outer side edge
8 second electrode (Source)
80 second opposite side
81 second outside edge
9 pixel electrode
10 opposite substrate
11 common electrode
Cgd parasitic capacitance
Ch channel
Cs auxiliary capacitor
L1、Lla
Figure BDA0002973362750000191
A length of a portion of an outer edge of the Llc first electrode which overlaps with the gate electrode without the semiconductor film interposed therebetween
L2、L2a
Figure BDA0002973362750000192
The length of a portion of the outer edge of the L2d semiconductor film which is not covered by the first electrode in a region closer to the first electrode than the intermediate line
LC liquid crystal layer
M middle line
P1 space between first outer side of first electrode and first side of semiconductor film
The interval between the second outer side of the P2 second electrode and the third side of the semiconductor film

Claims (8)

1. A liquid crystal display device, comprising:
a TFT substrate including a thin film transistor and a pixel electrode connected to the thin film transistor;
an opposite substrate having a common electrode facing the pixel electrode via a liquid crystal layer,
the thin film transistor includes:
a semiconductor film which is laminated on the gate electrode with a gate insulating film interposed therebetween and has a planar shape including a first side and a second side which overlap with the gate electrode in a plan view;
a first electrode and a second electrode formed on the semiconductor film, respectively, the first electrode being connected to the pixel electrode, the second electrode being provided to face the first electrode;
the first side and the second side are adjacent to each other at a predetermined angle,
the first electrode at least partially covers the first and second edges, respectively.
2. The liquid crystal display device according to claim 1,
the first electrode is drawn out from a region on the gate electrode to the outside along a first direction in which the first electrode and the second electrode face each other.
3. The liquid crystal display device according to claim 2,
the first side extending substantially parallel to the first direction and substantially orthogonal to the second side,
the first electrode partially covers the first and second edges, respectively.
4. The liquid crystal display device according to claim 3,
the width of the first electrode in the direction along the second side is shorter than the length of the second side.
5. The liquid crystal display device according to claim 3 or 4,
the planar shape of the semiconductor film further includes a third side opposite to the first side and a fourth side opposite to the second side,
the second electrode partially covers the third side and the fourth side, respectively.
6. The liquid crystal display device according to claim 5,
the first electrode has a planar shape including a first opposing side and a first outer side in a plan view, the first opposing side opposing the second electrode, the first outer side extending substantially in parallel with the first side from an end portion of the first opposing side located outside the semiconductor film,
the second electrode has a planar shape including a second opposite side facing the first electrode and a second outer side extending substantially parallel to the third side from an end portion of the second opposite side located outside the semiconductor film in a plan view,
the spacing between the first edge and the first outer side edge is substantially the same as the spacing between the third edge and the second outer side edge.
7. The liquid crystal display device according to any one of claims 1 to 6,
the planar shape of the semiconductor film has a point-symmetrical shape,
the first electrode and the second electrode are symmetrical with respect to the center of the semiconductor film at least inside the gate electrode in a plan view.
8. The liquid crystal display device according to any one of claims 1 to 7,
in a region closer to the first electrode than a middle line passing through a middle between the first electrode and the second electrode in a plan view, a length of a portion of an outer edge of the semiconductor film not covered with the first electrode is substantially equal to a length of a portion of the outer edge of the first electrode not overlapping with the gate electrode via the semiconductor film.
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