CN112688552B - Double-path PFC control circuit and method - Google Patents
Double-path PFC control circuit and method Download PDFInfo
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- CN112688552B CN112688552B CN202011518327.XA CN202011518327A CN112688552B CN 112688552 B CN112688552 B CN 112688552B CN 202011518327 A CN202011518327 A CN 202011518327A CN 112688552 B CN112688552 B CN 112688552B
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Abstract
The invention provides a double-path PFC control circuit and a method, comprising the following steps: the first PFC main loop is connected with the first rectifier bridge and the second rectifier bridge, and the second PFC main loop is connected with the first rectifier bridge and the second rectifier bridge; the PFC control loop is connected with the first PFC main loop and the second PFC main loop; the first enabling control circuit and the second enabling control circuit are respectively connected to the PFC control loop; the bus voltage control circuit is connected with the PFC control circuit, the first PFC main circuit and the second PFC main circuit; the bus circuit is connected with the first PFC main loop and the second PFC main loop; the first driving signal enhancement loop is respectively connected with the first PFC main loop and the PFC control loop, and the second driving signal enhancement loop is respectively connected with the second PFC main loop and the PFC control loop. The invention realizes the on and off of two PFC circuits through software and hardware control, adjusts the bus voltage by using the software and hardware control, and realizes the adjustment of the bus voltage according to the difference of the output load so as to optimize the efficiency of the driver.
Description
Technical Field
The invention relates to the technical field of PFC, in particular to a double-circuit PFC control circuit and a double-circuit PFC control method.
Background
In the traditional PFC control technology, the on-off of the IGBT is controlled through software, under the condition of a large load, the current passing through the IGBT is large, the IGBT with higher parameters needs to be used, and the requirement on the heat dissipation condition is higher.
In the conventional PFC control technology, the bus voltage is generally controlled at 380V, which is a constant value.
In the traditional PFC control technology, the reactor needs to be externally connected with a large reactor, and has large volume and high price.
Therefore, it is desirable to solve the problems of large on/off current, constant bus voltage, large reactor size and high cost of the IGBT.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a two-way PFC control circuit and method for solving the problems of large on/off current, constant bus voltage, large reactor volume and high price in controlling an IGBT in the prior art.
To achieve the above and other related objects, the present invention provides a two-way PFC control circuit, comprising: the circuit comprises: the rectifier comprises a first rectifier bridge and a second rectifier bridge, wherein the first rectifier bridge is used for generating a first rectification signal, and the second rectifier bridge is used for generating a second rectification signal; the first PFC main loop is connected to the first rectifier bridge and the second rectifier bridge, and the second PFC main loop is connected to the first rectifier bridge and the second rectifier bridge; the PFC control loop is connected to the first PFC main loop and the second PFC main loop; the first enabling control circuit and the second enabling control circuit are respectively connected to the PFC control loop; the bus voltage control circuit is connected with the PFC control circuit, the first PFC main circuit and the second PFC main circuit; the bus circuit is connected to the first PFC main loop and the second PFC main loop; the first driving signal enhancement loop is respectively connected with the first PFC main loop and the PFC control loop, and the second driving signal enhancement loop is respectively connected with the second PFC main loop and the PFC control loop; the first driving signal enhancement circuit is used for outputting a first driving control signal to the PFC control circuit when the input current is larger than a first threshold value, the PFC control circuit is used for outputting the first driving control signal to the first driving signal enhancement circuit, the first driving signal enhancement circuit is used for enhancing the first driving signal, the first driving signal enhancement circuit is used for outputting the enhanced first driving signal to the first PFC main circuit, and the first PFC main circuit is used for outputting a first sampling current signal to the PFC control circuit, so that the PFC control circuit controls the duty ratio of the first driving control signal based on the first sampling current signal; the second driving signal enhancement circuit is configured to output a second driving control signal to the PFC control circuit when the input current is greater than a second threshold, the PFC control circuit is configured to output the second driving control signal to the second driving signal enhancement circuit, the second driving signal enhancement circuit is configured to enhance the second driving signal, the second driving signal enhancement circuit is configured to output the enhanced second driving signal to the second PFC main circuit, and the second PFC main circuit is configured to output a second sampling current signal to the PFC control circuit, so that the PFC control circuit controls a duty ratio of the second driving control signal based on the second sampling current signal; and the bus voltage control loop and the bus circuit are used for providing bus voltage for the first PFC main loop and the second PFC main loop.
In order to achieve the above object, the present invention further provides a two-way PFC control method applied to any one of the two-way PFC control circuits, including the steps of: the first driving signal enhancement loop is respectively connected with the first PFC main loop and the PFC control loop, and the second driving signal enhancement loop is respectively connected with the second PFC main loop and the PFC control loop; the first driving signal enhancement circuit is used for outputting a first driving control signal to the PFC control circuit when the input current is larger than a first threshold value, the PFC control circuit is used for outputting the first driving control signal to the first driving signal enhancement circuit, the first driving signal enhancement circuit is used for enhancing the first driving signal, the first driving signal enhancement circuit is used for outputting the enhanced first driving signal to the first PFC main circuit, and the first PFC main circuit is used for outputting a first sampling current signal to the PFC control circuit, so that the PFC control circuit controls the duty ratio of the first driving control signal based on the first sampling current signal; the second driving signal enhancement circuit is configured to output a second driving control signal to the PFC control circuit when the input current is greater than a second threshold, the PFC control circuit is configured to output the second driving control signal to the second driving signal enhancement circuit, the second driving signal enhancement circuit is configured to enhance the second driving signal, the second driving signal enhancement circuit is configured to output the enhanced second driving signal to the second PFC main circuit, and the second PFC main circuit is configured to output a second sampling current signal to the PFC control circuit, so that the PFC control circuit controls a duty ratio of the second driving control signal based on the second sampling current signal; and the bus voltage control loop and the bus circuit are used for providing bus voltage for the first PFC main loop and the second PFC main loop.
As described above, the two-way PFC control circuit and method of the present invention have the following advantages: the on and off of two PFC paths are realized through software and hardware control, the bus voltage is adjusted through software and hardware control, and the adjustment of the bus voltage is realized according to the difference of the output load size so as to optimize the efficiency of the driver.
Drawings
Fig. 1a is a schematic structural diagram of a dual PFC control circuit according to an embodiment of the present invention;
fig. 1b is a schematic structural diagram of a first rectifier bridge of a dual-path PFC control circuit according to an embodiment of the present invention;
fig. 1c is a schematic diagram illustrating a second rectifier bridge of the dual PFC control circuit according to an embodiment of the present invention;
fig. 1d is a schematic structural diagram of a first PFC main loop and a second PFC main loop of a dual-path PFC control circuit according to an embodiment of the present invention;
fig. 1e is a schematic diagram illustrating a first enable control circuit of a dual PFC control circuit according to an embodiment of the present invention;
fig. 1f is a schematic diagram illustrating a second enable control circuit of the dual PFC control circuit according to an embodiment of the present invention;
fig. 1g is a schematic structural diagram of a bus circuit of a dual-path PFC control circuit according to an embodiment of the present invention;
fig. 1h is a schematic diagram illustrating a bus voltage control loop of a dual PFC control circuit according to an embodiment of the present invention;
fig. 1i is a schematic structural diagram of a first driving signal enhancement circuit of a dual-channel PFC control circuit according to an embodiment of the present invention;
fig. 1j is a schematic diagram illustrating a second driving signal enhancement circuit of the dual-channel PFC control circuit according to an embodiment of the present invention;
FIG. 1k is a schematic diagram of a two-way PFC control circuit according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating a two-way PFC control method according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, so that the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation can be changed freely, and the layout of the components can be more complicated.
The double-path PFC control circuit and the method realize the on and off of the two paths of PFC through hardware control, adjust the bus voltage by using software and hardware control, and realize the adjustment of the bus voltage according to the difference of the output load so as to optimize the efficiency of a driver.
As shown in fig. 1a, in an embodiment, the two-way PFC control circuit of the present invention includes:
the rectifier comprises a first rectifier bridge and a second rectifier bridge, wherein the first rectifier bridge is used for generating a first rectification signal, and the second rectifier bridge is used for generating a second rectification signal.
The first PFC main loop is connected to the first rectifier bridge and the second rectifier bridge, and the second PFC main loop is connected to the first rectifier bridge and the second rectifier bridge.
And the PFC control loop is connected with the first PFC main loop and the second PFC main loop.
And the first enabling control circuit and the second enabling control circuit are respectively connected to the PFC control loop.
And the bus voltage control loop is connected to the PFC control loop, the first PFC main loop and the second PFC main loop.
And the bus circuit is connected to the first PFC main loop and the second PFC main loop.
The first driving signal enhancement loop is respectively connected with the first PFC main loop and the PFC control loop, and the second driving signal enhancement loop is respectively connected with the second PFC main loop and the PFC control loop.
The first driving signal enhancement circuit is configured to output a first driving control signal to the PFC control circuit when an input current is greater than a first threshold, the PFC control circuit is configured to output the first driving control signal to the first driving signal enhancement circuit, the first driving signal enhancement circuit is configured to enhance the first driving signal, the first driving signal enhancement circuit is configured to output the enhanced first driving signal to the first PFC main circuit, and the first PFC main circuit is configured to output a first sampling current signal to the PFC control circuit, so that the PFC control circuit controls a duty ratio of the first driving control signal based on the first sampling current signal.
The second driving signal enhancement circuit is configured to output a second driving control signal to the PFC control circuit when the input current is greater than a second threshold, the PFC control circuit is configured to output the second driving control signal to the second driving signal enhancement circuit, the second driving signal enhancement circuit is configured to enhance the second driving signal, the second driving signal enhancement circuit is configured to output the enhanced second driving signal to the second PFC main circuit, and the second PFC main circuit is configured to output a second sampling current signal to the PFC control circuit, so that the PFC control circuit controls a duty ratio of the second driving control signal based on the second sampling current signal.
And the bus voltage control loop and the bus circuit are used for providing bus voltage for the first PFC main loop and the second PFC main loop.
Specifically, as shown in fig. 1b, the first rectifier bridge is composed of four rectifier diodes. It is noted that the numerical references in the various figures are consistent for the same point of connection.
In particular, as shown in fig. 1c, the second rectifier bridge consists of four rectifier diodes.
Specifically, as shown in fig. 1d, the first PFC main loop and the second PFC main loop include: an inductor L24, a diode D23, an IGBTQ5, a resistor R158, a resistor R162, a resistor R163, a capacitor C102, a capacitor C103 and a capacitor C104, wherein one end of the inductor L24 is connected with the anode of the diode D23; the collector of the IGBTQ5 is connected to one end of the inductor L24, the emitter of the IGBTQ5 is connected to one end of the resistor R158, the emitter of the IGBTQ5 is connected to one end of the resistor R162, and the gate of the IGBTQ5 is connected to the first driving signal boosting loop; the other end of the resistor R158 is connected with one end of the resistor R163; the other end of the resistor R162 is connected to one end of the capacitor C102, and the other end of the resistor R162 is connected to one end of the capacitor C103; the other end of the resistor R163 is connected to one end of the capacitor C104, and the other end of the resistor R163 is connected to the other end of the capacitor C103. The second rectifier bridge comprises: an inductor L25, a diode D24, an IGBTQ6, a resistor R160, a resistor R164, a resistor R165, a capacitor C106, a capacitor C107 and a capacitor C108, wherein one end of the inductor L25 is connected with the anode of the diode D24; the collector of the IGBTQ6 is connected to one end of the inductor L25, the emitter of the IGBTQ6 is connected to one end of the resistor R160, the emitter of the IGBTQ6 is connected to one end of the resistor R164, and the gate of the IGBTQ6 is connected to the first driving signal boosting loop; the other end of the resistor R160 is connected with one end of the resistor R165; the other end of the resistor R164 is connected with one end of the capacitor C106, and the other end of the resistor R164 is connected with one end of the capacitor C107; the other end of the resistor R165 is connected with one end of the capacitor C108, and the other end of the resistor R165 is connected with the other end of the capacitor C107.
Specifically, as shown in fig. 1e, the first enable control circuit includes: the resistor R203, the resistor R204, the resistor R205, the resistor R206, the MOS transistor Q7 and the capacitor C140; one end of the resistor R203 is connected with a 16V voltage output end of the PFC control loop; the drain of the MOS transistor Q7 is connected to the other end of the resistor R203, the source of the MOS transistor Q7 is grounded, and the gate of the MOS transistor Q7 is connected to one end of the resistor R206; the drain electrode of the MOS tube Q7 is connected with a channel 1 management setting pin of the PFC control loop; one end of the resistor R204 is connected with the drain electrode of the MOS transistor Q7, and the other end of the resistor R204 is grounded; one end of the resistor R205 is grounded, and the other end of the resistor R205 is connected to one end of the resistor R206; one end of the capacitor C140 is grounded, and the other end of the capacitor C140 is connected to one end of the resistor R206.
Specifically, as shown in fig. 1f, the second enable control circuit includes: the resistor R208, the resistor R207, the resistor R210, the resistor R209, the MOS transistor Q8 and the capacitor C141; one end of the resistor R208 is connected with a 16V voltage output end of the PFC control loop; the drain of the MOS transistor Q8 is connected with the other end of the resistor R208, the source of the MOS transistor Q8 is grounded, and the gate of the MOS transistor Q8 is connected with one end of the resistor R209; the drain electrode of the MOS tube Q8 is connected with a channel 2 management setting pin of the PFC control loop; one end of the resistor R207 is connected with the drain electrode of the MOS transistor Q8, and the other end of the resistor R207 is grounded; one end of the resistor R210 is grounded, and the other end of the resistor R210 is connected with one end of the resistor R209; one end of the capacitor C141 is grounded, and the other end of the capacitor C141 is connected to one end of the resistor R209.
Specifically, as shown in fig. 1g, the bus circuit includes four electrode capacitors E1, E2, E3, E4 connected in parallel; the anode of the bus circuit is connected with the cathode of the diode D23 of the first rectifier bridge; the anode of the bus circuit is connected with the cathode of the diode D24 of the second rectifier bridge; and the negative electrode of the bus circuit is grounded.
Specifically, as shown in fig. 1h, the bus voltage control loop includes: a resistor R182, a resistor R183, a resistor R184, a resistor R185, a resistor R186, a resistor R187, a resistor R188, a relay RY1, a relay RY2, a relay RY3 and a capacitor C124; the resistor R182, the resistor R183, the resistor R184, the resistor R185, the resistor R186 and the resistor R187 are sequentially connected in series, one end of the resistor R182 is connected with the negative electrode of the diode D23 of the first rectifier bridge, and one end of the resistor R182 is connected with the negative electrode of the diode D24 of the first rectifier bridge; the relay RY1 is used for controlling a first switch for short-circuiting the resistor R185 by opening and closing; the relay RY2 is used for controlling a second switch for short-circuiting the resistor R186 by opening and closing; the relay RY3 is used for controlling a third switch for short-circuiting the resistor R187 by opening and closing; one end of the resistor R188 is connected to one end of the resistor R184 and one end of the resistor R185, the other end of the resistor R188 is connected to one end of the capacitor C124, and the other end of the resistor R188 is connected to a first voltage output end PFCFB of the PFC control loop; the other end of the capacitor C124 is grounded. Specifically, the bus voltage control circuit controls the relay RY1, the relay RY2, and the relay RY3 to be turned on and off according to the magnitude of the input current. When the current is small and reaches the threshold value a, the control signal controls the relays RY1, RY2 and RY3 to be disconnected, and the bus voltage value is minimum; when the input current continues to increase and reaches a threshold value b, the relay RY1 is controlled to be closed by the control signal, the relays RY2 and RY3 are controlled to be opened by the control signal, and the bus voltage value is a second small value; when the input current continues to increase and reaches the threshold value c, the relay RY2 is controlled to be closed by the control signal, the relays RY1 and RY3 are controlled to be opened by the control signal, and the bus voltage value is a third small value; when the input current continues to increase and reaches the threshold value d, the control signal control relay RY3 is closed, and the control signal control relays RY1 and RY2 are opened, at which time the bus voltage value is at a maximum value. By controlling the opening and closing of relays RY1, RY2, and RY3, it is possible to adjust the bus voltage between 330V and 380V according to different input currents. Wherein the resistance values of R185, R186 and R187 are increased in sequence. One end of the resistor R182 is connected to the cathode of the diode D23 of the first rectifier bridge and the cathode of the diode D24 of the second rectifier bridge, and is configured to provide a bus voltage for the bus circuit and the first and second PFC main circuits.
Specifically, as shown in fig. 1i, the first driving signal enhancement loop includes: the circuit comprises a resistor R174, a resistor R176, a resistor R177, a resistor R178, a capacitor C116, a capacitor C117, a capacitor C118, a capacitor C119 and a driving chip U16; one end of the resistor R174 is connected with a first driving signal output end OPFC1 of the PFC control loop; the other end of the resistor R174 is connected with a first signal non-inverting input end IN + of the driving chip U16; one end of the capacitor C116 is connected to the other end of the resistor R174, and the other end of the capacitor C116 is grounded; a first signal inverting input end IN-of the driving chip U16 is grounded, a first power supply end VDD of the driving chip U16 is respectively connected with one ends of the capacitor C117, the capacitor C118 and the capacitor C119, a first high-level output end of the driving chip U16 is respectively connected with one ends of the resistor R176 and the resistor R177, and a first low-level output end of the driving chip U16 is connected with one end of the resistor R178; the other ends of the capacitor C117, the capacitor C118 and the capacitor C119 are all grounded; the other ends of the resistor R176, the resistor R177 and the resistor R178 are connected to the gate of the IGBTQ5 of the first rectifier bridge.
Specifically, as shown in fig. 1j, the second driving signal enhancement loop includes: a resistor R175, a resistor R179, a resistor R180, a resistor R181, a capacitor C120, a capacitor C121, a capacitor C122, a capacitor C123 and a driving chip U17; one end of the resistor R175 is connected to a second driving signal output end OPFC2 of the PFC control loop; the other end of the resistor R175 is connected with a second signal non-inverting input end IN + of the driving chip U17; one end of the capacitor C120 is connected to the other end of the resistor R175, and the other end of the capacitor C120 is grounded; a second signal inverting input terminal IN-of the driving chip U17 is grounded, a second power terminal VDD of the driving chip U17 is respectively connected with one end of the capacitor C121, one end of the capacitor C122 and one end of the capacitor C123, a second high-level output terminal of the driving chip U17 is respectively connected with one end of the resistor R179 and one end of the resistor R180, and a second low-level output terminal of the driving chip U17 is connected with one end of the resistor R181; the other ends of the capacitor C121, the capacitor C122 and the capacitor C123 are all grounded; the other ends of the resistor R179, the resistor R180 and the resistor R181 are connected with the gate of the IGBTQ6 of the second rectifier bridge.
Specifically, as shown in fig. 1k, the PFC control loop is composed of a control chip U15 and peripheral circuits. The peripheral circuit is specifically shown in the figure and is not described herein again. The dual-path PFC technology with the bus voltage controllable is realized through software and hardware control, namely the on and off of two paths of PFC are realized through hardware control. And the bus voltage is adjusted by using software and hardware control, and the adjustment of the bus voltage is realized according to the difference of the output load size so as to optimize the efficiency of the driver.
The specific scheme is as follows: an input L, N is connected with a first PFC main loop and a second PFC main loop through a first rectifier bridge and a second rectifier bridge, and then is connected with a bus circuit, and the first PFC main loop and the second PFC main loop form a circuit main loop; the control chip U15 and the peripheral circuit form a control loop, the first drive signal enhancement loop and the second drive signal enhancement loop increase the capacity of driving the IGBT current, and the bus voltage control loop controls and adjusts the voltage through software and hardware.
The rectification input part comprises a first rectification bridge and a second rectification bridge. The first main PFC loop includes a high frequency inductor L24, an IGBTQ5, a rectifying diode D23, a first PFC current detection resistor R158, and peripheral RC absorption devices. The second main PFC loop comprises a high-frequency inductor L25, an IGBTQ6, a rectifier diode D24, a second PFC current detection resistor R160, and peripheral RC absorption devices. And the PFC control loop comprises a main control chip U15, and a resistor R and a capacitor C required by peripheral parameter setting. The first enabling control circuit and the second enabling control circuit comprise patch MOS (Q7, Q8) and resistors and capacitors for controlling the configuration. The first driving signal enhancement circuit and the second driving signal enhancement circuit comprise driving chips U16 and U17, driving resistors R176-R181, power supply energy storage filter capacitors C117-C121 and the like. The bus voltage control circuit comprises voltage dividing resistors R182-R187 and control switch relays RY 1-RY 3.
The control chip U15 pin functions as follows:
the implementation mode is as follows:
under the condition that the driver does not work when the driver is normally connected with a mains supply, the first enabling control circuit and the second enabling control circuit are controlled by software, PFCEN1 and PFCEN2 are at low level, PFCEN1 'and PFCEN 2' are 5V and are larger than an enabling and closing voltage 4V, CM1 and CM2 in a PFC control loop are enabled and closed, and the chip does not work.
When the compressor is operated, software detects that the input current reaches a first threshold value A, the software controls the PFCEN1 in the first enabling control circuit to be set high, the PFCEN 1' is 0V, the level is low, the CM1 in the PFC control circuit enables operation, the pin27 outputs an OPFC1 driving control signal, the OPFC1 driving control signal is enhanced through a driving signal of the first driving signal enhancing circuit, the driving signal GATE1 is output, the driving signal GATE1 controls the on and off of the IGBT Q5 in the first PFC main circuit, the sampling current signal is sent to the control chip U15 through the current signals CS1+ and CS 1-collected in the first PFC main circuit, the sampling current signal is connected to the pin22 and the pin23 in the PFC control circuit, and the duty ratio of the driving signal OPFC1 is adjusted through the sampling current signal.
When the compressor operates, the input current continues to be increased, and when the input current reaches a second threshold value B, the software controls the PFCEN2 in the second enabling control circuit to be set high, the PFCEN 2' is 0V, the level is low, the CM2 in the PFC control circuit enables work, the pin26 in the PFC control circuit outputs an OPFC2 driving control signal, the OPFC2 driving control signal is enhanced through a driving signal of the second driving signal enhancing circuit and outputs a driving signal GATE2, the driving signal GATE2 controls the on and off of the IGBT Q6 in the second PFC main circuit, the sampling current signal is sent to the control chip U15 through current signals CS2+ and CS 2-collected in the second PFC main circuit and is connected to the pin21 and the pin20 in the PFC control circuit, and the duty ratio of the driving signal OPFC2 is adjusted through the sampling signal.
Specifically, as shown in fig. 1k, the PFC control loop is composed of a control chip U15 and a peripheral circuit, and the peripheral circuit of the control chip U15 is used to adjust the resistance and capacitance values in the peripheral circuit according to the calculation and test conditions.
Specifically, because two PFC control circuits are provided, the power devices IGBT (Q5, Q6) and diode (D23, D24) in each PFC control circuit can be smaller power devices. Under the same power consumption condition, the requirement on the heat dissipation condition is lower because of the devices sharing the power consumption. Through software control, switches 1,2 and 3 (corresponding to relay RY1, relay RY2 and relay RY 3) are controlled, the size of the voltage dividing resistor is changed, the size of the bus voltage (DC1+) is adjusted, and the efficiency of the driver is optimized. The high-frequency inductors (L24, L25) replace external reactors and are directly welded on the PCB, so that the installation volume of the system is reduced, the time for installing the external reactors is saved, and the risk of system errors caused by poor installation possibly generated by the installation of the external reactors is reduced.
As shown in fig. 2, in an embodiment, a two-way PFC control method according to the present invention is applied to any one of the two-way PFC control circuits, and includes the following steps:
step S21, a first driving signal enhancement loop and a second driving signal enhancement loop, where the first driving signal enhancement loop is connected to the first PFC main loop and the PFC control loop, respectively, and the second driving signal enhancement loop is connected to the second PFC main loop and the PFC control loop, respectively.
Step S22, the first driving signal enhancement circuit is configured to output a first driving control signal to the PFC control circuit when the input current is greater than a first threshold, the PFC control circuit is configured to output the first driving control signal to the first driving signal enhancement circuit, the first driving signal enhancement circuit is configured to enhance the first driving signal, the first driving signal enhancement circuit is configured to output the enhanced first driving signal to the first PFC main circuit, and the first PFC main circuit is configured to output a first sampling current signal to the PFC control circuit, so that the PFC control circuit controls a duty ratio of the first driving control signal based on the first sampling current signal.
Step S23, the second driving signal enhancement circuit is configured to output a second driving control signal to the PFC control circuit when the input current is greater than a second threshold, the PFC control circuit is configured to output the second driving control signal to the second driving signal enhancement circuit, the second driving signal enhancement circuit is configured to enhance the second driving signal, the second driving signal enhancement circuit is configured to output the enhanced second driving signal to the second PFC main circuit, and the second PFC main circuit is configured to output a second sampling current signal to the PFC control circuit, so that the PFC control circuit controls a duty ratio of the second driving control signal based on the second sampling current signal.
And step S24, the bus voltage control loop is used for providing bus voltage for the first PFC main loop and the second PFC main loop.
It should be noted that the above step principle corresponds to the structure in the two-way PFC control circuit one to one, and therefore, the details are not repeated herein.
In summary, the two-way PFC control circuit and method of the present invention implement the on/off of the two-way PFC through hardware control, adjust the bus voltage by using software and hardware control, and implement the adjustment of the bus voltage according to the difference of the output load size, so as to optimize the driver efficiency. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A two-way PFC control circuit, the circuit comprising:
the rectifier comprises a first rectifier bridge and a second rectifier bridge, wherein the first rectifier bridge is used for generating a first rectification signal, and the second rectifier bridge is used for generating a second rectification signal;
the first PFC main loop is connected to the first rectifier bridge and the second rectifier bridge, and the second PFC main loop is connected to the first rectifier bridge and the second rectifier bridge;
the PFC control loop is connected to the first PFC main loop and the second PFC main loop;
the first enabling control circuit and the second enabling control circuit are respectively connected to the PFC control loop;
the bus voltage control circuit is connected with the PFC control circuit, the first PFC main circuit and the second PFC main circuit;
the bus circuit is connected to the first PFC main loop and the second PFC main loop;
the first driving signal enhancement loop is respectively connected with the first PFC main loop and the PFC control loop, and the second driving signal enhancement loop is respectively connected with the second PFC main loop and the PFC control loop;
the first driving signal enhancement circuit is used for outputting a first driving control signal to the PFC control circuit when the input current is larger than a first threshold value, the PFC control circuit is used for outputting the first driving control signal to the first driving signal enhancement circuit, the first driving signal enhancement circuit is used for enhancing the first driving signal, the first driving signal enhancement circuit is used for outputting the enhanced first driving signal to the first PFC main circuit, and the first PFC main circuit is used for outputting a first sampling current signal to the PFC control circuit, so that the PFC control circuit controls the duty ratio of the first driving control signal based on the first sampling current signal;
the second driving signal enhancement circuit is configured to output a second driving control signal to the PFC control circuit when the input current is greater than a second threshold, the PFC control circuit is configured to output the second driving control signal to the second driving signal enhancement circuit, the second driving signal enhancement circuit is configured to enhance the second driving signal, the second driving signal enhancement circuit is configured to output the enhanced second driving signal to the second PFC main circuit, and the second PFC main circuit is configured to output a second sampling current signal to the PFC control circuit, so that the PFC control circuit controls a duty ratio of the second driving control signal based on the second sampling current signal;
the bus voltage control loop and the bus circuit are used for providing bus voltage for the first PFC main loop and the second PFC main loop;
inductor L24, diode D23, IGBTQ5, resistor R158, resistor R162, resistor R163, capacitor C102, capacitor C103 and capacitor C104,
one end of the inductor L24 is connected with the anode of the diode D23;
the collector of the IGBTQ5 is connected to one end of the inductor L24, the emitter of the IGBTQ5 is connected to one end of the resistor R158, the emitter of the IGBTQ5 is connected to one end of the resistor R162, and the gate of the IGBTQ5 is connected to the first driving signal boosting loop;
the other end of the resistor R158 is connected with one end of the resistor R163;
the other end of the resistor R162 is connected to one end of the capacitor C102, and the other end of the resistor R162 is connected to one end of the capacitor C103; the other end of the capacitor C102 is grounded;
the other end of the resistor R163 is connected with one end of the capacitor C104, and the other end of the resistor R163 is connected with the other end of the capacitor C103; the other end of the capacitor C104 is grounded;
first sampling current signals CS1+ and CS 1-obtained after being filtered by a resistor R162, a resistor R163, a capacitor C102, a capacitor C103 and a capacitor C104 are output to a PFC control loop;
the bus voltage control loop includes: a resistor R182, a resistor R183, a resistor R184, a resistor R185, a resistor R186, a resistor R187, a resistor R188, a relay RY1, a relay RY2, a relay RY3 and a capacitor C124;
the resistor R182, the resistor R183, the resistor R184, the resistor R185, the resistor R186 and the resistor R187 are sequentially connected in series, one end of the resistor R182 is connected with the negative electrode of the diode D23 of the first PFC main loop, and one end of the resistor R182 is connected with the negative electrode of the diode D24 of the second PFC main loop;
the relay RY1 is used for controlling a first switch for short-circuiting the resistor R185 by opening and closing;
the relay RY2 is used for controlling a second switch for short-circuiting the resistor R186 by opening and closing;
the relay RY3 is used for controlling a third switch for short-circuiting the resistor R187 by opening and closing;
one end of the resistor R188 is connected to one end of the resistor R184 and one end of the resistor R185, the other end of the resistor R188 is connected to one end of the capacitor C124, and the other end of the resistor R188 is connected to a first voltage output end PFCFB of the PFC control loop;
the other end of the capacitor C124 is grounded;
the other end of the resistor R187 is grounded.
2. The two-way PFC control circuit of claim 1, wherein: the second PFC main loop includes:
inductor L25, diode D24, IGBTQ6, resistor R160, resistor R164, resistor R165, capacitor C106, capacitor C107 and capacitor C108,
one end of the inductor L25 is connected with the anode of the diode D24;
the collector of the IGBTQ6 is connected to one end of the inductor L25, the emitter of the IGBTQ6 is connected to one end of the resistor R160, the emitter of the IGBTQ6 is connected to one end of the resistor R164, and the gate of the IGBTQ6 is connected to the first driving signal boosting loop;
the other end of the resistor R160 is connected with one end of the resistor R165;
the other end of the resistor R164 is connected with one end of the capacitor C106, and the other end of the resistor R164 is connected with one end of the capacitor C107; the other end of the capacitor C106 is grounded;
the other end of the resistor R165 is connected with one end of the capacitor C108, and the other end of the resistor R165 is connected with the other end of the capacitor C107; the other end of the capacitor C108 is grounded;
and second sampling current signals CS2+ and CS 2-obtained after being filtered by the resistor R164, the resistor R165, the capacitor C106, the capacitor C107 and the capacitor C108 are output to the PFC control loop.
3. The two-way PFC control circuit of claim 1, wherein: the first enable control circuit includes:
the resistor R203, the resistor R204, the resistor R205, the resistor R206, the MOS transistor Q7 and the capacitor C140;
one end of the resistor R203 is connected with a 16V voltage output end of the PFC control loop;
the drain of the MOS transistor Q7 is connected to the other end of the resistor R203, the source of the MOS transistor Q7 is grounded, and the gate of the MOS transistor Q7 is connected to one end of the resistor R206; the drain electrode of the MOS tube Q7 is connected with a channel 1 management setting pin of the PFC control loop;
one end of the resistor R204 is connected with the drain electrode of the MOS transistor Q7, and the other end of the resistor R204 is grounded;
one end of the resistor R205 is grounded, and the other end of the resistor R205 is connected to one end of the resistor R206;
one end of the capacitor C140 is grounded, and the other end of the capacitor C140 is connected to one end of the resistor R206;
the other end of the resistor R206 is used for inputting a control signal output by the digital signal processor for control.
4. The two-way PFC control circuit of claim 1, wherein: the second enable control circuit includes:
the resistor R208, the resistor R207, the resistor R210, the resistor R209, the MOS transistor Q8 and the capacitor C141;
one end of the resistor R208 is connected with a 16V voltage output end of the PFC control loop;
the drain of the MOS transistor Q8 is connected with the other end of the resistor R208, the source of the MOS transistor Q8 is grounded, and the gate of the MOS transistor Q8 is connected with one end of the resistor R209; the drain electrode of the MOS tube Q8 is connected with a channel 2 management setting pin of the PFC control loop;
one end of the resistor R207 is connected with the drain electrode of the MOS transistor Q8, and the other end of the resistor R207 is grounded;
one end of the resistor R210 is grounded, and the other end of the resistor R210 is connected with one end of the resistor R209; one end of the capacitor C141 is grounded, and the other end of the capacitor C141 is connected with one end of the resistor R209;
the other end of the resistor R209 is used for inputting a control signal output by the digital signal processor for control.
5. The two-way PFC control circuit of claim 1, wherein: the bus circuit comprises four electrode capacitors E1, an electrode capacitor E2, an electrode capacitor E3 and an electrode capacitor E4 which are connected in parallel;
the anode of the bus circuit is connected with the cathode of a diode D23 of the first PFC main loop;
the anode of the bus circuit is connected with the cathode of a diode D24 of the second PFC main loop;
and the negative electrode of the bus circuit is grounded.
6. The two-way PFC control circuit of claim 2, wherein: the first drive signal boost circuit includes:
the circuit comprises a resistor R174, a resistor R176, a resistor R177, a resistor R178, a capacitor C116, a capacitor C117, a capacitor C118, a capacitor C119 and a driving chip U16;
one end of the resistor R174 is connected with a first driving signal output end OPFC1 of the PFC control loop; the other end of the resistor R174 is connected with a first signal non-inverting input end IN + of the driving chip U16;
one end of the capacitor C116 is connected to the other end of the resistor R174, and the other end of the capacitor C116 is grounded;
a first signal inverting input end IN-of the driving chip U16 is grounded, a first power supply end VDD of the driving chip U16 is respectively connected with one ends of the capacitor C117, the capacitor C118 and the capacitor C119, a first high-level output end of the driving chip U16 is respectively connected with one ends of the resistor R176 and the resistor R177, and a first low-level output end of the driving chip U16 is connected with one end of the resistor R178;
the other ends of the capacitor C117, the capacitor C118 and the capacitor C119 are all grounded;
the other ends of the resistor R176, the resistor R177 and the resistor R178 are connected to the gate of the IGBTQ5 of the first rectifier bridge.
7. The two-way PFC control circuit of claim 1, wherein: the second drive signal boost circuit includes:
a resistor R175, a resistor R179, a resistor R180, a resistor R181, a capacitor C120, a capacitor C121, a capacitor C122, a capacitor C123 and a driving chip U17;
one end of the resistor R175 is connected to a second driving signal output end OPFC2 of the PFC control loop; the other end of the resistor R175 is connected with a second signal non-inverting input end IN + of the driving chip U17;
one end of the capacitor C120 is connected to the other end of the resistor R175, and the other end of the capacitor C120 is grounded;
a second signal inverting input terminal IN-of the driving chip U17 is grounded, a second power terminal VDD of the driving chip U17 is respectively connected with one end of the capacitor C121, one end of the capacitor C122 and one end of the capacitor C123, a second high-level output terminal of the driving chip U17 is respectively connected with one end of the resistor R179 and one end of the resistor R180, and a second low-level output terminal of the driving chip U17 is connected with one end of the resistor R181;
the other ends of the capacitor C121, the capacitor C122 and the capacitor C123 are all grounded;
the other ends of the resistor R179, the resistor R180 and the resistor R181 are connected with the gate of the IGBTQ6 of the second rectifier bridge.
8. A two-way PFC control method applied to the two-way PFC control circuit of any one of claims 1 to 7, comprising the steps of:
the first driving signal enhancement loop is respectively connected with the first PFC main loop and the PFC control loop, and the second driving signal enhancement loop is respectively connected with the second PFC main loop and the PFC control loop;
the first driving signal enhancement circuit is used for outputting a first driving control signal to the PFC control circuit when the input current is larger than a first threshold value, the PFC control circuit is used for outputting the first driving control signal to the first driving signal enhancement circuit, the first driving signal enhancement circuit is used for enhancing the first driving signal, the first driving signal enhancement circuit is used for outputting the enhanced first driving signal to the first PFC main circuit, and the first PFC main circuit is used for outputting a first sampling current signal to the PFC control circuit, so that the PFC control circuit controls the duty ratio of the first driving control signal based on the first sampling current signal;
the second driving signal enhancement circuit is configured to output a second driving control signal to the PFC control circuit when the input current is greater than a second threshold, the PFC control circuit is configured to output the second driving control signal to the second driving signal enhancement circuit, the second driving signal enhancement circuit is configured to enhance the second driving signal, the second driving signal enhancement circuit is configured to output the enhanced second driving signal to the second PFC main circuit, and the second PFC main circuit is configured to output a second sampling current signal to the PFC control circuit, so that the PFC control circuit controls a duty ratio of the second driving control signal based on the second sampling current signal;
the bus voltage control loop and the bus circuit are used for providing bus voltage for the first PFC main loop and the second PFC main loop;
inductor L24, diode D23, IGBTQ5, resistor R158, resistor R162, resistor R163, capacitor C102, capacitor C103 and capacitor C104,
one end of the inductor L24 is connected with the anode of the diode D23;
the collector of the IGBTQ5 is connected to one end of the inductor L24, the emitter of the IGBTQ5 is connected to one end of the resistor R158, the emitter of the IGBTQ5 is connected to one end of the resistor R162, and the gate of the IGBTQ5 is connected to the first driving signal boosting loop;
the other end of the resistor R158 is connected with one end of the resistor R163;
the other end of the resistor R162 is connected to one end of the capacitor C102, and the other end of the resistor R162 is connected to one end of the capacitor C103; the other end of the capacitor C102 is grounded;
the other end of the resistor R163 is connected with one end of the capacitor C104, and the other end of the resistor R163 is connected with the other end of the capacitor C103; the other end of the capacitor C104 is grounded;
first sampling current signals CS1+ and CS 1-obtained after being filtered by a resistor R162, a resistor R163, a capacitor C102, a capacitor C103 and a capacitor C104 are output to a PFC control loop;
the bus voltage control loop includes: a resistor R182, a resistor R183, a resistor R184, a resistor R185, a resistor R186, a resistor R187, a resistor R188, a relay RY1, a relay RY2, a relay RY3 and a capacitor C124;
the resistor R182, the resistor R183, the resistor R184, the resistor R185, the resistor R186 and the resistor R187 are sequentially connected in series, one end of the resistor R182 is connected with the negative electrode of the diode D23 of the first PFC main loop, and one end of the resistor R182 is connected with the negative electrode of the diode D24 of the second PFC main loop;
the relay RY1 is used for controlling a first switch for short-circuiting the resistor R185 by opening and closing;
the relay RY2 is used for controlling a second switch for short-circuiting the resistor R186 by opening and closing;
the relay RY3 is used for controlling a third switch for short-circuiting the resistor R187 by opening and closing;
one end of the resistor R188 is connected to one end of the resistor R184 and one end of the resistor R185, the other end of the resistor R188 is connected to one end of the capacitor C124, and the other end of the resistor R188 is connected to a first voltage output end PFCFB of the PFC control loop;
the other end of the capacitor C124 is grounded;
the other end of the resistor R187 is grounded.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103872895A (en) * | 2012-12-13 | 2014-06-18 | 电力系统技术有限公司 | Controller for a Power Converter and Method of Operating the Same |
| CN109004656A (en) * | 2018-07-31 | 2018-12-14 | 奥克斯空调股份有限公司 | A kind of control method, device and the air conditioner of interleaved PFC circuit |
| CN209267442U (en) * | 2019-01-30 | 2019-08-16 | 广东美的制冷设备有限公司 | Pfc circuit, electrically-controlled component and air conditioner |
| CN110311358A (en) * | 2019-07-26 | 2019-10-08 | 广东美的制冷设备有限公司 | Compressor control device and air conditioner |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103973095B (en) * | 2013-02-01 | 2016-07-06 | 英飞特电子（杭州）股份有限公司 | A kind of control circuit in circuit of power factor correction |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103872895A (en) * | 2012-12-13 | 2014-06-18 | 电力系统技术有限公司 | Controller for a Power Converter and Method of Operating the Same |
| CN109004656A (en) * | 2018-07-31 | 2018-12-14 | 奥克斯空调股份有限公司 | A kind of control method, device and the air conditioner of interleaved PFC circuit |
| CN209267442U (en) * | 2019-01-30 | 2019-08-16 | 广东美的制冷设备有限公司 | Pfc circuit, electrically-controlled component and air conditioner |
| CN110311358A (en) * | 2019-07-26 | 2019-10-08 | 广东美的制冷设备有限公司 | Compressor control device and air conditioner |
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