CN217427993U

CN217427993U - Control circuit for reducing power supply no-load power consumption

Info

Publication number: CN217427993U
Application number: CN202220724549.5U
Authority: CN
Inventors: 不公告发明人
Original assignee: Mornsun Guangzhou Science and Technology Ltd
Current assignee: Mornsun Guangzhou Science and Technology Ltd
Priority date: 2022-03-30
Filing date: 2022-03-30
Publication date: 2022-09-13
Anticipated expiration: 2032-03-30

Abstract

The utility model relates to a reduce control circuit of no-load power consumption of power, control circuit include sampling circuit, difference amplifier circuit, hysteresis comparison circuit and controlled circuit, sampling circuit sampling output current to with sampling signal input to difference amplifier circuit, input to an input of hysteresis comparison circuit after the difference amplifier circuit enlargies, another input reference signal of hysteresis comparison circuit, hysteresis comparison circuit compares difference amplified signal and reference signal, and with comparison result signal input to controlled circuit action. The utility model discloses can carry out real-time supervision to the output current by sampling device, when being less than the setting value by sampling device's output current, control circuit begins the action, reduces by sampling device's no-load consumption.

Description

Control circuit for reducing power supply no-load power consumption

Technical Field

The utility model relates to a crisscross BUCK topology control IC field, in particular to reduce control circuit of power no-load consumption.

Background

With the development of modern electronic devices towards low power consumption and greenization, people have higher requirements on the volume of a power supply necessary for industrial equipment, and the research on the power supply with high efficiency, high power density and low no-load power consumption is more and more urgent. Meanwhile, the staggered BUCK topology is increasingly applied to the field of high-efficiency and high-power-density power modules.

Due to the requirements on high efficiency and high power density, the conventional staggered BUCK control IC integrates the drive signal control functions of two or more BUCK switching tubes and synchronous rectifying tubes, and the master control IC can control two or more BUCK switching tube drive signals and synchronous rectifying tube drive signals of a staggered BUCK topology. LM25119 is an interleaved BUCK control IC, which is used for the design of interleaved BUCK power supplies; the LM25119 integrates BUCK1 and BUCK2 switching tube driving control logic and synchronous rectifier tube driving control logic. In the application process of LM25119, BUCK1 and BUCK2 work simultaneously, BUCK1 and BUCK2 work in a synchronous rectification mode simultaneously, and the switching frequency is fixed and unchanged, so that the problem of overlarge no-load power consumption of a power supply designed by using an interleaved BUCK topology of LM25119 occurs under the condition of no-load output, and the standby time of the whole system is further influenced.

As shown in fig. 1, in practical applications, a control circuit of the conventional LM25119 is shown in the figure, where an EN2 terminal is connected to VCC through a resistor R9, and signal outputs of a switch tube driving signal output terminal HO2 and a synchronous rectifier tube driving signal output terminal LO2 terminal of the BUCK2 are turned on; connecting the DEMB end to VCC through a resistor R10, and starting signal output of a drive signal output end LO1 end of a BUCK1 synchronous rectifier tube and a drive signal output end LO2 end of a BUCK2 synchronous rectifier tube; the RT terminal is connected to the ground through a resistor R11 with a fixed resistance, so that the power supply works at a fixed switching frequency. Under the control circuit, the BUCK1 and the BUCK2 can be ensured to work simultaneously and a synchronous rectification mode is used, so that the power density and the efficiency of the power supply can be improved.

The disadvantages of this control circuit are:

1. under the no-load condition, the control circuit has the advantages that the BUCK1 switching tube, the BUCK1 synchronous rectifying tube, the BUCK2 switching tube and the BUCK2 synchronous rectifying tube work simultaneously, so that the driving loss and the switching loss of a power supply are greatly increased, and the no-load power consumption of the power supply is increased;

2. under the no-load condition, both BUCK1 and BUCK2 work at the fixed switching frequency correspondingly set by the resistor R11, and the no-load power consumption of the power supply is increased.

3. The no-load power consumption of the control circuit is too large, and the control circuit is not suitable for a power supply requiring low no-load power consumption.

SUMMERY OF THE UTILITY MODEL

To the problem that current control circuit exists, the utility model provides a reduce control circuit of power no-load power consumption when using the crisscross BUCK topology power of LM25119 design, effectively reduces power no-load power consumption, improves entire system's stand-by time.

In order to achieve the above purpose, the technical solution of the present invention is as follows:

a control circuit for reducing power no-load power consumption is applied to a power circuit adopting an interleaved BUCK to control an IC, wherein the interleaved BUCK comprises BUCK1 and BUCK2 which are connected in parallel, the control circuit comprises a sampling circuit, a differential amplifying circuit, a hysteresis comparison circuit and a controlled circuit, the sampling circuit samples the output current of an output circuit and inputs a sampling signal to the differential amplifying circuit, the sampling signal is amplified by the differential amplifying circuit and then input to one input end of the hysteresis comparison circuit, the other input end of the hysteresis comparison circuit inputs a reference signal, the hysteresis comparison circuit compares the differential amplifying signal with the reference signal and inputs a comparison result signal to the controlled circuit for action;

when the differential amplification signal is greater than the reference signal, the controlled circuit controls BUCK1 and BUCK2 to work simultaneously, and BUCK1 and BUCK2 use a synchronous rectification mode simultaneously, so that the working frequency of the power supply is increased to ensure the loading efficiency of the power supply;

when the differential amplification signal is smaller than the reference signal, the controlled circuit controls BUCK1 to work alone, BUCK1 forbids the use of the synchronous rectification mode, and the working frequency of the power supply is reduced so as to reduce the no-load power consumption of the power supply.

Preferably, the sampling circuit comprises a resistor R1, the resistor R1 is connected in series in the output loop, the voltages at two ends of the resistor R1 are V1 and V2 respectively, and V2 is larger than V1.

Preferably, one end of the resistor R2 is used as a negative input end of the differential amplifier circuit and connected to the V1 end of the sampling circuit, the other end of the resistor R2 is connected to the V1-end of the operational amplifier IC1, one end of the resistor R3 is connected to the V1-end of the operational amplifier IC1, the other end of the resistor R3 is connected to the output end of the operational amplifier IC1 and used as an output end V3 of the differential amplifier circuit, one end of the resistor R4 is used as a positive input end of the differential amplifier circuit and connected to the V2 end of the sampling circuit, the other end of the resistor R4 is connected to the V1+ end of the operational amplifier IC1, one end of the resistor R5 is connected to the V1+ end of the operational amplifier IC1, and the other end of the resistor R5 is grounded.

Preferably, the hysteretic comparator circuit includes a resistor R6, a resistor R7, a resistor R8, a diode D1 and an operational amplifier IC2, one end of the resistor R6 is used as a forward input end of the hysteretic comparator and is connected to the output end V3 of the differential amplifier circuit, the other end of the resistor R6 is connected to the V2+ end of the operational amplifier IC2, one end of the resistor R7 is connected to the V2+ end of the operational amplifier IC2, the other end of the resistor R7 is grounded, one end of the resistor R8 is connected to the V2+ end of the operational amplifier IC2, the other end of the resistor R8 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the output end of the operational amplifier IC2 and is used as the output end V4 of the hysteretic comparator circuit, and the V2-end of the operational amplifier IC2 is connected to the reference signal VREF.

Preferably, the controlled circuit includes a resistor R9, a resistor R10, a resistor R11, a resistor R12, a switch Q1 and a control IC3, one end of the resistor R9 is connected to the hysteresis comparison circuit output terminal V4, the other end of the resistor R9 is connected to the enable terminal EN2 of the control IC3, one end of the resistor R10 is connected to the hysteresis comparison circuit output terminal V4, the other end of the resistor R10 is connected to the control IC3 synchronous rectification control terminal DEMB, one end of the resistor R11 is connected to the frequency control terminal RT of the control IC3, the other end of the resistor R11 is grounded, one end of the resistor R12 is connected to the frequency control terminal RT of the control IC3, the other end of the resistor R12 is connected to the drain of the switch Q1, the gate of the switch Q1 is connected to the hysteresis comparison circuit output terminal V4, and the source of the switch Q1 is grounded.

Preferably, the resistance of the differential amplifier circuit resistor R2 is equal to the resistance of the resistor R4, and the resistance of the resistor R3 is equal to the resistance of the resistor R5, so as to satisfy the requirement that the differential amplifier circuit output terminal V3 is (V2-V1) × R3/R2.

Compared with the prior control circuit, the utility model discloses there is following effect of showing:

1. the utility model discloses a under no-load condition, forbid BUCK2 work, forbid BUCK1, the synchronous rectification mode of BUCK2, reduced the drive loss and the switching loss of power by a wide margin, reduced the no-load power consumption of power;

2. the utility model discloses a under no-load condition, reduce BUCK1, BUCK2 switching frequency, further reduced the no-load consumption of power.

Drawings

FIG. 1 is a schematic diagram of a conventional LM25119 control circuit;

FIG. 2 is a schematic diagram of a circuit according to an embodiment of the present invention;

FIG. 3 is a timing logic diagram of the output signal V41 of the hysteresis comparator, the HO1 terminal of the BUCK1 switch driving signal output terminal, the LO1 terminal of the BUCK1 synchronous rectifier driving signal output terminal, and the HO2 terminal of the BUCK2 switch driving signal output terminal;

fig. 4 is a timing logic diagram of the output signal V42 of the hysteresis comparison circuit, the terminal HO1 of the BUCK1 switching tube driving signal output terminal, the terminal LO1 of the BUCK1 synchronous rectifier tube driving signal output terminal, and the terminal HO2 of the BUCK2 switching tube driving signal output terminal.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Fig. 2 is the schematic diagram of the embodiment of the utility model, the utility model discloses the control circuit that reduces the no-load power consumption of power includes sampling circuit 10, differential amplifier circuit 20, hysteresis comparison circuit 30 and controlled circuit 40, and this embodiment is applied to on the crisscross BUCK power supply circuit who uses control IC LM25119 design.

The sampling circuit 10 comprises a resistor R1, one end of a resistor R1 is connected with the positive input end of the differential amplification circuit, the other end of a resistor R1 is connected with the negative input end of the differential amplification circuit, the voltages at two ends of the resistor R1 are V1 and V2 respectively, a resistor R1 is connected in series with an output loop of the sampled device, the output current Io of the sampled device flows from the V2 end of the resistor R1 to the V1 end, and V2 is larger than V1.

The differential amplifying circuit 20 comprises a resistor R2, a resistor R3, a resistor R4, a resistor R5 and an operational amplifier IC1, wherein one end of the resistor R2 is used as a negative input end of the differential amplifying circuit and connected with a V1 end of a resistor R1, the other end of the resistor R2 is connected with a V1-end of an operational amplifier IC1, one end of the resistor R3 is connected with a V1-end of the operational amplifier IC1, the other end of the resistor R3 is connected with an output end of the operational amplifier IC1 and used as an output end V3 of the differential amplifying circuit, one end of the resistor R4 is used as a positive input end of the differential amplifying circuit and connected with a V2 end of a resistor R1, the other end of R4 is connected with a V1+ end of the operational amplifier IC1, one end of the resistor R5 is connected with a V1+ end of the operational amplifier IC1, the other end of the resistor R5 is connected with the ground of a sampled device, and the output end V3 of the differential amplifying circuit is connected with a positive input end of a comparator.

The hysteresis comparator circuit 30 includes a resistor R6, a resistor R7, a resistor R8, a diode D1 and an operational amplifier IC2, wherein one end of the resistor R6 is used as a positive input end of the hysteresis comparator and is connected to the output end V3 of the differential amplifier circuit, the other end of the resistor R6 is connected to the V2+ end of the operational amplifier IC2, one end of the resistor R7 is connected to the V2+ end of the operational amplifier IC2, the other end of the resistor R7 is connected to the ground of the device to be sampled, one end of the resistor R8 is connected to the V2+ end of the operational amplifier IC2, the V2-end of the operational amplifier IC2 is connected to the reference signal VREF output by the sampling device, the other end of the resistor R8 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the output end of the operational amplifier IC2 and is used as the output end V4 of the hysteresis comparator circuit, and the output end V4 of the controlled circuit.

The controlled circuit 40 comprises a resistor R9, a resistor R10, a resistor R11, a resistor R12, a switch Q1 and a control IC3LM25119, one end of the resistor R9 is connected to the output end V4 of the hysteretic comparison circuit, the other end of the resistor R9 is connected to the end EN2 of the control IC3LM25119, one end of the resistor R10 is connected to the output end V4 of the hysteretic comparison circuit, the other end of the resistor R10 is connected to the end DEMB of the control IC3LM25119, one end of the resistor R11 is connected to the end RT of the control IC3LM25119, the other end of the resistor R11 is connected to the ground of the sampled device, one end of the resistor R12 is connected to the end RT of the control IC3LM25119, the other end of the resistor R12 is connected to the drain of the switch Q1, the gate of the switch Q1 is connected to the output end V4 of the hysteretic comparison circuit, and the source of the switch Q1 is connected to the ground of the sampled device.

The control IC3LM25119 includes 7 terminals: the drive signal output end HO1 end of the BUCK1 switch tube, the drive signal output end LO1 end of the BUCK1 synchronous rectifier tube, the drive signal output end HO2 end of the BUCK2 switch tube, the drive signal output end LO2 end of the BUCK2 synchronous rectifier tube, the drive signal output end HO2 end of the BUCK2 switch tube and the drive signal output end LO2 end control end EN2 end of the BUCK2 synchronous rectifier tube, the drive signal output end LO1 end of the BUCK1 synchronous rectifier tube and the drive signal output end LO2 end DEMB end of the BUCK2 synchronous rectifier tube, and the switch frequency control end RT ends of the BUCK1 and the BUCK2 switch frequency control end.

The driving signal output end HO1 end of the BUCK1 switching tube is connected with the grid electrode of the BUCK1 switching tube and drives the BUCK1 switching tube to be switched on and off; the LO1 end of the drive signal output end of the BUCK1 synchronous rectifier tube is connected with the grid electrode of the BUCK1 synchronous rectifier tube, and drives the BUCK1 synchronous rectifier tube to be switched on and switched off; the driving signal output end HO2 end of the BUCK2 switching tube is connected with the grid electrode of the BUCK2 switching tube to drive the BUCK2 switching tube to be switched on and off; the drive signal output end LO2 end of the BUCK2 synchronous rectifier tube is connected with the grid electrode of the BUCK2 synchronous rectifier tube, and drives the BUCK2 synchronous rectifier tube to be switched on and switched off.

The terminal HO2 of the BUCK2 switching tube driving signal output terminal and the terminal EN2 of the LO2 terminal of the BUCK2 synchronous rectifier driving signal output terminal have a threshold value judging function, and when the terminal voltage of the HO2 terminal of the BUCK2 switching tube driving signal output terminal and the terminal EN2 terminal of the LO2 terminal of the BUCK2 synchronous rectifier driving signal output terminal is less than 2V, the signal output of the HO2 terminal of the BUCK2 switching tube driving signal output terminal and the terminal LO2 terminal of the BUCK2 synchronous rectifier driving signal output terminal is cut off; when the terminal voltage of the HO2 end of the BUCK2 switching tube driving signal output end and the terminal voltage of the EN2 end of the LO2 end of the BUCK2 synchronous rectifier tube driving signal output end are larger than 2V, the HO2 end of the BUCK2 switching tube driving signal output end and the signal output of the LO2 end of the BUCK2 synchronous rectifier tube driving signal output end are started.

The end of a drive signal output end LO1 of a BUCK1 synchronous rectifier tube and the end of a control end DEMB of the end of a drive signal output end LO2 of a BUCK2 synchronous rectifier tube have a threshold value judgment function, and when the end voltage of the DEMB of the end of the drive signal output end LO1 of the BUCK1 synchronous rectifier tube and the end of the control end DEMB of the end of the drive signal output end LO2 of the BUCK2 synchronous rectifier tube is less than 2.6V, the signal output of the end of the drive signal output end LO1 of the BUCK1 synchronous rectifier tube and the end of the drive signal output end LO2 of the BUCK2 synchronous rectifier tube is cut off; when the voltage of the DEMB terminal at the end of the drive signal output end LO1 of the BUCK1 synchronous rectifier tube and the control end DEMB terminal at the end of the drive signal output end LO2 of the BUCK2 synchronous rectifier tube is more than 2.6V, the signal output at the end of the drive signal output end LO1 of the BUCK1 synchronous rectifier tube and the signal output at the end of the drive signal output end LO2 of the BUCK2 synchronous rectifier tube are started.

The larger the resistance of the RT end of the switching frequency control end of BUCK1 and BUCK2 to the ground of the sampled device is, the lower the switching frequency of BUCK1 and BUCK2 is.

The specific working process of the control circuit is as follows:

the voltage (V2-V1) at two ends of the resistor R1 is amplified by a differential amplification circuit and outputs a voltage V3, the voltage V3 is used as a control signal of the positive input end of the hysteresis comparator, the voltage V3 is divided by resistors R6 and R7 to obtain a voltage V2+, the voltage V2+ is compared with the voltage V2-of the reference signal VREF, and the hysteresis comparator outputs a voltage V4 according to the comparison result of the voltage V2+ and the voltage V2-.

When the power supply is loaded, the hysteresis comparator V2+ is greater than V2-, and the output voltage V41 is 10V. V41-10V makes EN2 terminal voltage of the controlled circuit > 2V; the DEMB terminal voltage of the controlled circuit is more than 2.6V; the switch tube Q1 of the controlled circuit is conducted, the RT end of the controlled circuit is connected with the ground in parallel through the resistor R12 and the switch tube Q1 and the resistor R11, and the RT end of the controlled circuit is small in resistance to the ground. Namely, when the power supply is loaded, BUCK1 and BUCK2 work simultaneously, and BUCK1 and BUCK2 use synchronous rectification mode simultaneously, and the working frequency is high, so that the loading efficiency of the power supply is ensured. FIG. 3 is a timing logic diagram of the output signal V41 of the hysteresis comparator, the output terminal HO1 of the BUCK1 switching tube driving signal, the output terminal LO1 of the BUCK1 synchronous rectifier, and the output terminal HO2 of the BUCK2 switching tube driving signal.

When the power supply is unloaded, the hysteresis comparator V2+ < V2-, and the output voltage V42 is equal to 0V. V42-0V makes EN2 terminal voltage of the controlled circuit < 2V; enabling the DEMB terminal voltage of the controlled circuit to be less than 2.6V; the switch tube Q1 of the controlled circuit is turned off, the RT end of the controlled circuit is connected to the ground only through the resistor R11, and the resistance value of the RT end of the controlled circuit to the ground is increased. That is, when the power supply is unloaded, BUCK2 is prohibited to work, only BUCK1 works alone, BUCK1 prohibits the synchronous rectification mode, the working frequency becomes low, and the unloaded power consumption efficiency of the power supply is greatly reduced. FIG. 4 is a timing logic diagram of the output signal V42 of the hysteresis comparator, the output terminal HO1 of the BUCK1 switching tube driving signal, the output terminal LO1 of the BUCK1 synchronous rectifier, and the output terminal HO2 of the BUCK2 switching tube driving signal.

Meanwhile, considering the lowest working frequency of the control ICLM25119, the working frequency of the power supply in no-load can be reduced by further increasing the resistance value of the resistor R11, and the no-load power consumption of the power supply is further reduced.

It should be noted that, since the output terminal V4 of the hysteresis comparator circuit in this embodiment is electrically connected to the EN2 terminal, the DEMB terminal, and the RT terminal of the IC3LM25119 at the same time, when the power supply is no-load, the EN2 terminal prohibits the operation of the BUCK2, and only the BUCK1 operates; the DEMB end forbids a synchronous rectification mode; the RT end reduces the working frequency; the no-load power consumption of the power supply is reduced in three modes to different degrees, so that the optimal effect of reducing the no-load power consumption of the power supply is achieved. However, if the output end V4 of the hysteresis comparison circuit is only electrically connected with any end and any two ends of the EN2 end, the DEMB end or the RT end, when the power supply is in no load, only the BUCK1 works, or the synchronous rectification mode is forbidden, or the working frequency is reduced, and the effect of reducing the no-load power consumption of the power supply can be achieved.

The above are only preferred embodiments of the present invention, and those skilled in the art can also change and modify the above embodiments. Therefore, the present invention is not limited to the specific control modes disclosed and described above, and some modifications and changes to the present invention should fall within the protection scope of the claims of the present invention. In addition, although specific terms are used in the description of the present invention, these terms are used for convenience of description and do not limit the present invention in any way.

Claims

1. A control circuit for reducing power supply no-load power consumption is applied to a power supply circuit adopting an interlaced BUCK to control an IC, wherein the interlaced BUCK comprises BUCK1 and BUCK2 which are connected in parallel, and the control circuit is characterized in that: the control circuit comprises a sampling circuit (10), a differential amplification circuit (20), a hysteresis comparison circuit (30) and a controlled circuit (40), wherein the sampling circuit (10) samples the output current of the output circuit, inputs a sampling signal to the differential amplification circuit (20), inputs the sampling signal to one input end of the hysteresis comparison circuit (30) after being amplified by the differential amplification circuit (20), inputs a reference signal to the other input end of the hysteresis comparison circuit (30), and the hysteresis comparison circuit (30) compares the differential amplification signal with the reference signal and inputs a comparison result signal to the controlled circuit (40);

when the differential amplification signal is larger than the reference signal, the controlled circuit (40) controls BUCK1 and BUCK2 to work simultaneously, and BUCK1 and BUCK2 use a synchronous rectification mode simultaneously, so that the working frequency of the power supply is increased to ensure the loading efficiency of the power supply;

when the differential amplification signal is smaller than the reference signal, the controlled circuit (40) controls BUCK1 to operate alone, and BUCK1 prohibits the use of the synchronous rectification mode, and the operating frequency of the power supply is reduced to reduce the no-load power consumption of the power supply.

2. The control circuit for reducing no-load power consumption of a power supply according to claim 1, wherein: the sampling circuit (10) comprises a resistor R1, a resistor R1 is connected in series in an output loop, the voltages of two ends of the resistor R1 are V1 and V2 respectively, and V2 is larger than V1.

3. The control circuit for reducing no-load power consumption of a power supply according to claim 2, wherein: one end of a resistor R2 serving as a negative input end of the differential amplification circuit is connected with a V1 end of the sampling circuit (10), the other end of the resistor R2 is connected with a V1-end of the operational amplifier IC1, one end of a resistor R3 is connected with a V1-end of the operational amplifier IC1, the other end of a resistor R3 is connected with an output end of the operational amplifier IC1 serving as a V3 output end of the differential amplification circuit, one end of a resistor R4 serving as a positive input end of the differential amplification circuit is connected with a V2 end of the sampling circuit (10), the other end of a resistor R8269556 is connected with a V1+ end of the operational amplifier IC1, one end of a resistor R5 is connected with a V1+ end of the operational amplifier IC1, and the other end of a resistor R5 is grounded.

4. The control circuit of claim 3, wherein: the hysteresis comparison circuit (30) comprises a resistor R6, a resistor R7, a resistor R8, a diode D1 and an operational amplifier IC2, wherein one end of the resistor R6 is used as a positive input end of the hysteresis comparator to be connected with a differential amplification circuit output end V3, the other end of the resistor R6 is connected with a V2+ end of the operational amplifier IC2, one end of the resistor R7 is connected with a V2+ end of the operational amplifier IC2, the other end of the resistor R7 is grounded, one end of the resistor R8 is connected with a V2+ end of the operational amplifier IC2, the other end of the resistor R8 is connected with an anode of the diode D1, a cathode of a diode D1 is connected with an output end of the operational amplifier IC2 to be used as a hysteresis comparison circuit output end V4, and a V2-end of the operational amplifier IC2 is connected with a reference signal VREF.

5. The control circuit for reducing the idle power consumption of a power supply of claim 4, wherein: the controlled circuit (40) comprises a resistor R9, a resistor R10, a resistor R11, a resistor R12, a switch tube Q1 and a control IC3, wherein one end of the resistor R9 is connected with a hysteresis comparison circuit output end V4, the other end of the resistor R9 is connected with an enable end (EN2) of a control IC3, one end of the resistor R10 is connected with the hysteresis comparison circuit output end V4, the other end of the resistor R10 is connected with a control IC3 synchronous rectification control end (DEMB), one end of the resistor R11 is connected with a frequency control end (RT) of the control IC3, the other end of the resistor R11 is grounded, one end of the resistor R12 is connected with a frequency control end (RT) of the control IC3, the other end of the resistor R12 is connected with a drain of the switch tube Q1, a gate of the switch tube Q1 is connected with the hysteresis comparison circuit output end V4, and a source of the switch tube Q1 is grounded.

6. The control circuit for reducing no-load power consumption of a power supply of claim 3, wherein: the resistance value of the resistor R2 of the differential amplification circuit (20) is equal to the resistance value of the resistor R4, and the resistance value of the resistor R3 is equal to the resistance value of the resistor R5, so that the output end V3 of the differential amplification circuit is equal to (V2-V1) R3/R2.