CN112684845B - Three-junction band gap circuit with zero Kelvin reference voltage - Google Patents
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Abstract
The invention discloses a three-junction band gap circuit with zero Kelvin reference voltage, and belongs to the technical field of integrated circuits. The circuit includes: the device comprises a voltage generation module, a voltage bootstrap module and a voltage summation module. The voltage generation module comprises three diodes, and the three diodes are biased by utilizing positive temperature coefficient current and constant current to obtain output voltages of the three diodes; the voltage bootstrap module comprises three voltage bootstrap units, three input ends of the three voltage bootstrap units are correspondingly connected with cathodes of three diodes in the voltage generation module, and the output voltages of the three diodes are gained to obtain three gain voltages; and three input ends of the voltage summing module are correspondingly connected with output ends of the three voltage bootstrap units, and the three gain voltages are summed to obtain the reference voltage. The invention ideally eliminates all temperature non-linearities, overcomes the disadvantages of bandgap circuits in the prior art, and eliminates the temperature dependence of the reference output voltage.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a three-junction band gap circuit with zero Kelvin reference voltage.
Background
The reference voltage source is an important component in an analog integrated circuit, a precise and stable voltage reference is required in a plurality of integrated circuits (such as an analog-digital converter, a digital-analog converter, a linear voltage regulator and a switching regulator), and no matter which scene is applied, the output voltage of the voltage reference is required to have no variation along with the voltage, the voltage variation is small when the temperature fluctuates, and the output voltage cannot be influenced by the process.
In order to solve the problem of the influence of temperature fluctuation on the voltage, the prior art generally tries to reduce the temperature dependency by reducing the temperature curvature or introducing a second inflection point, for example, a positive temperature coefficient voltage and a negative temperature coefficient voltage are realized in a bandgap circuit, and the positive temperature coefficient voltage and the negative temperature coefficient voltage are added with proper weight to obtain a zero kelvin reference voltage. This is in fact achieved by modifying the basic bandgap circuit to include one or more other higher order temperature dependent terms which may be combined to reduce the overall temperature dependence. The additional term or terms will not naturally track the non-linearity in the original reference output at all times, and therefore require tedious adjustments to achieve a reduction in the reference temperature coefficient.
Disclosure of Invention
The invention provides a three-junction band gap circuit with zero Kelvin reference voltage, which aims to solve the problem that in the prior art, an additional item or a plurality of items can not naturally track the nonlinearity in the original reference output all the time, so that the reference temperature coefficient is reduced by means of complicated adjustment.
In order to solve the above problems, the present invention adopts a technical solution that: a three-junction bandgap circuit of a zero Kelvin reference voltage is provided, which includes a voltage generation module, a voltage bootstrap module and a voltage summation module. The device comprises a voltage generation module, a voltage bootstrap module and a voltage summation module.
The voltage generation module comprises three diodes, two of the diodes are biased by positive temperature coefficient current, and the other diode is biased by constant current to obtain output voltages of the three diodes;
the voltage bootstrap module comprises three voltage bootstrap units, three input ends of the three voltage bootstrap units are respectively input with output voltages of three diodes, and the output voltages of the three diodes are gained to obtain three gain voltages; and the number of the first and second groups,
three input ends of the voltage summing module are correspondingly connected with output ends of the three voltage bootstrap units;
the voltage generation module comprises a first diode, a second diode, a third diode, a first bias resistor, a second bias resistor, a first operational amplifier, a second operational amplifier, a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, wherein the same-direction input end of the first operational amplifier is connected with the drain electrode of the first MOS tube and one end of the first bias resistor, the other end of the first bias resistor is connected with the anode of the first diode, the reverse-direction input end of the first operational amplifier is connected with the drain electrode of the second MOS tube and the anode of the second diode, the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube, the cathode of the second diode is connected with the cathode of the first diode and the cathode of the third diode, the anode of the third diode is connected with the drain electrode of the third MOS tube, the cathode of the third diode is connected with one end of the second bias resistor, the same-direction input end of the second operational amplifier is connected with the output end of the zero Kelvin reference voltage, the reverse input end of the second operational amplifier is connected with the other end of the second bias resistor and the drain electrode of the fourth MOS tube, the output end of the second operational amplifier is connected with the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube, and the source electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are connected;
three voltage bootstrap units in the voltage bootstrap module include a first bootstrap unit, a second bootstrap unit and a third bootstrap unit, wherein the first bootstrap unit includes a fourth bias resistor, an eighth MOS transistor and a third operational amplifier, the second bootstrap unit includes a fifth bias resistor, a ninth MOS transistor and a fourth operational amplifier, the third bootstrap unit includes a sixth bias resistor, a tenth MOS transistor and a fifth operational amplifier, wherein, the non-inverting input terminal of the third operational amplifier inputs the output voltage of the first diode, the inverting input terminal of the third operational amplifier is connected with one end of the fourth bias resistor and the drain electrode of the eighth MOS transistor, the output terminal of the third operational amplifier is connected with the gate electrode of the eighth MOS transistor, the non-inverting input terminal of the fourth operational amplifier inputs the output voltage of the second diode, the inverting input terminal of the fourth operational amplifier is connected with one end of the fifth bias resistor and the drain electrode of the ninth MOS transistor, the output end of the fourth operational amplifier is connected with the grid electrode of the ninth MOS tube, the non-inverting input end of the fifth operational amplifier is connected with the output voltage input into the third diode, the inverting input end of the fifth operational amplifier is connected with one end of the sixth bias resistor and the drain electrode of the tenth MOS tube, the output end of the fifth operational amplifier is connected with the grid electrode of the tenth MOS tube, the source electrodes of the eighth MOS tube, the ninth MOS tube and the tenth MOS tube are connected, and the other ends of the fourth bias resistor, the fifth bias resistor and the sixth bias resistor are connected;
the technical scheme of the invention can achieve the following beneficial effects: the invention provides a three-junction band gap circuit with zero Kelvin reference voltage, which ideally eliminates all temperature nonlinearity, overcomes the defects of the band gap circuit in the prior art, and eliminates the temperature dependence of the reference output voltage.
Drawings
FIG. 1 is a diagram of a bandgap circuit implementing an exemplary positive/negative temperature coefficient voltage in the prior art;
FIG. 2 is a diagram showing a specific example of the basic structure of a bandgap circuit in the prior art;
FIG. 3 is a schematic diagram of one embodiment of a zero Kelvin reference voltage triple junction bandgap circuit of the present invention;
FIG. 4 is a diagram of an embodiment of a voltage generation module in a three-junction bandgap circuit with zero Kelvin reference voltage according to the present invention;
FIG. 5 is a diagram of an embodiment of a voltage bootstrap module in a zero Kelvin reference voltage three-junction bandgap circuit of the present invention;
FIG. 6 is a diagram of a voltage summing module in a three-junction bandgap circuit with zero Kelvin reference voltage according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a specific example of a zero Kelvin reference voltage triple junction bandgap circuit of the present invention.
The components in the drawings are numbered as follows: ra-bias resistor a, Rb-bias resistor b, Q1-first transistor, R1-first bias resistor, R2-second bias resistor, R3-third bias resistor, R4-fourth bias resistor, R5-fifth bias resistor, R6-sixth bias resistor, D1-first diode, D2-second diode, D3-third diode, A1-first operational amplifier, A2-second operational amplifier, A3-third operational amplifier, A4-fourth operational amplifier, A5-fifth operational amplifier, M1-first MOS tube, M2-second MOS tube, M3-third MOS tube, M4-fourth MOS tube, M5-fifth MOS tube, M6-sixth MOS tube, M7-seventh MOS tube, M8-eighth MOS tube, M9-ninth MOS tube, M10-tenth MOS tube, M11-eleventh MOS tube, M12-twelfth MOS tube, M13-thirteenth MOS tube and M14-fourteenth MOS tube.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the prior art, the zero temperature coefficient voltage is obtained by adding two quantities with opposite temperature coefficients with proper weights, and is expressed by the following expression:
VRER＝αV1+βV2
in the first step, the negative temperature coefficient is realized, and the collector current I of the bipolar transistor is realizedcAnd base-emitter voltage VBEThe relationship of (1) is:
in the above expression, IsIs the saturation current, V, of the bipolar transistorTkT/q is the thermal voltage, k is the boltzmann constant, T is the thermodynamic temperature, and q is the electron volume.
When V isTAt 26mV, can be obtained
Deriving the temperature to obtain V at a given temperature TBETemperature coefficient of (2):
wherein
Deriving the temperature to obtain I at a given temperature TsTemperature coefficient of (2):
finally, finishing to obtain:
the second step is to realize positive temperature coefficient, if two transistors work under unequal current density, their VBEThe difference is proportional to the absolute temperature, the specific structure is shown in figure 1,
deriving the temperature to obtain V at a given temperature TBETemperature coefficient of (2):
and thirdly, the temperature coefficient of the whole circuit can be eliminated by superposing the positive temperature coefficient and the negative temperature coefficient, and the structure is shown in figure 2.
Thus obtaining
While taking the derivative of T yields:
it is sufficient to make it equal to 0.
Fig. 3 is a schematic diagram of an embodiment of a zero kelvin reference voltage triple junction bandgap circuit of the present invention.
In this specific embodiment, the three-junction bandgap circuit with zero kelvin reference voltage mainly includes:
the device comprises a voltage generation module, a voltage bootstrap module and a voltage summation module. The device comprises a voltage generation module, a voltage bootstrap module and a voltage summation module. The voltage generation module comprises three diodes, two of the diodes are biased by positive temperature coefficient current, and the other diode is biased by constant current to obtain output voltages of the three diodes; the voltage bootstrap module comprises three voltage bootstrap units, three input ends of the three voltage bootstrap units are respectively input with output voltages of the three diodes, and the output voltages of the three diodes are gained to obtain three gain voltages; and three input ends of the voltage summing module are correspondingly connected with output ends of the three voltage bootstrap units.
In an embodiment of the present invention, the voltage generating module includes a first diode, a second diode, a third diode, a first bias resistor, a second bias resistor, a first operational amplifier, a second operational amplifier, a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, wherein a same-direction input terminal of the first operational amplifier is connected to a drain of the first MOS transistor and one end of the first bias resistor, the other end of the first bias resistor is connected to an anode of the first diode, a reverse-direction input terminal of the first operational amplifier is connected to a drain of the second MOS transistor and an anode of the second diode, an output terminal of the first operational amplifier is connected to a gate of the first MOS transistor and a gate of the second MOS transistor, and a cathode of the second diode is connected to a cathode of the first diode and a cathode of the third diode, the anode of the third diode is connected with the drain electrode of the third MOS tube, the cathode of the third diode is connected with one end of the second bias resistor, the homodromous input end of the second operational amplifier is connected with the output end of the zero Kelvin reference voltage, the reverse input end of the second operational amplifier is connected with the other end of the second bias resistor and the drain electrode of the fourth MOS tube, the output end of the second operational amplifier is connected with the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube, and the source electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are connected. This module generates a voltage to facilitate further bootstrapping of the voltage.
In an embodiment of the invention, the first diode, the second diode and the third diode are all silicon diodes.
In an embodiment of the invention, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are PMOS transistors.
Fig. 4 is a schematic diagram showing a specific example of a voltage generation module in a zero kelvin reference voltage three-junction bandgap circuit according to the present invention.
In this specific example, the voltage generation module includes a diode D1, a diode D2, a diode D3, a bias resistor R1, a bias resistor R2, an operational amplifier a1, an operational amplifier a2, a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, and a MOS transistor M4, wherein a same-direction input terminal of a1 is connected to a drain of M1 and one end of R1, the other end of R1 is connected to an anode of D1, an inverting input terminal of a1 is connected to a drain of M2 and an anode of D2, an output terminal of a1 is connected to a gate of M1 and a gate of M2, a cathode of D2 is connected to a cathode of D1 and a cathode of D3, an anode of D3 is connected to a drain of M3, a cathode of D3 is connected to one end of R3, a same-direction input terminal of A3 is connected to an output terminal of a kelvin voltage, an inverting input terminal of A3 is connected to an inverting input terminal of R3, and a drain of M3, and a drain 3 is connected to a gate of M3, and a drain 3, and a drain of M3, and A3 are connected to a gate of M3, The sources of M2, M3, and M4 are connected. This module generates a voltage to facilitate further bootstrapping of the voltage.
Wherein, the D1, D2 and D3 are all silicon diodes, and the M1, M2, M3 and M4 are all PMOS tubes.
The specific internal operation is as follows, D1 and D2 are biased by positive temperature coefficient current, D3 is biased by constant current, and the weighted sum voltage of three diodes can represent the band gap voltage VG0，
In the above expression, k is Boltzmann's constant, T is the thermodynamic temperature, q is the electron electric quantity, JSDenotes the diode current density, AD1、AD2、AD3Respectively representing the PN junction areas of the three diodes.
If the mirror gain M1: M2 of the current mirror consisting of M1 and M2 is equal to 1, then ID1＝ID2θ T, θ is independent of temperature,
i in the above expressionZTCIs a zero temperature coefficient current.
A brief representation of the expression for the three diode voltages described above is available,
VD1＝VG0+b1T-c1TlnT
VD2＝VG0+b2T-c2TlnT
VD3＝VG0+b3T-c3TlnT
wherein
In an embodiment of the invention, three voltage bootstrap units in the voltage bootstrap module include a first bootstrap unit, a second bootstrap unit, and a third bootstrap unit, where the first bootstrap unit includes a fourth bias resistor, an eighth MOS transistor, and a third operational amplifier, the second bootstrap unit includes a fifth bias resistor, a ninth MOS transistor, and a fourth operational amplifier, the third bootstrap unit includes a sixth bias resistor, a tenth MOS transistor, and a fifth operational amplifier, where a non-inverting input terminal of the third operational amplifier inputs an output voltage of the first diode, an inverting input terminal of the third operational amplifier is connected to one end of the fourth bias resistor and a drain of the eighth MOS transistor, an output terminal of the third operational amplifier is connected to a gate of the eighth MOS transistor, a non-inverting input terminal of the fourth operational amplifier inputs an output voltage of the second diode, an inverting input terminal of the fourth operational amplifier is connected to one end of the fifth bias resistor and a drain of the ninth MOS transistor, the output end of the fourth operational amplifier is connected with the grid electrode of the ninth MOS tube, the non-inverting input end of the fifth operational amplifier is connected with the output voltage input into the third diode, the inverting input end of the fifth operational amplifier is connected with one end of the sixth bias resistor and the drain electrode of the tenth MOS tube, the output end of the fifth operational amplifier is connected with the grid electrode of the tenth MOS tube, the source electrodes of the eighth MOS tube, the ninth MOS tube and the tenth MOS tube are connected, and the other ends of the fourth bias resistor, the fifth bias resistor and the sixth bias resistor are connected. This module bootstraps the voltages in order to further sum the voltages.
In an embodiment of the invention, the eighth MOS transistor, the ninth MOS transistor and the tenth MOS transistor in the voltage bootstrap module are all PMOS transistors.
In an embodiment of the present invention, the third operational amplifier, the fourth operational amplifier and the fifth operational amplifier are all operated in a linear region to avoid tracking nonlinearity in the original reference output.
Fig. 5 is a schematic diagram showing a specific example of a voltage bootstrap module in a zero kelvin reference voltage three-junction bandgap circuit according to the present invention.
In this specific example, three voltage bootstrap units in the voltage bootstrap modules include a first bootstrap unit, a second bootstrap unit, and a third bootstrap unit, where the first bootstrap unit includes a bias resistor R4, a MOS transistor M8, and an operational amplifier A3, the second bootstrap unit includes a bias resistor R5, a MOS transistor M9, and an operational amplifier A4, and the third bootstrap unit includes a bias resistor R6, a MOS transistor M10, and an operational amplifier a5, where a non-inverting input terminal of A3 is input with the output voltage of D1, an inverting input terminal of A3 is connected with one end of R4 and a drain of M8, an output terminal of A3 is connected with a gate of M8, a non-inverting input terminal of A8 is input with the output voltage of D8, an inverting input terminal of A8 is connected with one end of R8 and a drain of M8, an output terminal of A8 is connected with a gate of M8, a non-inverting input terminal of A8 is input with the output voltage of D8, an inverting input terminal of A8 is connected with an inverting input terminal of M8 and a drain of M8, the output terminal of A5 is connected to the gate of M10, the sources of M8, M9 and M10, and the other terminals of R4, R5 and R6. This module bootstraps the voltages in order to further sum the voltages.
Wherein the M8, M9 and M10 are PMOS tubes, and the A3, A4 and A5 operate in linear region to avoid tracking non-linearity in the original reference output.
The specific internal operation is as follows,using three operational amplifier pairs VD1、VD2、VD3Is subjected to gain obtaining ofX1,VX2,VX3。
In an embodiment of the invention, the voltage summing module includes a third bias resistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor, wherein a gate of the fifth MOS transistor is connected to the non-inverting input/output terminal of the third operational amplifier, a drain of the fifth MOS transistor is connected to one end of the third bias resistor, a drain of the eleventh MOS transistor, and a drain of the thirteenth MOS transistor, a gate of the sixth MOS transistor is connected to the non-inverting input/output terminal of the fourth operational amplifier, a drain of the sixth MOS transistor is connected to the gate and the drain of the twelfth MOS transistor, a gate of the seventh MOS transistor is connected to the non-inverting input/output terminal of the fifth operational amplifier, a drain of the seventh MOS transistor is connected to the gate and the drain of the fourteenth MOS transistor, and sources of the fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are connected, the source electrodes of the eleventh MOS tube, the twelfth MOS tube, the thirteenth MOS tube and the fourteenth MOS tube are connected, the source electrode of the eleventh MOS tube is connected with the other ends of the second bias resistor and the third bias resistor and one end of the second bias resistor, which is connected with the cathode of the third diode, the source electrode of the fourteenth MOS tube is connected with the source electrode of the fourth bias resistor and one end of the fifth bias resistor, which is connected with the source electrode of the fourth MOS tube, and the source electrode of the seventh MOS tube is connected with the source electrode of the eighth MOS tube. The module sums the voltages, overcomes the disadvantages of the summing circuit in early operation, eliminates the temperature dependence of the reference output voltage, and eliminates temperature-related factors in the voltages, so as to further obtain a zero Kelvin reference voltage.
In an embodiment of the invention, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor are PMOS transistors, and the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor and the fourteenth MOS transistor are NMOS transistors.
Fig. 6 is a schematic diagram showing a specific example of a voltage summing module in a zero kelvin reference voltage three-junction bandgap circuit according to the present invention.
In this embodiment, the voltage summing module includes a bias resistor R3, a MOS transistor M3 and a MOS transistor M3, wherein the gate of the MOS transistor M3 is connected to the output of the operational amplifier a3, the drain of the MOS transistor M3 is connected to one end of the bias resistor R3, the drain of the MOS transistor M3 and the drain of the MOS transistor M3, the gate of the MOS transistor M3 is connected to the output of the operational amplifier a3, the drain of the MOS transistor M3 is connected to the gate and the drain of the MOS transistor M3, the source of the MOS transistor M3 and the source of the MOS transistor M3, the source of the bias resistor 3, the source of the MOS transistor M3 and the source of the MOS transistor M3 are connected to the cathode of the bias resistor 3, and the bias resistor R3, and the drain of the bias resistor 3 of the transistor M3 are connected to the drain of the operational amplifier a3, the source of MOS pipe M14 is connected with the other end of bias resistor R4 connecting resistor R4, the source of MOS pipe M5 is connected with the source of MOS pipe M4, and the source of MOS pipe M7 is connected with the source of MOS pipe M8. This module sums the voltages, eliminating temperature-related factors in the voltages, in order to further obtain a zero kelvin reference voltage.
Wherein, M5, M6 and M7 are PMOS tubes, and M11, M12, M13 and M14 are NMOS tubes.
The specific internal operation is as follows,
VREF＝K1VD1+K2VD2+K3VD3
and VREF＝aVG0+bT-cTlnT
Wherein a is K1+K2+K3
b＝K1b1+K2b2+K3b3
c＝K1c1+K2c2+K3c3
Reference voltage VREFAfter all temperature-related factors are eliminated, a key expression is obtained:
as long as K1+K2≠0，VREFIt can be used as a temperature independent bandgap reference voltage.
Finally, the
Theta and AD1、AD2、M12、R1There is a certain unique relationship.
The effect of the three bootstrap circuits is to couple VD1、VD2、VD3Conversion to VX1,VX2,VX3Controlling the current flowing through the transistors M8, M9 and M10 to make the voltages at the upper ends of R4, R5 and R6 and VD1、VD2、VD3The three voltages V are obtained by equaling (namely, the current is in a proportional relation with the voltage), then mirroring the current to M5, M6 and M7 of the voltage summing circuit, so that the current flowing through the resistor R3 is R3 (IM5-IM6-IM7), and further obtaining the three voltages VD1、VD2、VD3And voltage summation is realized.
Fig. 7 is a schematic diagram of an embodiment of a zero kelvin reference voltage triple junction bandgap circuit of the present invention.
The voltage generating module, the voltage bootstrapping module, and the voltage summing module are connected as shown in the figure, where the specific connections of the voltage generating module, the voltage bootstrapping module, and the voltage summing module have been described in detail in the above examples, and are not described herein again, and a circuit that actually expresses the zero kelvin bandgap voltage of silicon can be implemented by using the connections shown in the figure to eliminate the temperature dependence of the output voltage.
The above embodiments are merely examples, which are not intended to limit the scope of the present disclosure, and all equivalent structural changes made by using the contents of the specification and the drawings, or any other related technical fields, are also included in the scope of the present disclosure.
Claims (7)
1. A three-junction bandgap circuit with zero Kelvin reference voltage is provided, which comprises,
the voltage generating module, the voltage bootstrap module and the voltage summing module;
the voltage generation module comprises three diodes, two of the diodes are biased by utilizing positive temperature coefficient current, and the other diode is biased by utilizing constant current to obtain output voltages of the three diodes;
the voltage bootstrap module comprises three voltage bootstrap units, three input ends of the three voltage bootstrap units are respectively input with output voltages of the three diodes, and the output voltages of the three diodes are gained to obtain three gain voltages; and the number of the first and second groups,
three input ends of the voltage summing module are correspondingly connected with output ends of the three voltage bootstrap units, and the voltage summing module outputs zero Kelvin reference voltage according to the three gain voltages;
the voltage generation module comprises a first diode, a second diode, a third diode, a first bias resistor, a second bias resistor, a first operational amplifier, a second operational amplifier, a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, wherein the same-direction input end of the first operational amplifier is connected with the drain electrode of the first MOS tube and one end of the first bias resistor, the other end of the first bias resistor is connected with the anode of the first diode, the reverse input end of the first operational amplifier is connected with the drain electrode of the second MOS tube and the anode of the second diode, the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube, and the cathode of the second diode is connected with the cathode of the first diode and the cathode of the third diode, the anode of the third diode is connected with the drain of the third MOS transistor, the cathode of the third diode is connected with one end of the second bias resistor, the homodromous input end of the second operational amplifier is connected with the output end of the zero kelvin reference voltage, the reverse input end of the second operational amplifier is connected with the other end of the second bias resistor and the drain of the fourth MOS transistor, the output end of the second operational amplifier is connected with the gate of the third MOS transistor and the gate of the fourth MOS transistor, and the sources of the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are connected;
the three voltage bootstrap units in the voltage bootstrap module include a first bootstrap unit, a second bootstrap unit, and a third bootstrap unit, wherein the first bootstrap unit includes a fourth bias resistor, an eighth MOS transistor, and a third operational amplifier, the second bootstrap unit includes a fifth bias resistor, a ninth MOS transistor, and a fourth operational amplifier, the third bootstrap unit includes a sixth bias resistor, a tenth MOS transistor, and a fifth operational amplifier, wherein a non-inverting input terminal of the third operational amplifier inputs the output voltage of the first diode, an inverting input terminal of the third operational amplifier is connected to one end of the fourth bias resistor and a drain of the eighth MOS transistor, an output terminal of the third operational amplifier is connected to a gate of the eighth MOS transistor, and a non-inverting input terminal of the fourth operational amplifier inputs the output voltage of the second diode, an inverting input end of the fourth operational amplifier is connected with one end of the fifth bias resistor and a drain electrode of the ninth MOS transistor, an output end of the fourth operational amplifier is connected with a gate electrode of the ninth MOS transistor, a non-inverting input end of the fifth operational amplifier is connected with an output voltage input to the third diode, an inverting input end of the fifth operational amplifier is connected with one end of the sixth bias resistor and a drain electrode of the tenth MOS transistor, an output end of the fifth operational amplifier is connected with a gate electrode of the tenth MOS transistor, source electrodes of the eighth MOS transistor, the ninth MOS transistor and the tenth MOS transistor are connected, and the other ends of the fourth bias resistor, the fifth bias resistor and the sixth bias resistor are connected; the third operational amplifier, the fourth operational amplifier and the fifth operational amplifier respectively output one gain voltage of the three gain voltages.
2. The triple-junction bandgap circuit of claim 1, wherein the voltage summing module comprises a third bias resistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor, wherein a gate of the fifth MOS transistor is connected to the output terminal of the third operational amplifier, a drain of the fifth MOS transistor is connected to one end of the third bias resistor, a drain of the eleventh MOS transistor, and a drain of the thirteenth MOS transistor, a gate of the sixth MOS transistor is connected to the output terminal of the fourth operational amplifier, a drain of the sixth MOS transistor is connected to the gate and the drain of the twelfth MOS transistor, a gate of the seventh MOS transistor is connected to the output terminal of the fifth operational amplifier, and a drain of the seventh MOS transistor is connected to the gate and the drain of the fourteenth MOS transistor, the source electrodes of the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are connected, the source electrodes of the eleventh MOS tube, the twelfth MOS tube, the thirteenth MOS tube and the fourteenth MOS tube are connected, the source electrode of the eleventh MOS tube is connected with the other end of the third bias resistor and one end of the second bias resistor, which is connected with the cathode of the third diode, the source electrode of the fourteenth MOS tube is connected with one end of the fourth bias resistor, which is connected with the fifth bias resistor, the source electrode of the fifth MOS tube is connected with the source electrode of the fourth MOS tube, and the source electrode of the seventh MOS tube is connected with the source electrode of the eighth MOS tube.
3. The zero Kelvin reference voltage three-junction bandgap circuit of claim 1, comprising the first diode, the second diode and the third diode are all silicon diodes.
4. The zero kelvin reference voltage triple-junction bandgap circuit according to claim 1, comprising said first MOS transistor, said second MOS transistor, said third MOS transistor and said fourth MOS transistor in said voltage generating module are all PMOS transistors.
5. The zero Kelvin reference voltage triple-junction bandgap circuit of claim 1, comprising the eighth MOS transistor, the ninth MOS transistor and the tenth MOS transistor in the voltage bootstrap module all being PMOS transistors.
6. The zero kelvin reference voltage triple-junction bandgap circuit according to claim 2, wherein the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor in the voltage summing module are PMOS transistors, and the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor and the fourteenth MOS transistor are NMOS transistors.
7. The zero Kelvin reference voltage triple-junction bandgap circuit of claim 1, comprising the third operational amplifier, the fourth operational amplifier and the fifth operational amplifier all operating in a linear region.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1758176A (en) * | 2005-02-11 | 2006-04-12 | 钰创科技股份有限公司 | Temp stabilized reference voltage circuit |
| CN101533288A (en) * | 2009-04-09 | 2009-09-16 | 中国科学院微电子研究所 | A closed-loop curvature compensation CMOS band-gap reference voltage source |
| CN102622031A (en) * | 2012-04-09 | 2012-08-01 | 中国科学院微电子研究所 | Low-voltage and high-precision band-gap reference voltage source |
| CN103412611A (en) * | 2013-07-18 | 2013-11-27 | 电子科技大学 | High-precision reference voltage source |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW574782B (en) * | 2002-04-30 | 2004-02-01 | Realtek Semiconductor Corp | Fast start-up low-voltage bandgap voltage reference circuit |
| KR100780771B1 (en) * | 2006-06-30 | 2007-11-29 | 주식회사 하이닉스반도체 | Band-gap reference voltage generator |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1758176A (en) * | 2005-02-11 | 2006-04-12 | 钰创科技股份有限公司 | Temp stabilized reference voltage circuit |
| CN101533288A (en) * | 2009-04-09 | 2009-09-16 | 中国科学院微电子研究所 | A closed-loop curvature compensation CMOS band-gap reference voltage source |
| CN102622031A (en) * | 2012-04-09 | 2012-08-01 | 中国科学院微电子研究所 | Low-voltage and high-precision band-gap reference voltage source |
| CN103412611A (en) * | 2013-07-18 | 2013-11-27 | 电子科技大学 | High-precision reference voltage source |
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