CN112670825A - Preparation method of semiconductor device - Google Patents
Preparation method of semiconductor device Download PDFInfo
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- CN112670825A CN112670825A CN202011543029.6A CN202011543029A CN112670825A CN 112670825 A CN112670825 A CN 112670825A CN 202011543029 A CN202011543029 A CN 202011543029A CN 112670825 A CN112670825 A CN 112670825A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
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Abstract
The invention provides a preparation method of a semiconductor device, which relates to the technical field of semiconductors. A lower cladding layer, a waveguide layer, and a ridge-shaped layer are formed on the substrate layer in which the first current blocking region, the channel region, and the second current blocking region are formed. The ridge forming layer is patterned to form a ridge layer having a ridge structure. The ridge-shaped layered partial area is etched through the patterning, namely, the area of the orthographic projection of the ridge structure on the substrate layer is smaller than that before etching. The ridge structure is matched with the channel area to effectively control the path of the current, so that the current is more concentrated, and the electro-optic conversion efficiency of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
Semiconductor devices are lasers using semiconductor materials as working substances, and have the advantages of being small and exquisite, efficient, long in service life, easy to integrate and the like, so that the semiconductor devices are widely applied to the fields of imaging, communication, machining and the like. However, with the advancement of technology, there is a higher demand for semiconductor devices.
The existing semiconductor device generally adopts a laminated semiconductor device epitaxial structure, but the on-state current is not effectively controlled, so that the electro-optic conversion efficiency is lower.
Disclosure of Invention
The present invention is directed to a method for manufacturing a semiconductor device, so as to solve the problem of low electro-optic conversion efficiency of the conventional semiconductor device due to current diffusion.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
in one aspect of the embodiments of the present invention, a method for manufacturing a semiconductor device is provided, where the method includes: forming a first current blocking area and a second current blocking area on the substrate layer, wherein the part of the substrate layer between the first current blocking area and the second current blocking area is a channel area, and the top surfaces of the first current blocking area, the second current blocking area and the channel area are all positioned on the same plane; forming a lower cladding layer, a waveguide layer and a ridge-shaped layer on the substrate layer on which the first current blocking region, the channel region and the second current blocking region are formed; the ridge forming layer is patterned to form a ridge layer having a ridge structure.
Optionally, a lower cladding layer, a waveguide layer, and a ridge-shaped layer are sequentially formed on the substrate layer on which the first current blocking region, the channel region, and the second current blocking region are formed, and the method further includes: forming a lower cladding layer on the substrate layer on which the first current blocking region, the channel region, and the second current blocking region are formed; forming a lower limiting layer, a quantum well and an upper limiting layer as a waveguide layer on the lower cladding layer in sequence; an upper cladding layer and an ohmic contact layer are sequentially formed as ridge-shaped layers on the upper confinement layer.
Optionally, the patterning the ridge layer to form the ridge stripe layer having the ridge stripe structure includes: and patterning the upper cladding layer and the ohmic contact layer to form a patterned upper cladding layer and a patterned ohmic contact layer.
Optionally, after patterning the ridge formation layer to form a ridge stripe layer having a ridge stripe structure, the method further includes: and forming an insulating layer and a conductive layer on the ridge layer, wherein the top surface of the ridge layer is in contact with the conductive layer, the insulating layer is positioned between the ridge layer and the conductive layer, and the insulating layer covers the side wall of the ridge layer.
Optionally, forming the first current blocking region and the second current blocking region on the substrate layer includes: a first current blocking region and a second current blocking region are respectively formed on the substrate layer by ion implantation.
Optionally, forming the first current blocking region and the second current blocking region on the substrate layer includes: etching the substrate layer to form a first etching groove and a second etching groove which are adjacent, wherein a mesa structure is arranged between the first etching groove and the second etching groove; epitaxially growing a current barrier layer on the substrate layer; and carrying out surface planarization treatment on the current blocking layer to expose the mesa structure, wherein the part of the current blocking layer, which is positioned in the first etching groove after the surface planarization treatment, is a first current blocking area, the part of the current blocking layer, which is positioned in the second etching groove after the surface planarization treatment, is a second current blocking area, and the mesa structure, which is positioned between the first current blocking area and the second current blocking area, is a channel area.
Optionally, the orthographic projection area of the channel region on the substrate layer is located within the orthographic projection area of the ridge structure on the substrate layer.
Optionally, the first current blocking region and the second current blocking region are separately located at two sides of the channel region.
Optionally, the first current blocking region and the second current blocking region are disposed around the periphery of the channel region and connected to each other.
Optionally, the channel region is an N-type region, and the first current blocking region and the second current blocking region are P-type layers; or, the channel region is a P-type region, and the first current blocking region and the second current blocking region are N-type layers.
The beneficial effects of the invention include:
the invention provides a preparation method of a semiconductor device, which is characterized in that a first current blocking area and a second current blocking area are formed on a substrate layer, and the part of the substrate layer between the first current blocking area and the second current blocking area is a channel area. Under the current blocking effect of the first current blocking area and the second current blocking area, current passes through the channel area in a concentrated mode, and therefore the path of the current on the substrate layer can be effectively controlled. A lower cladding layer, a waveguide layer, and a ridge-shaped layer are formed on the substrate layer in which the first current blocking region, the channel region, and the second current blocking region are formed. The ridge formation layer is patterned to form a ridge layer. And etching the ridge forming partial area of the whole layer to form the ridge layer with the ridge structure through patterning, namely, the area of the orthographic projection of the ridge structure in the ridge layer on the substrate layer is smaller than that before etching. When a voltage is applied to the semiconductor device, the generated current forms a current channel from the ridge structure formed by the ridge layer to the substrate layer, so that the path and the diffusion area of the current can be effectively limited. The ridge structure of the ridge layer formed by the ridge layering through patterning can be matched with the channel region to effectively control the path of current, so that the current is more concentrated, and the electro-optic conversion efficiency of the device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a second schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 3 is one of schematic substrate layer structures of a semiconductor device according to an embodiment of the present invention;
fig. 4 is a second schematic structural diagram of a substrate layer of a semiconductor device according to an embodiment of the present invention;
FIG. 5 is an enlarged view of a portion of area A of FIG. 3;
fig. 6 is a third schematic structural diagram of a substrate layer of a semiconductor device according to an embodiment of the present invention;
fig. 7 is a fourth schematic structural diagram of a substrate layer of a semiconductor device according to an embodiment of the present invention;
fig. 8 is a third schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 9 is a fourth schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 10 is a fifth schematic structural diagram of a substrate layer of a semiconductor device according to an embodiment of the present invention.
Icon: 100-a substrate layer; 110-a channel region; 111-the top surface of the channel region; 112-the sides of the channel region; 210 — a first current blocking region; 211-first etch trenches; 220-a second current blocking region; 221-a second etching groove; 300-patterning an upper cladding layer; 310-ridge stripe structure; 400-lower cladding; 510-a lower confinement layer; 520-quantum well; 530-upper confinement layer; 600-patterning an ohmic contact layer; 700-a conductive layer; 800-insulating layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. It should be noted that, in the case of no conflict, various features in the embodiments of the present invention may be combined with each other, and the combined embodiments are still within the scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In an aspect of the embodiments of the present invention, there is provided a method for manufacturing a semiconductor device, as shown in fig. 1, the method including: forming a first current blocking area 210 and a second current blocking area 220 on the substrate layer 100, wherein the part of the substrate layer 100 between the first current blocking area 210 and the second current blocking area 220 is a channel area 110, the first current blocking area 210, the second current blocking area 220 and the top surface 111 of the channel area are all located on the same plane, and the plane is parallel to the bottom surface of the substrate layer 100; forming a lower cladding layer 400, a waveguide layer, and a ridge-shaped layer on the substrate layer 100 where the first current blocking region 210, the channel region 110, and the second current blocking region 220 are formed; patterning the ridge layer forms the ridge layer of ridge structure 310.
By way of example, by improving the hierarchical structure of the semiconductor device, the diffusion region of the current and the flowing path of the current are effectively controlled, and the overall performance of the semiconductor device is improved, and the improved structure can be schematically prepared by the following method:
step 1: a first current blocking region 210 and a second current blocking region 220 are formed in the substrate layer 100, and a portion of the substrate layer 100 between the first current blocking region 210 and the second current blocking region 220 is the channel region 110.
As shown in fig. 2, the first current blocking region 210 and the second current blocking region 220 are first formed on the substrate layer 100, i.e., the first current blocking region 210 and the second current blocking region 220 are in the same layer. The portion of the substrate layer 100 between the first current blocking area 210 and the second current blocking area 220 can be used as the channel area 110, so that when an external voltage is applied to the semiconductor device and a current flows through the substrate layer 100, under the current blocking effect of the first current blocking area 210 and the second current blocking area 220, the current does not flow through the positions of the first current blocking area 210 and the second current blocking area 220 around the channel area 110, but flows through the channel area 110 more intensively, so that the path of the current on the substrate layer 100 can be effectively controlled. In actual implementation, the positions, areas or equivalent resistances of the first current blocking region 210 and the second current blocking region 220 on the substrate layer 100 may be reasonably set according to requirements, so that the position and area of the channel region 110 formed along with the first current blocking region 210 and the second current blocking region 220 are on a preset current path. Meanwhile, the diffusion of current may also be controlled using the first current blocking region 210 and the second current blocking region 220.
In addition, the top surface of the first current blocking region 210, the top surface 111 of the channel region, and the top surface of the second current blocking region 220 formed on the substrate layer 100 are all in the same plane, which may be parallel to the substrate plane, so that a functional layer formed on the substrate subsequently may be directly formed in a whole layer, thereby avoiding the need for additional process treatment on the functional layer due to the concave-convex surface of the substrate layer 100, and effectively improving the reliability of the device. For example, when the substrate layer 100 is made of GaAs and the functional layer is made of AlGaAs, the substrate layer 100 may be processed by the present embodiment and then the AlGaAs functional layer may be epitaxially grown, so as to avoid the defect caused by oxidation of Al in the AlGaAs material during the processing process when the AlGaAs functional layer is processed. The first current blocking region 210 and the second current blocking region 220 may be formed using an equivalent reverse biased diode, a dielectric material, or the like. When forming a reverse biased diode, the first current blocking region 210 may be a reverse biased diode directly formed along the current flowing direction, or may be formed by matching with the substrate layer 100, or may be formed by matching with another layer (which may be a functional layer or a matching layer separately disposed) formed on the first current blocking region 210, and the second current blocking region 220 is similar to the first current blocking region.
Step 2: a lower cladding layer 400, a waveguide layer, and a ridge-shaped layer are sequentially formed on the substrate layer 100 where the first current blocking region 210, the channel region 110, and the second current blocking region 220 are formed.
After the substrate layer 100 formed with the current blocking region and the channel region 110 in step 1 is processed, a lower cladding layer 400, a waveguide layer, and a ridge-shaped layer, that is, a part of a functional layer of a semiconductor device, may be formed on the substrate layer 100 by using epitaxial growth.
And step 3: patterning the ridge formation forms a ridge layer having a ridge structure 310.
After the growth of the ridge forming layer is completed in step 2, the ridge forming layer can be formed into a ridge layer with ridge structure 310 through patterning processing, and the ridge layer with ridge structure 310 can be formed by etching the ridge forming layer in the whole ridge forming layer area, that is, the area of the orthographic projection of ridge structure 310 on substrate layer 100 is smaller than that before etching. The shape of the orthographic projection of the ridge structure 310 and the channel region 110 on the substrate layer 100 may be rectangular, a gradual pattern from one end to the other end, such as triangular, trapezoidal (as shown in fig. 10), etc., and when the pattern is a gradual pattern, the gradual angle may be less than 10 degrees. The shape of the orthographic projection of the channel regions 110 on the substrate layer 100 may be arranged with reference to the ridge structure 310. When a voltage is applied to the semiconductor device, the generated current will form a current channel from the ridge stripe structure 310 to the substrate layer 100, and when the current flows through the upper waveguide layer, the current will pass through the ridge stripe structure 310, so that the path and diffusion region of the current can be effectively limited. The ridge structure 310 formed by patterning can effectively control the current path by matching with the channel region 110, so that the current is more concentrated, the electro-optic conversion efficiency of the device is improved, and when the semiconductor device is a semiconductor laser, the semiconductor laser can have a lower laser threshold.
In patterning the ridge-shaped layer, dry etching, wet etching, laser etching, and the like may be used in various forms, and the processes may include resist coating, exposure, development, and the like.
Optionally, the lower cladding layer 400, the waveguide layer, and the ridge-shaped layer are sequentially formed on the substrate layer 100 on which the first current blocking region 210, the channel region 110, and the second current blocking region 220 are formed, and the method further includes: forming a lower cladding layer 400 on the substrate layer 100 where the first current blocking region 210, the channel region 110, and the second current blocking region 220 are formed; forming a lower confinement layer 510, a quantum well 520, and an upper confinement layer 530 as a waveguide layer on the lower cladding layer 400 in this order; an upper cladding layer and an ohmic contact layer are sequentially formed as ridge-shaped layers on the upper confinement layer 530.
For example, as shown in fig. 1, in order to further improve the functional layer, the waveguide layer may include a lower confinement layer 510, a quantum well 520, and an upper confinement layer 530 sequentially formed on the lower cladding layer 400, and the ridge layer may include an upper cladding layer and an ohmic contact layer sequentially formed on the upper confinement layer 530. The process of sequentially forming the lower cladding layer 400, the lower cladding layer 510, the quantum well 520, the upper cladding layer 530, the upper cladding layer and the ohmic contact layer on the substrate layer 100 may be chemical vapor deposition, molecular beam epitaxy, or the like.
Optionally, the patterning the ridge layer to form the ridge stripe layer having the ridge stripe structure includes: the upper cladding layer and the ohmic contact layer are patterned to form a patterned upper cladding layer 300 and a patterned ohmic contact layer 600.
For example, when patterning the ridge formation layer, direct etching may be performed, for example, in fig. 2; or not directly, such as in fig. 1. In fig. 1, the patterned upper cladding layer includes a portion having a ridge and a planar layer remaining by etching, the patterned ohmic contact layer 600 includes only the remaining ridge, and the ridge stripe structure 310 may be formed of the portion having the ridge of the patterned upper cladding layer 300 and the portion having the ridge of the patterned ohmic contact layer 600. As shown in fig. 2, the upper cladding layer and the ohmic contact layer may be completely etched through, i.e., etched until the upper cladding layer, and the etched patterned upper cladding layer 300 and the patterned ohmic contact layer 600 constitute the ridge stripe structure 310. The orthographic projection area of the ridge structure 310 in the formed ridge layer on the substrate layer 100 is positioned in the orthographic projection area of the lower cladding layer 400 on the substrate layer 100, so that the current can be effectively controlled. The channel region 110 corresponds to a waveguide structure, so that mode limitation, such as single mode and few mode, can be realized, high-brightness laser output can be realized, and efficiency can be improved.
Optionally, after patterning the ridge formation layer to form a ridge layer having a ridge structure 310, the method further includes: an insulating layer 800 and a conductive layer 700 are formed on the ridge layer, wherein the top surface of the ridge layer is in contact with the conductive layer 700, the insulating layer 800 is between the ridge layer and the conductive layer 700, and the insulating layer 800 covers the sidewalls of the ridge layer.
For example, after step 3, the insulating layer 800 and the conductive layer 700 may be formed on the ridge layer, and the formed structure may be that the top surface of the patterned ohmic contact layer 600 contacts the bottom surface of the conductive layer 700 (e.g., a metal layer) as shown in fig. 2. Meanwhile, since the ridge layer is formed after patterning, the insulating layer 800 may be disposed in the etched region, so as to insulate and isolate the ridge layer from the conductive layer 700, and the isolation may be performed in a manner that the insulating layer 800 is located between the ridge layer and the conductive layer 700, and meanwhile, the insulating layer 800 also covers the sidewall of the ridge layer, so that the device has better stability. When the conductive layer 700 has a voltage, a current path is formed from the patterned ohmic contact layer 600, the portion of the patterned upper cladding layer 300 having the ridge, the upper confinement layer 530, the quantum well 520, the lower confinement layer 510, the lower cladding layer 400 to the channel region 110 due to the blocking of the insulating layer 800.
The substrate layer 100 may be configured as an N-type substrate or a P-type substrate according to the conductivity type, and the N-type substrate will be schematically described as an example below:
when the substrate layer 100 is an N-type substrate (the corresponding channel region 110 is also an N-type region), the first current blocking region 210 and the second current blocking region 220 are P-type regions, and at this time, the lower cladding layer 400 may be set as an N-type lower cladding layer 400 (or an N-type matching layer may be separately set), so that a reverse PN junction may be formed by matching the N-type lower cladding layer 400 with the P-type first current blocking region 210 or the P-type second current blocking region 220, an NPN structure is formed, and the first current blocking region 210 and the second current blocking region 220 may correspondingly form a current blocking region. The P-type layer doping atoms grown include: C. zn, etc.
Alternatively, forming the first current blocking region 210 and the second current blocking region 220 on the substrate layer 100 includes: the first current blocking region 210 and the second current blocking region 220 are respectively formed on the substrate layer 100 by ion implantation.
For example, as shown in fig. 1, the first current blocking region 210 and the second current blocking region 220 may be formed on the substrate layer 100 by ion implantation, which may be formed by coating a photoresist on the substrate, exposing, developing, and etching, so that the patterned photoresist covers only the top surface of the channel region 110, forming the first current blocking region 210 and the second current blocking region 220 in the regions not covered by the patterned photoresist (which may or may not be connected), and then removing the photoresist to form the substrate layer 100 that is flat and has the first current blocking region 210, the channel region 110, and the second current blocking region 220. The depth of the ion implantation (doping), i.e. in a direction perpendicular to the plane of the substrate layer 100, may be more than 100 nm. The current blocking layer is realized by ion implantation, which may be H, He plasma.
Alternatively, forming the first current blocking region 210 and the second current blocking region 220 on the substrate layer 100 includes: etching the substrate layer 100 to form a first etching groove 211 and a second etching groove 221 which are adjacent, wherein a mesa structure is arranged between the first etching groove 211 and the second etching groove 221; epitaxially growing a current blocking layer on the substrate layer 100; the current blocking layer is subjected to surface planarization to expose the mesa structure, a portion of the current blocking layer, which is located in the first etching groove 211 after the surface planarization, is a first current blocking region 210, a portion of the current blocking layer, which is located in the second etching groove 221 after the surface planarization, is a second current blocking region 220, and the mesa structure, which is located between the first current blocking region 210 and the second current blocking region 220, is a channel region 110.
For example, in step 1, when the first current blocking region 210 and the second current blocking region 220 are formed by epitaxial growth, the following steps may be performed for illustrative purposes:
step 1.1: the substrate layer 100 is etched to form a first etching groove 211 and a second etching groove 221 which are adjacent to each other, and a mesa structure is formed between the first etching groove 211 and the second etching groove 221.
As shown in fig. 3, the substrate layer 100 is etched to form two adjacent first etching trenches 211 and second etching trenches 221 and a mesa structure between the first etching trenches 211 and the second etching trenches 221.
Step 1.2: a current blocking layer is epitaxially grown on the substrate layer 100.
And then, epitaxially growing a current blocking layer on the whole etched substrate layer 100, wherein the material of the current blocking layer can be a P-type material, an N-type material or a dielectric material. The thickness of the grown current blocking layer may be less than the thickness of the mesa structure. All thicknesses in this application refer to values in a direction perpendicular to the plane of the substrate.
Step 1.3: the current blocking layer is subjected to surface planarization to expose the mesa structure, a portion of the current blocking layer, which is located in the first etching groove 211 after the surface planarization, is a first current blocking region 210, a portion of the current blocking layer, which is located in the second etching groove 221 after the surface planarization, is a second current blocking region 220, and the mesa structure, which is located between the first current blocking region 210 and the second current blocking region 220, is a channel region 110.
As shown in fig. 4, the top surface of the substrate layer 100 is made flat by planarizing the surface of the current blocking layer, and the planarizing process may be a polishing process, such as introducing a CMP process, i.e., a chemical mechanical polishing process, which can make the polished whole wafer have a micron-level flatness of less than 1 nm. Meanwhile, the method can also assist wet etching, thereby reducing the surface dislocation density to a certain degree (EPD is less than 1000/cm)2). Thereby reducing the defects of the subsequent epitaxial growth material and improving the quality of the material.
When the surface planarization process is performed, the mesa structure needs to be exposed so that the mesa structure as the channel region 110 can make good contact with the lower cladding layer 400. The first current blocking region 210, the second current blocking region 220, and the top surface 111 of the channel region may all be located on the same plane through the surface planarization process.
The thickness of the channel region 110 (i.e., the thickness of the mesa structure subjected to the surface planarization treatment) may be 20nm or more, and further, may be 100nm or more. The higher the thickness of the channel region 110, the better the current effect.
The width W of the channel region 110 may be, as shown in fig. 6, the maximum distance from the first current blocking region 210 to the second current blocking region 220 in the lateral direction, and the width W of the channel region 110 may be 0.1 to 500 μm, and further may be 5 to 200 μm, and may be reasonably selected according to the size of the device and the implementation capability of the lithography machine in the specific setting.
Illustratively, as shown in fig. 5, the included angle a between the side surface 112 of the channel region and the top surface 111 of the channel region is an obtuse angle, so that the mesa structure forms a trapezoid structure, which can facilitate the growth of the subsequent epitaxial growth layer. In other embodiments, the angle between the side surface 112 of the channel region and the top surface 111 of the channel region may be acute, right-angled, or the like.
Optionally, the orthographic projection area of the channel region 110 on the substrate layer 100 is located within the orthographic projection area of the ridge structure 310 on the substrate layer 100.
For example, in order to make the current controlled better, the channel region 110 and the ridge structure 310 in the ridge layer may be made to correspond, that is, the orthographic projection areas of the two in the same plane (the plane where the bottom surface of the substrate layer 100 is located) may overlap each other, that is, the edges completely overlap, as in fig. 8, one of the two may be located in the orthographic projection area of the other, or there may be a deviation between the orthographic projection areas of the two, and the maximum distance between the edges of the orthographic projection areas of the two should be less than or equal to half of the width of the ridge structure 310. As shown in fig. 9, when there is a deviation between the orthographic projection areas of the two, the deviation b of the center lines of the two should also be less than or equal to one-half of the width of the ridge structure 310.
Optionally, alignment marks are provided at the edge regions of the substrate layer 100.
As an example, the substrate layer 100 may be further provided with one or more alignment marks in an edge region, and when there are a plurality of alignment marks, the alignment marks may be wound along the edge of the substrate layer 100. The alignment mark may be formed simultaneously with the patterning of the substrate layer 100, the formation of the first current blocking region 210 and the second current blocking region 220.
Optionally, the substrate layer structure comprises a plurality of substrate layers 100 formed with a first current blocking region 210, a channel region 110 and a second current blocking region 220, the plurality of substrate layers 100 are arranged in an array, and when the semiconductor device is a semiconductor laser, a bar of the laser can be matched.
Optionally, the first current blocking region 210 and the second current blocking region 220 are spaced at both sides of the channel region 110.
For example, the upper and lower ends of the channel region 110 may directly extend to the upper and lower ends of the substrate, as shown in fig. 6, when viewed from the top of the substrate layer 100, the channel region 110 is located between the first current blocking region 210 and the second current blocking region 220, and the channel region 110 separates the first current blocking region 210 from the second current blocking region 220, so that the first current blocking region 210 and the second current blocking region 220 are spaced apart from each other at two sides of the channel region 110.
Optionally, the first current blocking region 210 and the second current blocking region 220 are disposed around the outer circumference of the channel region 110 and connected to each other.
For example, the upper and lower ends of channel region 110 may not directly extend to the upper and lower ends of the substrate, as shown in fig. 7, when viewed from the top of substrate layer 100, channel region 110 is located between first current blocking region 210 and second current blocking region 220, and first current blocking region 210 and second current blocking region 220 are connected at the upper and lower ends of channel region 110, and in this case, the current channel of substrate layer 100 is only channel region 110 surrounded in the middle.
In another embodiment, one of the upper and lower ends of the channel region 110 may be one end directly extending to the substrate layer 100, the other of the upper and lower ends of the channel region 110 may not directly extend to the other end of the substrate layer 100, when viewed from the top of the substrate layer 100, the channel region 110 is located between the first current blocking region 210 and the second current blocking region 220, and the first current blocking region 210 and the second current blocking region 220 are connected at one end of the channel region 110 and disconnected at the other end.
Optionally, the channel region 110 is an N-type region, and the first current blocking region 210 and the second current blocking region 220 are P-type layers; alternatively, the channel region 110 is a P-type region, and the first and second current blocking regions 210 and 220 are N-type layers.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method of fabricating a semiconductor device, the method comprising:
forming a first current blocking area and a second current blocking area on a substrate layer, wherein the part of the substrate layer between the first current blocking area and the second current blocking area is a channel area, and the top surfaces of the first current blocking area, the second current blocking area and the channel area are all located on the same plane;
sequentially forming a lower cladding layer, a waveguide layer and a ridge-shaped layer on the substrate layer on which the first current blocking region, the channel region and the second current blocking region are formed;
and patterning the ridge forming layer to form a ridge layer with a ridge structure.
2. A method for manufacturing a semiconductor device according to claim 1, wherein a lower cladding layer, a waveguide layer, and a ridge-shaped layer are sequentially formed on the substrate layer on which the first current blocking region, the channel region, and the second current blocking region are formed, the method further comprising:
forming a lower cladding layer on the substrate layer on which the first current blocking region, the channel region, and the second current blocking region are formed;
forming a lower limiting layer, a quantum well and an upper limiting layer as a waveguide layer on the lower cladding layer in sequence;
an upper cladding layer and an ohmic contact layer are sequentially formed as ridge-shaped layers on the upper confinement layer.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the patterning of the ridge formation layer to form a ridge layer having a ridge structure comprises:
and patterning the upper cladding layer and the ohmic contact layer to form a patterned upper cladding layer and a patterned ohmic contact layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein after the patterning of the ridge formation layer to form a ridge layer having a ridge structure, the method further comprises:
and forming an insulating layer and a conductive layer on the ridge layer, wherein the top surface of the ridge layer is in contact with the conductive layer, the insulating layer is positioned between the ridge layer and the conductive layer, and the insulating layer covers the side wall of the ridge layer.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the first current blocking region and the second current blocking region on the substrate layer comprises:
and respectively forming a first current blocking area and a second current blocking area on the substrate layer through ion implantation.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the first current blocking region and the second current blocking region on the substrate layer comprises:
etching the substrate layer to form a first etching groove and a second etching groove which are adjacent, wherein a mesa structure is arranged between the first etching groove and the second etching groove;
epitaxially growing a current blocking layer on the substrate layer;
and performing surface planarization treatment on the current blocking layer to expose the mesa structure, wherein the part of the current blocking layer, which is positioned in the first etching groove after the surface planarization treatment, is the first current blocking area, the part of the current blocking layer, which is positioned in the second etching groove after the surface planarization treatment, is the second current blocking area, and the mesa structure, which is positioned between the first current blocking area and the second current blocking area, is the channel area.
7. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein an orthographic projection area of the channel region on the substrate layer is located within an orthographic projection area of the ridge structure on the substrate layer.
8. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the first current blocking region and the second current blocking region are spaced apart on both sides of the channel region.
9. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the first current blocking region and the second current blocking region are provided around a periphery of the channel region and are connected to each other.
10. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the channel region is an N-type region, and the first current blocking region and the second current blocking region are P-type layers; or, the channel region is a P-type region, and the first current blocking region and the second current blocking region are N-type layers.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63169093A (en) * | 1987-01-06 | 1988-07-13 | Fujikura Ltd | Semiconductor laser |
| FR2693047A1 (en) * | 1992-06-24 | 1993-12-31 | Fujitsu Ltd | Heterostructure semiconductor laser fabrication method with epitaxy on mesa patterned substrate - using epitaxial MOCVD growth of current stop gallium arsenide layer on sides of mesa stripe, with tri:methyl gallium as source gas |
| US5887011A (en) * | 1996-09-25 | 1999-03-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor laser |
-
2020
- 2020-12-22 CN CN202011543029.6A patent/CN112670825A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63169093A (en) * | 1987-01-06 | 1988-07-13 | Fujikura Ltd | Semiconductor laser |
| FR2693047A1 (en) * | 1992-06-24 | 1993-12-31 | Fujitsu Ltd | Heterostructure semiconductor laser fabrication method with epitaxy on mesa patterned substrate - using epitaxial MOCVD growth of current stop gallium arsenide layer on sides of mesa stripe, with tri:methyl gallium as source gas |
| US5887011A (en) * | 1996-09-25 | 1999-03-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor laser |
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Application publication date: 20210416 |