CN112670401A - Josephson junction and superconducting device and preparation method thereof - Google Patents
Josephson junction and superconducting device and preparation method thereof Download PDFInfo
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- CN112670401A CN112670401A CN202011518329.9A CN202011518329A CN112670401A CN 112670401 A CN112670401 A CN 112670401A CN 202011518329 A CN202011518329 A CN 202011518329A CN 112670401 A CN112670401 A CN 112670401A
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Abstract
The invention provides a Josephson junction, a superconducting device and a preparation method thereof, wherein the preparation method of the Josephson junction comprises the following steps: forming a first superconducting material layer, a barrier material layer and a second superconducting material layer on a substrate; etching the second superconducting material layer to form an upper electrode; depositing an insulating material on the barrier material layer, etching away, and etching the barrier layer; and finally, etching the first superconducting material layer to obtain the lower electrode. According to the invention, before the barrier layer is etched, a layer of insulating material is deposited, the insulating material is etched based on the same mask layer, the photoresist is not removed, and then the barrier layer is etched, so that the barrier layer is well protected, and the barrier layer is prevented from reacting with a developing solution to generate a black reactant. The insulating layer deposited first can also improve the insulating effect of the insulating layer deposited later, reduce leakage current, realize homogeneous growth, have no obvious interface between the insulating layer and the insulating layer, have no influence on subsequent processes, and can improve the performance and stability of the superconducting circuit and the working range of the whole superconducting circuit.
Description
Technical Field
The invention relates to the technical field of superconducting quantum devices, in particular to a Josephson junction, a superconducting SQUID device, a superconducting SFQ device and preparation methods thereof.
Background
The superconducting circuit is an electronic device prepared by using a superconducting material, and mainly comprises a superconducting quantum interference device (SQUID), a single magnetic flux quantum device (SFQ) and the like. The superconducting quantum interference device (SQUID) is based on the Josephson effect and flux quantization principle, and its basic structure is that two Josephson junctions are inserted into the superconducting ring, and the SQUID is the most sensitive magnetic flux detecting sensor known at present, and the magnetic flux noise of typical SQUID device is measured at mu phi0/Hz1/2Magnitude (1 phi)0＝2.07×10-15Wb) with magnetic field noise at fT/Hz1/2Magnitude (1fT ═ 1 × 10)-15T), because of its extremely high sensitivity, can be widely applied to medical heart magnetism brain magnetism, material detection, earth magnetic field, military affairs, earthquake and archaeology, etc. the magnetic flux microscope prepared with it can be engaged in basic research. Single Flux Quantum devices (SFQ) are superconducting circuit technologies that use a Single Flux Quantum within a josephson junction to represent logic "1" and "0". The clock frequency of the superconducting digital circuit based on the frequency can reach 770GHz, and the superconducting digital circuit can be used for ultra-wideband analog-digital/digital-analog converters, wideband network switches, radio astronomical digital autocorrelators, superconducting computers and the like of radar and communication systems. Because of its advantages of high speed and low power consumption, the strategic research is invested in the united states and japan.
The superconducting circuit is generally composed of a Josephson junction and some resistors, inductors and the like which are matched with each other. Wherein, the Josephson junction is a key device of the superconducting circuit, and the formation and the preparation of the Josephson junction are closely related to the excellent performance of the superconducting circuit. Josephson junctions are generally structures formed by two superconductor clamps with a very thin barrier layer (thickness. ltoreq. the coherence length of a Coopper electron pair), such as the S (superconductor) -I (semiconductor or insulator) -S (superconductor) structure, SIS for short, in which superconducting electrons can tunnel through a thin film of semiconductor or insulator from one side to the other. Therefore, the preparation and formation of the barrier layer directly influence the excellent performance of the Josephson junction, and how to prepare and photo-etch the barrier layer in the Josephson junction is the key of device preparation, however, the barrier layer is generally very thin, usually only a few nanometers, and generally reacts with alkaline developer in the photo-etching process, so that the single photo-etching controllability and repeatability are poor, and some black reactants are easily formed on the surface of the circuit, thereby influencing the work of the whole circuit.
Therefore, how to provide a josephson junction, a superconducting device based on the josephson junction and a preparation method thereof is necessary to solve the problems in the prior art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a josephson junction, a superconducting device based on the same, and a method for manufacturing the same, which are used to solve the problems of the prior art that a barrier layer is difficult to be effectively manufactured, and the like.
To achieve the above and other related objects, the present invention provides a method for preparing a josephson junction, comprising the steps of:
(1) providing a substrate;
(2) sequentially forming a first superconducting material layer, a barrier material layer and a second superconducting material layer on the substrate, wherein the barrier material layer comprises an aluminum-containing material layer;
(3) etching the second superconducting material layer to obtain an upper electrode;
(4) forming a first insulating material layer on the surface of the structure obtained in the step (3);
(5) etching the first insulating material layer and the barrier material layer based on the same mask layer to obtain a barrier layer and a first insulating layer covering the exposed surfaces of the barrier layer and the first electrode, and removing the etched mask layer;
(6) and etching the first superconducting material layer to obtain the lower electrode.
Optionally, the preparation method further comprises:
forming a second insulating material layer on the surface of the structure obtained in the step (6);
etching the second insulating material layer to form a second insulating layer, wherein the second insulating layer and the first insulating layer form a composite insulating layer, and a first opening exposing the upper electrode and a second opening exposing the lower electrode are formed in the composite insulating layer;
preparing a second wiring layer on the composite insulating layer, the wiring layer including a first wiring section electrically connected to the upper electrode through the first opening and a second wiring section electrically connected to the lower electrode through the second opening.
Optionally, the aluminum-containing material layer comprises at least one of an aluminum layer, an aluminum oxide layer and an aluminum nitride layer; the process of forming the mask layer comprises a step of developing by using an alkaline developing solution.
Optionally, the substrate comprises at least one of a silicon substrate, a magnesium oxide substrate, a sapphire substrate, and a silicon carbide substrate; the first superconducting material layer comprises at least one of a niobium nitride layer and a niobium layer; the second superconducting material layer includes at least one of a niobium nitride layer and a niobium layer.
Optionally, the thickness of the first layer of insulating material is between 5-50 nm; the deposition process of the first insulating material layer comprises a PECVD process; the first insulating material layer is made of silicon dioxide or silicon nitride.
Optionally, the method for etching the first insulating material layer includes using a reactive ion etching or inductively coupled reactive ion etching method; the method for etching the barrier material layer comprises an ion beam etching method, wherein the ion beam angle is between 0 and 50 degrees.
The present invention also provides a method for preparing a superconducting SQUID device, the method for preparing a superconducting SQUID device comprising the step of preparing a josephson junction by the method for preparing a josephson junction according to any one of the above steps, further comprising: a step of preparing a shunt resistance on the substrate before forming the first superconducting material layer, the barrier material layer, and the second superconducting material layer.
The present invention also provides a method of manufacturing a superconducting SFQ device, the method of manufacturing the superconducting SFQ device including a step of manufacturing a josephson junction using the method of manufacturing a josephson junction as described in any one of the above steps, further including: a step of preparing a shunt resistance on the substrate before forming the first superconducting material layer, the barrier material layer, and the second superconducting material layer or after forming the lower electrode.
The invention also provides a josephson junction structure for protecting a barrier layer, wherein the josephson junction structure is preferably prepared by the preparation method of the josephson junction structure, and can adopt other modes, and the josephson junction comprises the following steps:
a substrate;
and the lower electrode is positioned on the substrate.
A barrier layer on the lower electrode, the barrier layer comprising a layer of aluminum-containing material;
an upper electrode on the barrier layer;
the first insulating layer covers the exposed surfaces of the barrier layer and the upper electrode;
and a second insulating layer formed on the substrate to cover the lower electrode and the first insulating layer.
Optionally, the aluminum-containing material layer comprises at least one of an aluminum layer, an aluminum oxide layer and an aluminum nitride layer; the thickness of the first insulating material layer is between 5 and 50 nm; the first insulating material layer is made of silicon dioxide or silicon nitride.
The present invention also provides a superconducting SQUID device comprising a josephson junction according to any of the above schemes.
The invention also provides a superconducting SFQ device comprising a josephson junction as described in any of the above schemes.
As described above, the present invention provides a josephson junction, a superconducting device based on the same, and a method for preparing the same, by depositing an insulating layer before etching a barrier layer aluminum material, etching the insulating material based on the same mask layer, without removing a photoresist, then etching a barrier layer, and finally removing the photoresist, the situation that the aluminum material reacts with a developing solution during photolithography is avoided, the barrier layer is well protected, and the generation of black reaction products is avoided. In addition, the insulating layer deposited first can also improve the insulating effect of the junction insulating layer deposited later, so that the leakage current is reduced, the junction insulating layer and the second insulating layer can grow in the same quality, no obvious interface exists between the junction insulating layer and the second insulating layer, and no influence is caused on the subsequent process. The Josephson junction structure for protecting the barrier layer and the preparation method thereof can improve the performance and stability of the superconducting circuit, thereby improving the working range of the whole superconducting circuit.
Drawings
Fig. 1 shows a schematic view of a method for fabricating a josephson junction for protecting a barrier layer according to the present invention.
Fig. 2 is a schematic structural view showing a semiconductor substrate provided in the fabrication of a josephson junction device structure according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of deposition of superconducting and barrier layers in preparation of a Josephson junction structure according to an embodiment of the present invention.
Fig. 4 shows a schematic structural view of an upper electrode fabricated for a josephson junction device structure in an embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating the formation of a first insulating material layer in the fabrication of a josephson junction device structure according to an embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating etching of the first insulating material layer and the barrier material layer in the fabrication of a josephson junction device structure according to an embodiment of the present invention.
Fig. 7 is a schematic diagram illustrating the formation of a lower electrode structure in the fabrication of a josephson junction device structure according to an embodiment of the present invention.
Fig. 8 is a schematic diagram illustrating the deposition of a second insulating material layer in the fabrication of a josephson junction device structure according to an embodiment of the present invention.
Fig. 9 is a schematic diagram illustrating the formation of a first opening and a second opening in the fabrication of a josephson junction device structure according to an embodiment of the present invention.
Fig. 10 is a schematic diagram illustrating deposition of a third layer of superconducting material in fabrication of a josephson junction device structure according to an embodiment of the present invention.
Fig. 11 is a schematic structural view of a superconducting SQUID device according to an embodiment of the present invention.
Fig. 12 is a schematic diagram of a superconducting SFQ device according to an embodiment of the present invention.
FIG. 13 is a schematic diagram of another embodiment of a superconducting SFQ device.
Description of the element reference numerals
001 semiconductor substrate
002 first layer of superconducting material
003 barrier material layer
004 second superconducting material layer
005 upper electrode layer
006 first layer of insulating material
007 first insulating layer
008 barrier layer
009 lower electrode layer
100 second insulating material layer
101 composite insulating layer
102 wiring layer
200 semiconductor substrate
201 resistance layer
202 first layer of insulating material
205 upper electrode
206 barrier layer
207 second insulating material layer
208 lower electrode
209 third insulating material layer
210 wiring layer
020 insulating layer
21 first opening
22 second opening
23 third opening
24 fourth opening
S1-S9
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. In addition, "between … …" as used herein includes both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, number and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
The first embodiment is as follows:
as shown in fig. 1, the present invention provides a method for preparing a josephson junction, the method comprising the steps of:
s1, providing a substrate;
s2, forming a first superconducting material layer, a barrier material layer and a second superconducting material layer on the substrate in sequence, wherein the barrier material layer comprises an aluminum-containing material layer;
s3, etching the second superconducting material layer to obtain an upper electrode;
s4, forming a first insulating material layer on the surface of the structure obtained in the step S3;
s5, etching the first insulating material layer and the barrier material layer based on the same mask layer to obtain a barrier layer and a first insulating layer covering the exposed surfaces of the barrier layer and the first electrode, and removing the etched mask layer;
and S6, etching the first superconducting material layer to obtain a lower electrode.
The following will describe the method for fabricating the josephson junction device structure of the present invention in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the fabrication sequence of the josephson junction device structure of the present invention, and those skilled in the art can change the sequence according to the actual process steps, and fig. 1 shows only one exemplary fabrication step of the josephson junction device structure.
As shown in S1 in fig. 1 and fig. 2, step S1 is performed to provide a semiconductor substrate 001. The semiconductor substrate 001 may include at least one of a silicon substrate, a magnesium oxide substrate, a sapphire substrate, and a silicon carbide substrate. In this embodiment, the semiconductor substrate 001 is a Si (111) substrate, and silicon is used as a substrate.
As shown in S2 in fig. 1 and fig. 3, step S2 is performed to form a first superconducting material layer 002, a barrier material layer 003, and a second superconducting material layer 004 in this order on the semiconductor substrate 001.
Specifically, the first superconducting material layer 002 includes at least one of a niobium nitride layer and a niobium layer, that is, may be one of them, or may be a laminated structure of two kinds of layers; the second superconducting material layer 004 may include at least one of a niobium nitride layer and a niobium layer, that is, may have one of them or a stacked structure of two kinds of layers; in addition, the barrier material layer 003 is an aluminum-containing material layer; the aluminum-containing material layer may include at least one of an aluminum layer, an aluminum oxide layer, and an aluminum nitride layer, and may have a stacked structure of two or more kinds. In this embodiment, the first superconducting material layer 002 is an Nb layer; the second layer of superconducting material 004 is a Nb layer; the barrier material layer 003 is an Al-AlOx layer.
As shown in S3 in fig. 1 and fig. 4, step S3 is performed to etch the second superconducting material layer 004 to obtain the upper electrode 005. The upper electrode 005 may be fabricated in a conventional manner, for example, by photolithography-etching. The shape and layout of the upper electrode 005 can be designed according to actual requirements.
As shown in S4 in fig. 1 and fig. 5, step S4 is performed to form a first insulating material layer 006 on the surface of the structure obtained by etching the second superconducting material layer 004. Specifically, the thickness of the first insulating material layer 006 is between 5nm and 50nm, and may be selected from 10nm, 20nm, 30nm, and 40 nm. In one example, the deposition process of the first insulating material layer 006 includes a PECVD process, which is prepared using a low deposition rate, the deposition rate being less than 20nm/min, for example, 15nm/min, 10nm/min, 8nm/min, 5 nm/min; the insulating layer directly protects the josephson junction, and the first insulating material layer 006 covers the upper electrode 005 and the barrier material layer 003 simultaneously, so that the first insulating material layer 006 can have good coverage on the device structure below the first insulating material layer based on the above process. In an example, the material of the first insulating material layer 006 includes silicon dioxide or silicon nitride.
As shown in S5 in fig. 1 and fig. 6, step S5 is performed to etch the first insulating material layer 006 using a mask layer (not shown), and the barrier material layer 003 is directly etched based on the same mask without removing photoresist, so as to obtain the barrier layer 008 and the first insulating layer 007 covering the surface of the barrier layer 008 and the surface of the upper electrode 005, and the mask layer is removed after the barrier layer 008 is formed.
In one example, a method of etching the first insulating material layer 006 includes using a reactive ion etching or an inductively coupled reactive ion etching method; the method for etching the barrier material layer 003 includes an ion beam etching IBE method, wherein the ion beam angle is between 0 ° and 50 °, for example, 10 °, 20 °, 30 °, 40 ° may be selected. In one example, the same photoresist pattern is used for etching twice, the insulating layer is etched by using trifluoromethane, the barrier layer is almost etched to zero under the etching condition, over etching cannot be formed, and the etching angle is adjusted to reduce the side wall generated by IBE etching when the barrier layer is subsequently etched by using IBE.
As shown in S6 of fig. 1 and S6 of fig. 7, the first superconducting material layer 002 is etched to obtain the lower electrode 009. The lower electrode 009 may be fabricated in a conventional manner, for example, by photo-etching. The shape and layout of the bottom electrode 009 can be designed according to actual requirements.
In addition, in one example, the preparation method further includes the steps of:
first, as shown in fig. 8, a second insulating material layer (not shown) is deposited on the surface of the structure where the lower electrode 009 is formed, and preferably, the material of the second insulating material layer is consistent with the material of the first insulating material layer 006, so that the second insulating material layer can be grown into the composite insulating material layer 100 with the first insulating material layer 006. The material of the composite insulating material layer 100 may be silicon dioxide or silicon nitride, and when the second insulating material layer and the first insulating material layer 006 realize homogeneous growth, no obvious interface exists between the two layers, which has no influence on the subsequent process.
Next, as shown in fig. 9, after obtaining the composite insulating material layer 100, a step of etching the composite insulating material layer 100 is further included to obtain a composite insulating layer 101. The composite insulating layer 101 includes a first opening 1 exposing the upper electrode 005 and a second opening 2 exposing the lower electrode 009. In addition, the etching of the composite insulating material layer may adopt the existing photolithography-etching process, but is not limited thereto.
Finally, as shown in fig. 10, a superconducting material is deposited on the composite insulating layer 101 to form a second wiring layer 102, thereby extracting an electric signal. Specifically, the material of the second wiring layer 102 includes at least one of niobium nitride and niobium, and in this embodiment, the second wiring layer 102 is a niobium layer; specifically, the first wiring layer 102 is electrically connected to the upper electrode 005 through the first opening 1 to form a first wiring portion, and is connected to the lower electrode 009 through the second opening 2 to form a second wiring portion.
In addition, as shown in fig. 10 and referring to fig. 1 to 9, the invention also provides a device structure of a josephson junction device. The josephson junction device structure comprises: a substrate 001; a lower electrode 009, the lower electrode 009 being located on the substrate 001; a barrier layer 008, the barrier layer 008 over the lower electrode 009, the barrier layer 008 comprising a layer of aluminum-containing material; the composite insulating layer 101, the composite insulating layer 101 is positioned on the surface of the barrier layer 008; an upper electrode 005 on the barrier layer 008; the composite insulating layer 101 is composed of two parts, and a first insulating layer 007 whose one part covers the exposed surfaces of the barrier layer and the upper electrode; another portion is a second insulating material layer (not shown) covering the bottom electrode and the first insulating layer. A wiring layer 102, the second wiring layer 102 being located above the composite insulating layer 101.
As an example, the aluminum-containing material layer includes at least one of an aluminum layer, an aluminum oxide layer, and an aluminum nitride layer.
As an example, the thickness of the first insulating layer 007 is between 5-50 nm.
As an example, the first insulating layer 007 and the second insulating material layer are made of the same material. Preferably, the material of the first insulating material layer includes silicon dioxide or silicon nitride.
Example two:
as shown in fig. 11, the present invention further provides a method for preparing a superconducting SQUID device, wherein the method for preparing a superconducting SQUID device according to the second embodiment comprises a step of preparing a josephson junction by using the method for preparing a josephson junction according to any one of the first embodiment, further comprising: a step of preparing a shunt resistance on the substrate before forming the first superconducting material layer, the barrier material layer, and the second superconducting material layer.
In a specific example, the method for manufacturing the superconducting SQUID device comprises the following steps:
(1) a substrate 200 is provided.
(2) A superconducting circuit parallel resistance layer 201 is prepared to constitute the shunt resistor, and the resistance layer 201 is positioned on the surface of the substrate 200. In an example, an insulating material layer may be formed on the substrate 200, and then the insulating material layer is etched and deposited to form the resistive layer 201, and the material of the resistive layer may be a resistive material in an existing SQUID device. In a further alternative example, the resistive layer 201 is formed on a surface of the substrate 200.
(3) An insulating material layer is formed on the substrate and the resistive layer 201, and the insulating material layer is etched to form an insulating layer 202. In one example, the resistive layer 201 is covered with a layer of insulating material. Of course, in other examples, the insulating layer 202 may be formed of an insulating material layer forming a resistive layer.
The method of example one is then used to prepare subsequent josephson junction structures, which may be, for example:
(4) a first superconducting material layer, a barrier material layer, and a second superconducting material layer are sequentially formed on the first insulating layer 202.
(5) Etching the second superconducting material layer to obtain an upper electrode 203;
(6) forming a second insulating material layer on the surface of the structure obtained in the step (5);
(7) etching the second insulating material layer and the barrier material layer based on the same mask layer to obtain a barrier layer 206 and a second insulating layer 207 covering the surface of the barrier layer and the upper electrode, and removing the mask layer after the barrier layer is formed;
(8) the first superconducting material layer is etched to obtain the lower electrode 208.
(7) Forming a third insulating material layer on the surface of the structure obtained in the step (8); in an example, before depositing the third insulating material layer, a step of preparing a third opening 23 in the material layer on the upper surface of the resistive layer to expose the resistive layer is further included, and an interconnection connecting the lower electrode and the resistive layer is further formed based on the third opening 23.
(8) And etching the third insulating material layer to obtain a third insulating layer 209, wherein the third insulating layer 209, the second insulating layer 207 and the first insulating layer 202 can be grown to be an insulating layer 020 in a homogeneous manner. A first opening 21 exposing the upper electrode, a second opening 22 exposing the lower electrode, and a fourth opening 24 exposing the resistive layer are formed in the insulating layer 020;
(9) a first wiring layer 210 including a first wiring portion connected to the upper electrode through the first opening 21 and a second wiring portion connected to the lower electrode through the second opening 22, and a third wiring portion connected to the resistive layer through the fourth opening 24 are formed on the third insulating layer.
Based on the above embodiment, the josephson junction structure of the protective barrier layer and the preparation method thereof of the invention can improve the performance and stability of the superconducting circuit, thereby improving the working range of the whole superconducting circuit. Of course, the shunt resistor can be prepared by other methods in the prior art, and the structure, connection with the josephson junction, layout and the like of the shunt resistor can be prepared by the existing methods.
In addition, the present invention also provides a superconducting SQUID device, wherein the superconducting SQUID device in the second embodiment comprises the josephson junction according to any one of the first embodiment. The superconducting SQUID device also comprises a bypass resistor which can be designed by adopting the structure of the existing bypass resistor. The superconducting SQUID device in the second embodiment is preferably prepared by the method for preparing the device in the second embodiment, but not limited thereto.
Example three:
in addition, as shown in fig. 12 and 13, the present invention further provides two methods for manufacturing a superconducting SFQ device, wherein the method for manufacturing a superconducting SFQ device according to the third embodiment includes a step of manufacturing a josephson junction by using the method for manufacturing a josephson junction according to any one of the first embodiment, and further includes: a step of preparing a shunt resistor on the substrate before forming the first superconducting material layer, the barrier material layer, and the second superconducting material layer, and a step of preparing a shunt resistor in parallel with the josephson junction after forming the lower electrode.
In a specific example, as shown in fig. 12, the method for manufacturing a superconducting SFQ device includes:
(1) providing a substrate 300;
(2) a superconducting circuit parallel resistance layer 301 is prepared to constitute the shunt resistance, and the resistance layer 301 is located on the surface of the substrate 300. In an example, an insulating material layer may be formed on the substrate 300, and then the insulating material layer is etched to deposit the resistive layer 301, and the material of the resistive layer may be a resistive material in an existing device. In a further alternative example, the resistive layer 301 is formed on a surface of the substrate 300.
(3) A first insulating material layer is formed on the substrate and the resistive layer 301, and the first insulating material layer is etched to form a first insulating layer 302. In one example, the resistive layer 301 is covered with a layer of insulating material. Of course, in other examples, the first insulating layer may be formed of an insulating material layer forming a resistive layer.
(4) A first superconducting material layer, a barrier material layer, and a second superconducting material layer are sequentially formed on the first insulating layer 302.
(5) Etching the second superconducting material layer to obtain an upper electrode 303;
(6) forming a second insulating material layer on the surface of the structure obtained in the step (5);
(7) etching the second insulating material layer and the barrier material layer based on the same mask layer to obtain a barrier layer 306 and a second insulating layer 307 covering the surface of the barrier layer and the upper electrode, and removing the mask layer after the barrier layer is formed;
(8) the first superconducting material layer is etched to obtain the lower electrode 308.
(7) Forming a third insulating material layer on the surface of the structure obtained in the step (8); in an example, before depositing the third insulating material layer, a step of preparing a third opening 33 in the material layer on the upper surface of the resistive layer to expose the resistive layer is further included, and an interconnection connecting the lower electrode and the resistive layer is further formed based on the third opening 33.
(8) And etching the third insulating material layer to obtain a third insulating layer 309, wherein the third insulating layer 309 can realize homogenous growth with the second insulating layer 307 and the first insulating layer 303. A first opening 31 exposing the upper electrode, a second opening 32 exposing the lower electrode and a fourth opening 34 exposing the resistive layer are formed in the three insulating layers;
(9) a third wiring layer 311 including a first wiring portion connected to the upper electrode through the first opening 31 and a second wiring portion connected to the lower electrode through the second opening 32, and a third wiring portion connected to the resistive layer through the fourth opening 34 is prepared on the third insulating layer.
(10) Forming a fourth insulating material layer on the surface of the structure obtained in the step (9); and etching the fourth insulating material layer to obtain a fourth insulating layer 310, wherein the fourth insulating layer 310 can be grown to be an insulating layer 030 with the third insulating layer 309, the second insulating layer 307 and the first insulating layer 303. The insulating layer 030 has formed therein fifth, sixth, and seventh openings 35, 36, and 37 exposing the second wiring layer;
(11) preparing a fourth wiring layer 312 on the fourth insulating layer, including through the fifth opening 35, the sixth opening 36, and the seventh opening 37; the fourth wiring layer is grounded. That is, one insulating layer (fourth insulating layer 310) and one metal layer (fourth wiring layer 312) are additionally provided on the wiring layer 311, and the upper metal layer is connected to the ground of the external test to be grounded.
In addition, in another specific example, as shown in fig. 13, in this example, it is possible to prepare with reference to the example of fig. 12: a substrate 400, a resistive layer 401, a first insulating layer 402, an upper electrode 403, a barrier layer 406, a second insulating layer 407, a lower electrode 408, a third insulating layer 409, a first opening 41, a second opening 42, a third opening 43, a fourth opening 44, an insulating layer 040, a fourth insulating layer 410, a third wiring layer 411, a fourth wiring layer 412, a fifth opening 45, a sixth opening 46, and a seventh opening 47. The SFQ device in this example is different from the SFQ device of the example shown in fig. 12 in that a resistive layer 401 (shunt resistor) is prepared and formed after the formation of the lower electrode and before the preparation of the wiring layer, that is, in one example, it may be that an insulating layer is prepared and photo-etched after the formation of the lower electrode, then the preparation of the superconducting circuit parallel resistor (the resistive layer 401) is performed, then an insulating layer and photo-etched are deposited on the resistor, then an Nb superconducting wiring layer is deposited and photo-etched to form a pattern, and finally an insulating layer is prepared and photo-etched, a superconducting Nb ground layer is prepared, and photo-etched to form a pattern.
In addition, as shown in fig. 12 and 13, the present invention further provides two superconducting SFQ devices, wherein the superconducting SFQ device in the third embodiment comprises the josephson junction according to any one of the first embodiment. The superconducting SFQ device also comprises a bypass resistor which can be designed by adopting the structure of the existing bypass resistor. The superconducting SFQ device in the third embodiment is preferably prepared by the method for preparing the device in the third embodiment, but not limited thereto.
In summary, according to the josephson junction, the superconducting device based on the josephson junction and the preparation method, the insulating layer is deposited before the barrier layer aluminum material is etched, the insulating material is etched based on the same mask layer, the photoresist is not removed, the barrier layer is etched, and the photoresist is removed finally, so that the situation that the barrier layer aluminum material reacts with the developing solution during photoetching is avoided, the barrier layer is well protected, and the generation of black reaction products is avoided. In addition, the insulating layer deposited first can also improve the insulating effect of the junction insulating layer deposited later, thereby reducing leakage current, and the junction insulating layer can grow with the second insulating layer, and the two layers have no obvious interface and have no influence on the subsequent process. The Josephson junction structure for protecting the barrier layer and the preparation method thereof can improve the performance and stability of the superconducting circuit, thereby improving the working range of the whole superconducting circuit. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be accomplished by those skilled in the art without departing from the spirit and scope of the present invention as set forth in the appended claims.
Claims (12)
1. A method of preparing a josephson junction, comprising the steps of:
(1) providing a substrate;
(2) sequentially forming a first superconducting material layer, a barrier material layer and a second superconducting material layer on the substrate, wherein the barrier material layer comprises an aluminum-containing material layer;
(3) etching the second superconducting material layer to obtain an upper electrode;
(4) forming a first insulating material layer on the surface of the structure obtained in the step (3);
(5) etching the first insulating material layer and the barrier material layer based on the same mask layer to obtain a barrier layer and a first insulating layer covering the exposed surfaces of the barrier layer and the upper electrode, and removing the etched mask layer;
(6) and etching the first superconducting material layer to obtain the lower electrode.
2. The method of preparing a josephson junction according to claim 1, further comprising:
forming a second insulating material layer on the surface of the structure obtained in the step (6);
etching the second insulating material layer to form a second insulating layer, wherein the second insulating layer and the first insulating layer form a composite insulating layer, and a first opening exposing the upper electrode and a second opening exposing the lower electrode are formed in the composite insulating layer;
preparing a second wiring layer on the composite insulating layer, the wiring layer including a first wiring section electrically connected to the upper electrode through the first opening and a second wiring section electrically connected to the lower electrode through the second opening.
3. The method of preparing a josephson junction according to claim 1, wherein the aluminum-containing material layer comprises at least one of an aluminum layer, an aluminum oxide layer and an aluminum nitride layer; the process of forming the mask layer comprises a step of developing by adopting an alkaline developing solution.
4. The method of manufacturing a josephson junction according to claim 1, wherein the substrate comprises at least one of a silicon substrate, a magnesium oxide substrate, a sapphire substrate, and a silicon carbide substrate; the first superconducting material layer comprises at least one of a niobium nitride layer and a niobium layer; the second superconducting material layer includes at least one of a niobium nitride layer and a niobium layer.
5. The method of preparing a josephson junction according to any one of claims 1 to 4, wherein the thickness of the first layer of insulating material is between 5 and 50 nm; the deposition process of the first insulating material layer comprises a PECVD process; the first insulating material layer is made of silicon dioxide or silicon nitride.
6. The method of preparing a josephson junction according to claim 5, wherein the method of etching the first layer of insulating material comprises using a reactive ion etching or inductively coupled reactive ion etching method; the method for etching the barrier material layer comprises an ion beam etching method, wherein the ion beam angle is between 0 and 50 degrees.
7. A method for producing a superconducting SQUID device, comprising a step of producing a josephson junction by the method for producing a josephson junction according to any one of claims 1 to 6, further comprising: a step of preparing a shunt resistance on the substrate before forming the first superconducting material layer, the barrier material layer, and the second superconducting material layer.
8. A method of manufacturing a superconducting SFQ device, comprising the step of manufacturing a josephson junction using the method of manufacturing a josephson junction according to any one of claims 1 to 6, further comprising:
a step of preparing a shunt resistance on the substrate before forming the first superconducting material layer, the barrier material layer, and the second superconducting material layer or after forming the lower electrode.
9. A Josephson junction, wherein the Josephson junction comprises:
a substrate;
and the lower electrode is positioned on the substrate.
A barrier layer on the lower electrode, the barrier layer comprising a layer of aluminum-containing material;
an upper electrode on the barrier layer;
the first insulating layer covers the exposed surfaces of the barrier layer and the upper electrode;
and a second insulating layer formed on the substrate to cover the lower electrode and the first insulating layer.
10. The josephson junction of claim 9, wherein the layer of aluminum-containing material comprises at least one of a layer of aluminum, a layer of aluminum oxide, and a layer of aluminum nitride; the thickness of the first insulating material layer is between 5 and 50 nm; the first insulating material layer is made of silicon dioxide or silicon nitride.
11. A superconducting SQUID device, comprising the josephson junction of any one of claims 9-10.
12. A superconducting SFQ device comprising the josephson junction of any one of claims 9-10.
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