CN112653457B - High-frequency voltage-controlled oscillator system - Google Patents
High-frequency voltage-controlled oscillator system Download PDFInfo
- Publication number
- CN112653457B CN112653457B CN202011485706.3A CN202011485706A CN112653457B CN 112653457 B CN112653457 B CN 112653457B CN 202011485706 A CN202011485706 A CN 202011485706A CN 112653457 B CN112653457 B CN 112653457B
- Authority
- CN
- China
- Prior art keywords
- frequency
- voltage
- controlled oscillator
- phase
- loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000013078 crystal Substances 0.000 claims description 15
- 238000004364 calculation method Methods 0.000 claims description 7
- 230000010355 oscillation Effects 0.000 description 41
- 238000000034 method Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 12
- 238000004891 communication Methods 0.000 description 6
- 230000010363 phase shift Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006880 cross-coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a high-frequency voltage-controlled oscillator system which comprises a low-frequency phase-locked loop and an external-loop voltage-controlled oscillator, wherein the low-frequency phase-locked loop comprises an internal-loop voltage-controlled oscillator, the external-loop voltage-controlled oscillator and the internal-loop voltage-controlled oscillator are controlled by control voltage locked by the low-frequency phase-locked loop, the external-loop voltage-controlled oscillator comprises M delay units, the M delay units are connected in a cascade mode and then input and output, the internal-loop voltage-controlled oscillator comprises N delay units, the N delay units are connected in a cascade mode and then input and output, and M is less than N. The high-frequency voltage-controlled oscillator system provided by the invention can avoid the problems of high complexity, high power consumption and the like caused by designing a high-frequency phase-locked loop on the basis of outputting stable output frequency and phase.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a high-frequency voltage-controlled oscillator system.
Background
The oscillator is used as the most critical carrier generation circuit in the communication circuit of the radio frequency transceiver, and the type selection and the performance of the oscillator directly influence the normal operation of the radio frequency transmitter and the receiver. There are three common oscillators:
1) A crystal oscillator. The output frequency of the crystal oscillator has high precision and good stability, and is usually used for a frequency generator in a communication system to provide a stable external input reference clock frequency for the communication system. However, the current crystal oscillator is not compatible in CMOS process and has high cost.
2) An LC oscillator. The LC oscillator forms an oscillation loop by using the cross coupling of an inductor and a capacitor, and although the capacitor and the inductor can be compatible in the current CMOS process, the introduction of the capacitor and the inductor increases the process requirement of a chip, and has higher manufacturing cost and higher design complexity. The LC oscillator is generally applied to some radio frequency communication systems with high requirements on indexes such as phase noise.
3) A ring oscillator. The ring oscillator is an oscillator with a simpler structure, usually, three cascaded CMOS inverters can form a ring oscillator, the oscillation frequency of the ring oscillator is determined by the inherent transmission delay of a digital logic gate circuit, an inductance element is not needed, the ring oscillator can be realized by adopting a pure digital CMOS process, the integration level is high, and the ring oscillator is extremely superior in terms of chip area and cost. However, when the ring oscillator is manufactured, the noise performance of the ring oscillator is poor and the oscillation frequency is difficult to control because the delay of the gate circuit is influenced by the process deviation and the external environment temperature, so that the ring oscillator is rarely applied to a radio frequency communication system at present.
The above background disclosure is only for the purpose of assisting understanding of the concept and technical solution of the present invention and does not necessarily belong to the prior art of the present patent application, and should not be used for evaluating the novelty and inventive step of the present application in the case that there is no clear evidence that the above content is disclosed at the filing date of the present patent application.
Disclosure of Invention
In order to solve the technical problems, the invention provides a high-frequency voltage-controlled oscillator system which can avoid the problems of high complexity, high power consumption and the like caused by designing a high-frequency phase-locked loop on the basis of outputting stable output frequency and phase.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention discloses a high-frequency voltage-controlled oscillator system which comprises a low-frequency phase-locked loop and an external-ring voltage-controlled oscillator, wherein the low-frequency phase-locked loop comprises an internal-ring voltage-controlled oscillator, the external-ring voltage-controlled oscillator and the internal-ring voltage-controlled oscillator are controlled by control voltage locked by the low-frequency phase-locked loop, the external-ring voltage-controlled oscillator comprises M time delay units, the M time delay units are connected in an input and output mode after being cascaded, the internal-ring voltage-controlled oscillator comprises N time delay units, the N time delay units are connected in an input and output mode after being cascaded, and M is less than N.
Preferably, the delay unit is formed by cascading Q CMOS inverters, wherein Q is odd number, and Q ≧ 3.
Preferably, the CMOS inverter includes an NMOS transistor for controlling the delay and an input control terminal to form a controllable delay inverter.
Preferably, the low-frequency phase-locked loop further includes a frequency divider, a phase frequency detector and a charge pump, the frequency divider is connected to the output end of the voltage-controlled ring oscillator and is used for dividing the frequency of the output signal of the voltage-controlled ring oscillator to obtain the frequency of the output signal of the voltage-controlled ring oscillator after frequency division, the phase frequency detector is connected to the output end of the frequency divider and is used for comparing the frequency of the output signal of the voltage-controlled ring oscillator after frequency division with a reference frequency input by an external crystal oscillator and obtaining a phase frequency offset, and the charge pump is connected to the output end of the phase frequency detector and is used for converting the phase frequency offset into a current and forming the control voltage.
Preferably, the low-frequency phase-locked loop further includes a loop low-pass filter, and the loop low-pass filter is connected to an output end of the charge pump to charge and discharge the current converted by the charge pump to form the control voltage.
Preferably, wherein the number N of the delay cells in the voltage-controlled-oscillator-within-loop is based on
The calculation result of (2) is evaluated: when in use
When it is an integer, N is a value of
Is calculated as
When non-integer, N takes the value of
Rounded integers are obtained by the calculation of (1); wherein f is ext Is the output frequency of the out-of-ring voltage controlled oscillator, D is the frequency dividing ratio of the frequency divider, f ref And inputting a reference frequency for the external crystal oscillator.
Preferably, the frequency dividing ratio D of the frequency divider and/or the reference frequency f input by the external crystal oscillator are/is adjusted ref So that N takes on the value of odd and M the value of odd.
Preferably, if the value of N is even and M is odd, the ring internal voltage controlled oscillator further includes an additional inverter, where the additional inverter is cascaded after the N delay units and the inputs of the N delay units are connected to the output of the additional inverter.
Preferably, M is an odd number, further, M =1.
Preferably, the frequency output by the ring external voltage-controlled oscillator is 380 MHz-5.3 GHz, and the frequency output by the ring internal voltage-controlled oscillator is 20 MHz-280 MHz.
Compared with the prior art, the invention has the beneficial effects that: the invention provides a high-frequency voltage-controlled oscillator system based on low-frequency phase-locked loop locking oscillation frequency, which comprises a low-frequency phase-locked loop and an annular voltage-controlled oscillator outside a loop, wherein the two voltage-controlled oscillators are formed by cascading delay units with the same structure but different composition numbers, and the oscillation frequencies of the voltage-controlled oscillator inside the phase-locked loop and the annular voltage-controlled oscillator outside the phase-locked loop are controlled by the same control voltage locked by the low-frequency phase-locked loop, so that the oscillation frequencies of the two voltage-controlled oscillators are in proportional relation; therefore, the low-frequency phase-locked loop can be used for locking the outer-loop high-frequency voltage-controlled oscillator which is in proportional relation with the inner frequency of the phase-locked loop through the control voltage locked in the loop while the low-frequency phase-locked loop is used for locking the inner-loop low-frequency voltage-controlled oscillator, so that the phase noise and the frequency deviation of the outer-loop voltage-controlled oscillator are reduced, the outer-loop high-frequency voltage-controlled oscillator outputs a high-frequency signal with stable frequency and phase when being locked, and the influence of process deviation and external environment temperature on the annular oscillator due to the delay of a gate circuit during manufacturing is avoided. Therefore, the high-frequency voltage-controlled oscillator system provided by the invention fully utilizes the advantages of the ring voltage-controlled oscillator, overcomes the defects of the ring voltage-controlled oscillator, and designs the high-frequency voltage-controlled oscillator system with good frequency stability and low process sensitivity, so that the ring voltage-controlled oscillator can be applied to a radio frequency communication system, such as an ultra-wideband radio frequency transceiver.
Drawings
Fig. 1 is a schematic structural diagram of a high-frequency voltage-controlled oscillator system based on a proportional phase-locked loop according to a preferred embodiment of the invention;
FIG. 2 is a schematic diagram of a basic delay cell according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an out-of-loop voltage controlled oscillator according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a voltage controlled oscillator within a ring according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a ring internal voltage controlled oscillator according to another embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the embodiments of the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element. In addition, the connection may be for either a fixing function or a circuit connection function.
Because the single annular voltage-controlled oscillator is easily influenced by factors such as process deviation, working environment change and the like, the single annular voltage-controlled oscillator has the problems of poor phase noise performance, unstable frequency offset and the like. However, in the design of the high-frequency ring voltage-controlled oscillator, it is very difficult to implement a high-frequency phase-locked loop because signals in the loop generate large power consumption during high-speed flipping and the requirement on the high-frequency performance of other modules in the phase-locked loop is high. In order to avoid the problems caused by designing a high-frequency phase-locked loop, the invention provides a low-frequency phase-locked loop with proportional relation of oscillation frequency to lock the oscillation frequency of a high-frequency voltage-controlled oscillator.
As shown in fig. 1, a preferred embodiment of the present invention discloses a high-frequency voltage-controlled oscillator system based on a proportional phase-locked loop, which includes a low-frequency phase-locked loop and an out-of-loop voltage-controlled oscillator 20, wherein the low-frequency phase-locked loop includes an in-loop voltage-controlled oscillator 11, a frequency divider 12, a phase frequency detector 13, a charge pump 14 and a loop filter 15, and both the out-of-loop voltage-controlled oscillator 20 and the in-loop voltage-controlled oscillator 11 are controlled by a control voltage V locked by the low-frequency phase-locked loop ctl And controlling, wherein the ring external voltage-controlled oscillator 20 comprises M basic delay units, the M basic delay units are cascaded and then input and output connected, the ring internal voltage-controlled oscillator 11 comprises N basic delay units, the N basic delay units are cascaded and then input and output connected, and M is less than N.
The external ring voltage-controlled oscillator 20 outside the phase-locked loop is formed by connecting M basic delay units in cascade and then inputting and outputting, wherein M is an odd number, the oscillation frequency of the voltage-controlled oscillator is determined by the delay of the basic delay units, the smaller the delay is, the higher the oscillation frequency is, and the delay of the basic delay units is controlled by a control voltage V ctl The oscillation frequency of the ring-outside voltage-controlled oscillator is determined by the control voltage V ctl Control, V ctl Provided by a low frequency phase locked loop.
The voltage-controlled oscillator 11 in the phase-locked loop is formed by connecting N basic delay units in cascade connection and then connecting input and output, wherein N is an odd number. The ring internal voltage-controlled oscillator 11 and the ring external voltage-controlled oscillator 20 share the control voltage V generated by the same phase-locked loop ctl The difference is that the number of basic delay cells used is different. In general, the out-of-loop vco 20 is required to operate at a higher frequency, the number of used basic delay units is small, and is usually one, and the in-loop vco 11 is stabilized at a relatively lower oscillation frequency because the phase noise of the phase-locked loop at a low frequency and the power consumption are much lower at a higher frequency oscillation.
In a low frequency phase-locked loop, a frequency divider 12 is connected to the output of a voltage-controlled oscillator 11 in the loopAnd at the output end, the phase frequency detector 13 is connected to the output end of the frequency divider 12, the charge pump 14 is connected to the output end of the phase frequency detector 13, the loop low-pass filter 15 is connected to the output end of the charge pump 14, and the voltage-controlled oscillator 11 in the loop is connected to the output end of the loop low-pass filter 15 to form a low-frequency phase-locked loop, wherein the low-frequency phase-locked loop is used for stabilizing the frequency and the phase of an output signal of the voltage-controlled oscillator through control voltage generated by the loop. Wherein, the frequency division ratio of the frequency divider 12 is D, and the frequency f output by the ring internal voltage controlled oscillator 11 in After D frequency division is carried out, a low-frequency reference source frequency f input by an external crystal oscillator is output ref Oscillating signals of similar magnitude; the phase frequency detector 13 inputs the low-frequency reference source frequency f ref Comparing the frequency and the phase of the output signal of the frequency divider 12 to obtain phase-frequency deviation; the charge pump 14 converts the phase frequency deviation detected by the phase frequency detector 13 into a current with a certain proportion, and then the current is charged and discharged through the loop low-pass filter 15, so that the control voltage V is changed ctl To change the oscillation frequency of the out-of-loop voltage controlled oscillator 20 and the in-loop voltage controlled oscillator 11. The loop low-pass filter 15 is used for filtering high-frequency noise and noise in the loop, and a second-order passive resistance-capacitance filter structure is adopted to increase the stability of the loop of the phase-locked loop.
The basic delay unit is formed by cascading odd number (more than or equal to 3) of CMOS inverters, in order to enable the delay of the inverters to be controllable, the adopted CMOS inverter can be a controllable delay inverter, and compared with a common inverter, the inverter is additionally provided with an NMOS (N-channel metal oxide semiconductor) tube for controlling the delay and an input control end; when the input and output phases of the basic delay units are connected to form a loop, a ring voltage-controlled oscillator can be formed. As shown in fig. 2, the basic delay unit of the present embodiment that constitutes the ring external voltage-controlled oscillator 20 and the ring internal voltage-controlled oscillator 11 is a unit that is composed of three controllable delay inverters, and the delay of each controllable delay inverter is τ cinv Therefore, the total delay τ of the basic delay unit of this embodiment is: τ =3 τ cinv 。
The high frequency ring voltage controlled oscillator of the present invention is further described below by taking an example in which the ring voltage controlled oscillator is composed of a basic delay unit.
As shown in fig. 3, for an out-of-loop voltage controlled oscillator formed by a basic delay unit in a specific embodiment, that is, M =1, since each stage of inverter in the basic delay unit provides a 180 ° dc phase shift and a maximum 90 ° ac phase shift, the input and output of the basic delay unit are connected to form a negative feedback loop, and there is a 180 ° dc phase shift in the loop, and each stage of inverter contributes a 60 ° ac phase shift at the oscillation frequency, and the loop satisfies the ring oscillator oscillation starting condition. Oscillation frequency f of the out-of-ring voltage-controlled oscillator of this embodiment ext Comprises the following steps:
control voltage V generated by a phase-locked loop ctl The oscillation frequency of the external-ring voltage-controlled oscillator is controlled by controlling a basic time delay unit in the external-ring voltage-controlled oscillator.
As shown in FIG. 4, the ring-shaped voltage-controlled oscillator is formed by connecting the input and output of N basic delay cells, and the oscillation frequency of the ring-shaped voltage-controlled oscillator is determined by the total delay of all the delay cells forming the structure, i.e. the oscillation frequency f of the ring-shaped voltage-controlled oscillator in Can be expressed as:
after a certain time, the phase-locked loop enters a locking state, and the oscillation frequency f of the voltage-controlled oscillator in the phase-locked loop is at the moment in Locking, i.e. controlling, the control voltage V controlling the delay of the basic delay cells in a voltage-controlled oscillator in a loop ctl Locking, at this time, the oscillation frequency f of the ring outside voltage controlled oscillator ext At a control voltage V ctl The locking is simultaneously obtained. In this embodiment, the oscillation frequency of the out-of-loop voltage-controlled oscillator outside the phase-locked loop is a target value to be realized, and the target value is a predetermined determination value f ext The frequency dividing ratio D of the frequency divider in the phase-locked loop is fixed, when the reference frequency input by the external crystal oscillator is f ref The oscillation frequency of the voltage-controlled oscillator in the phase-locked loop is in a frequency-locked stateFinal locking to f in ＝D×f ref At this time, the number N of the basic delay units of the ring internal voltage-controlled oscillator is:
the above embodiments are substituted into numerical examples to calculate and illustrate: if the oscillation frequency generated by the external voltage-controlled oscillator is required to be f ext An oscillation signal of =3.8GHz, and an input reference clock frequency provided by an external crystal oscillator or other precise frequency generators is f ref =50MHz, the division ratio of the frequency divider is D =4, and the final locking frequency of the ring internal voltage-controlled oscillator is f in =200MHz, and the number of basic delay units forming the ring internal voltage-controlled oscillator is
In the above embodiment with numerical examples, the number N of the calculated basic delay units is an integer and an odd number, and any other processing is not required, and only after the N basic delay units are cascaded, the input and output are connected to form a feedback loop. When the value of N calculated by the above method is not an integer, it is necessary to perform approximation processing of rounding, and the result N after approximation is * If the number is odd, no other processing is needed, and the number of the basic delay units is N * In this case, the phase-locked loop can still be locked at a predetermined oscillation frequency point after a certain period of time, and the influence on the oscillation frequency of the out-of-loop voltage-controlled oscillator is small because the deviation is small. If the calculated number N of the basic delay units is even or the result N after rounding up approximation * If the number of the ring-shaped voltage-controlled oscillators is even, the ring-shaped voltage-controlled oscillators do not meet the oscillation starting condition (if N is even, the voltage-controlled oscillator loop is formed by an even number of inverters with the direct-current phase shift of 180 degrees, and finally the direct-current phase shift in the loop is 0 degrees, so the oscillation starting condition of the ring-shaped oscillators is not met), and at the moment, the structure of the ring-shaped voltage-controlled oscillators needs to be corrected. As shown in fig. 5, an additional controllable delay inverter is added in the ring of the ring voltage-controlled oscillator, because of the delay of the controllable delay inverterTime tau cinv The controllable delay inverter is very small, so that the addition of the controllable delay inverter does not have great influence on the final system, and the system can be locked on a specified oscillation frequency within a certain time.
Although the stable frequency deviation brought to the system by adding an additional controllable delay inverter is very small, the stable frequency deviation still exists and cannot be eliminated and avoided. Therefore, in a specific embodiment, if the requirement for precision is high, and a high-frequency voltage-controlled oscillator system with higher precision is required, in order to avoid the deviation, the function of other components in the above-mentioned N value calculation formula may be exerted, for example, two methods of changing the frequency division ratio D of the frequency divider or changing the reference frequency of the reference clock source input by the external crystal oscillator, or both of them may be changed, so that the N value just satisfies the odd condition.
The above details how to lock a proportional relationship high frequency voltage controlled oscillator by designing a low frequency phase locked loop. The invention provides a brand-new oscillator design method for the technical field, and solves the outstanding problems of difficult realization of a high-frequency phase-locked loop, high power consumption and the like when designing a high-frequency oscillator which stably outputs high-frequency. The high-frequency voltage-controlled oscillator which utilizes the low-frequency phase-locked loop to lock the frequency proportional relation can effectively reduce the process deviation and can be effectively applied to scenes with the requirements on low power consumption, high integration level, high frequency and the like of the oscillator.
The voltage-controlled oscillator used in the embodiment of the invention is formed by cascading one or more than one basic delay units, the delay of the basic delay units is controlled by a control voltage, when the control voltage is determined, the delay of the basic delay units is also determined, and the oscillation frequency of the oscillator is inversely proportional to the total delay of the delay units forming the oscillator, therefore, the oscillation frequency of the oscillator can be controlled by controlling the control voltage of the delay units. In a preferred embodiment, the ring voltage-controlled oscillator inside the phase-locked loop is formed by cascading an odd number of basic delay cells, the ring voltage-controlled oscillator outside the phase-locked loop is formed by one basic delay cell, and the control voltage of the ring voltage-controlled oscillator outside the phase-locked loop is provided by the phase-locked loop and is consistent with the control voltage of the ring voltage-controlled oscillator inside the phase-locked loop, so that when the frequency of the voltage-controlled oscillator inside the phase-locked loop is locked by the control voltage, the frequency of the voltage-controlled oscillator outside the phase-locked loop is locked, and the oscillation frequencies of the voltage-controlled oscillators inside and outside the phase-locked loop are in a proportional relationship, which is referred to as proportional loop oscillation in the present invention. The key point of the invention is that the number of the basic delay units needed in the phase-locked loop is determined by the proportional relation between the voltage-controlled oscillator outside the loop and the voltage-controlled oscillator in the low-frequency phase-locked loop.
In the invention, three frequency indexes are provided, one is the oscillation frequency f of the ring external voltage-controlled oscillator ext And secondly the oscillation frequency f of the ring-controlled oscillator in Thirdly, the precise reference frequency f input into the loop by the external crystal oscillator ref The three frequency quantities are mutually related and have a certain proportional relation, and the proportional relation enables the oscillator system based on the proportional phase-locked loop to generate stable and controllable oscillation frequency, so that the aim of locking the high-frequency voltage-controlled oscillator through the low-frequency phase-locked loop is fulfilled.
In other embodiments of the present invention, if the vco 20 is formed by connecting M basic delay cells in cascade and then connecting the M basic delay cells to an input/output phase, and M is an odd number, the oscillation frequency f of the vco is the odd number ext Comprises the following steps:
oscillation frequency f of ring internal voltage-controlled oscillator formed by N basic time delay units connected in input and output in Can be expressed as:
at this time, the number N of the basic delay units of the voltage-controlled oscillator in the ring is as follows:
at this time, N is according to
The calculation result of (2) is evaluated: when the temperature is higher than the set temperature
When it is an integer, N takes the value of
As a result of the calculation of
When non-integer, N takes the value of
Rounded integers are calculated as (a). In a specific use process, the frequency dividing ratio D of the frequency divider and/or the frequency f input by the external crystal oscillator can be adjusted ref So that N takes on an odd number. If the value of N is even, an additional inverter can be further included in the ring internal voltage controlled oscillator, the additional inverter is cascaded after the N basic delay units, and the inputs of the N basic delay units are connected with the output of the additional inverter.
In some embodiments, the frequency output by the ring external voltage-controlled oscillator is a high frequency of 380MHz to 5.3GHz, and the frequency output by the ring internal voltage-controlled oscillator is a low frequency of 20MHz to 280 MHz. In the practical use process, the low frequency and the high frequency can be only a relative concept, that is, the frequency output by the external ring voltage-controlled oscillator is higher than the frequency output by the internal ring voltage-controlled oscillator, and then the frequency output by the external ring voltage-controlled oscillator is the high frequency and the frequency output by the internal ring voltage-controlled oscillator is the low frequency; according to the invention, the frequency output by the external-ring voltage-controlled oscillator is higher than the frequency output by the internal-ring voltage-controlled oscillator only by meeting the condition that M is less than N, namely, the locked control voltage is provided for the external-ring voltage-controlled oscillator through the phase-locked loop with relatively low frequency, so that the external-ring voltage-controlled oscillator outputs a high-frequency signal with stable frequency and phase when being locked.
In summary, the preferred embodiment of the present invention provides a method for implementing a ring-shaped voltage-controlled oscillator system with high integration and controllable oscillation frequency, which can effectively reduce process deviation, and provides a prominent innovative technology for locking a high-frequency voltage-controlled oscillator by a low-frequency phase-locked loop.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several equivalent substitutions or obvious modifications can be made without departing from the spirit of the invention, and all the properties or uses are considered to be within the scope of the invention.
Claims (9)
1. A high-frequency voltage-controlled oscillator system is characterized by comprising a low-frequency phase-locked loop and an external-loop voltage-controlled oscillator, wherein the low-frequency phase-locked loop comprises an internal-loop voltage-controlled oscillator, the external-loop voltage-controlled oscillator and the internal-loop voltage-controlled oscillator are controlled by control voltage locked by the low-frequency phase-locked loop, the external-loop voltage-controlled oscillator comprises M delay units, the M delay units are connected in a cascade mode and then input and output, the internal-loop voltage-controlled oscillator comprises N delay units, the N delay units are connected in a cascade mode and then input and output, and M is less than N;
the low-frequency phase-locked loop further comprises a frequency divider, a phase frequency detector and a charge pump, wherein the frequency divider is connected to the output end of the voltage-controlled ring oscillator and used for dividing the frequency of the output signal of the voltage-controlled ring oscillator to obtain the frequency of the output signal of the voltage-controlled ring oscillator after frequency division, the phase frequency detector is connected to the output end of the frequency divider and used for comparing the frequency of the output signal of the voltage-controlled ring oscillator after frequency division with a reference frequency input by an external crystal oscillator to obtain a phase-frequency deviation, and the charge pump is connected to the output end of the phase frequency detector and used for converting the phase-frequency deviation into a current and forming the control voltage;
the number N of the delay units in the voltage-controlled oscillator in the ring is determined according to
The calculation result of (2) is evaluated: when in use
When it is an integer, N is a value of
Is calculated as
When non-integer, N takes the value of
Rounded integers are obtained by the calculation of (1); wherein, f ext Is the output frequency of the out-of-ring voltage controlled oscillator, D is the frequency dividing ratio of the frequency divider, f ref And the reference frequency is input by the external crystal oscillator.
2. The high frequency voltage controlled oscillator system according to claim 1, wherein the delay unit is formed by a cascade of Q CMOS inverters, wherein Q is an odd number and Q ≧ 3.
3. The vco system of claim 2 wherein the CMOS inverter comprises an NMOS transistor for controlling delay and an input control terminal to form a controlled delay inverter.
4. The system according to claim 1, wherein the low frequency phase locked loop further comprises a loop low pass filter coupled to an output of the charge pump to charge and discharge the current converted by the charge pump to form the control voltage.
5. The system of claim 1, wherein the dividing ratio D of the frequency divider and/or the reference frequency f of the external crystal oscillator input are adjusted ref So that N takes on the value of odd and M the value of odd.
6. The vco system of claim 1, wherein if N is even and M is odd, the vco further comprises an additional inverter cascaded after N of the delay cells and wherein inputs of the N of the delay cells are connected to an output of the additional inverter.
7. The high frequency voltage controlled oscillator system of claim 1 wherein M is an odd number.
8. The high frequency voltage controlled oscillator system of claim 7, wherein M =1.
9. The high frequency voltage controlled oscillator system of claim 1, wherein the frequency output by the external-ring voltage controlled oscillator is a high frequency of 380MHz to 5.3GHz, and the frequency output by the internal-ring voltage controlled oscillator is a low frequency of 20MHz to 280 MHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011485706.3A CN112653457B (en) | 2020-12-16 | 2020-12-16 | High-frequency voltage-controlled oscillator system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011485706.3A CN112653457B (en) | 2020-12-16 | 2020-12-16 | High-frequency voltage-controlled oscillator system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112653457A CN112653457A (en) | 2021-04-13 |
| CN112653457B true CN112653457B (en) | 2023-01-17 |
Family
ID=75354204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011485706.3A Active CN112653457B (en) | 2020-12-16 | 2020-12-16 | High-frequency voltage-controlled oscillator system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112653457B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113611387B (en) * | 2021-07-30 | 2023-07-14 | 清华大学深圳国际研究生院 | Motion quality assessment method based on human body pose estimation and terminal equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5909149A (en) * | 1997-08-29 | 1999-06-01 | Lucent Technologies, Inc. | Multiband phase locked loop using a switched voltage controlled oscillator |
| CN101425803A (en) * | 2007-10-31 | 2009-05-06 | 三星电子株式会社 | Voltage controlled oscillator for loop circuit |
| CN101494449A (en) * | 2008-12-19 | 2009-07-29 | 清华大学深圳研究生院 | Excitation type pulse generator |
| CN110190846A (en) * | 2019-04-15 | 2019-08-30 | 上海酷芯微电子有限公司 | The anti-frequency over shoot circuit of phaselocked loop |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9166603B2 (en) * | 2012-07-10 | 2015-10-20 | Rambus Inc. | Digital calibration for multiphase oscillators |
| CN104202048B (en) * | 2014-08-27 | 2017-05-17 | 中国科学技术大学 | Broadband totally-integrated phase-locked loop frequency synthesizer |
-
2020
- 2020-12-16 CN CN202011485706.3A patent/CN112653457B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5909149A (en) * | 1997-08-29 | 1999-06-01 | Lucent Technologies, Inc. | Multiband phase locked loop using a switched voltage controlled oscillator |
| CN101425803A (en) * | 2007-10-31 | 2009-05-06 | 三星电子株式会社 | Voltage controlled oscillator for loop circuit |
| CN101494449A (en) * | 2008-12-19 | 2009-07-29 | 清华大学深圳研究生院 | Excitation type pulse generator |
| CN110190846A (en) * | 2019-04-15 | 2019-08-30 | 上海酷芯微电子有限公司 | The anti-frequency over shoot circuit of phaselocked loop |
Non-Patent Citations (1)
| Title |
|---|
| "射频锁相环型频率合成器的CMOS 实现";池保勇等;《电子学报》;20041125;第32卷(第11期);正文第1761-1765页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112653457A (en) | 2021-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8564340B2 (en) | Dual phase-locked loop circuit and method for controlling the same | |
| US7876136B2 (en) | Phase-locked-loop circuit having a pre-calibration function and method of pre-calibrating the same | |
| US5889437A (en) | Frequency synthesizer with low jitter noise | |
| JP2013179590A (en) | Phase-locked loop | |
| US8860511B2 (en) | Frequency divider and PLL circuit | |
| JP2011160279A (en) | Phase locked loop circuit and electronic apparatus employing the same | |
| CN114785340A (en) | Frequency band phase-locked loop based on programmable capacitor array | |
| KR20110130330A (en) | A frequency-phase-locked loop with a self-noise suppressing voltage controlled oscillator | |
| US8547150B2 (en) | Phase-locked loop with two negative feedback loops | |
| CN112653457B (en) | High-frequency voltage-controlled oscillator system | |
| US8373511B2 (en) | Oscillator circuit and method for gain and phase noise control | |
| TWI508428B (en) | Current reuse frequency divider and method thereof and voltage control oscillator module and phase lock loop using the same | |
| US9088285B2 (en) | Dynamic divider having interlocking circuit | |
| US9467154B2 (en) | Low power and integrable on-chip architecture for low frequency PLL | |
| CN112242841A (en) | Phase-locked loop circuit with high power supply noise rejection ratio | |
| Chen et al. | A 2 GHz VCO with process and temperature compensation | |
| CN111641409A (en) | Charge pump phase-locked loop circuit | |
| CN111211776B (en) | Phase-locked loop circuit | |
| US20060012414A1 (en) | Circuit and method for generating a polyphase clock signal and system incorporating the same | |
| CN210093195U (en) | Oscillator, phase-locked loop and radar system | |
| US8373465B1 (en) | Electronic device and method for phase locked loop | |
| Karra et al. | An Ultra-low Phase Noise, Low Power 28GHz Frequency Synthesizer for 5G Applications | |
| TWI477080B (en) | Dual phase locked loop and method of controlling the same | |
| CN213426145U (en) | Phase-locked loop circuit with high power supply noise rejection ratio | |
| US20210135676A1 (en) | Iq signal source |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |